Packaging substrate structure and manufacturing method thereof

Abstract

The invention discloses a package substrate structure and a manufacturing method thereof. The packaging substrate structure provided by the invention comprises a core plate, a first seed layer, a core plate circuit layer, an orifice bonding pad, a first resin layer, a second seed layer, an inner circuit layer, a multi-layer composite structure, a solder mask layer and a solder ball. The inner circuit layer adopts a circuit burying process, the first resin layer is etched to form the circuit grooves, and then the inner circuit layer is formed through processing, so that the distance between the circuit grooves and the width of the circuit grooves can be controlled, and a fine circuit with smaller distance is obtained by reducing the distance between the circuit grooves and the width of the circuit grooves, and particularly, a micron-sized circuit can be realized. The problem that in the prior art, a metal layer is etched, so that a thin circuit with a small interval cannot be obtained is solved, resin hole plugging and the thin circuit are achieved, and meanwhile a new structure that the core plate through hole and the outer layer line hole are vertically stacked is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate structure and a manufacturing method thereof. Background Art

[0002] The packaging substrate is an important material used for device packaging. In advanced packaging technology, the cost of the substrate is much higher than that of conventional packaging. The packaging substrate plays an increasingly important role in semiconductor packaging.

[0003] In high-speed signal transmission, due to the high requirements for signal transmission quality, it is necessary to minimize the right-angle bends and corners in the signal transmission line. For multi-layer interconnect packaging substrate structures, high-speed signal transmission requires the core board 01 through holes and interlayer blind holes of the packaging substrate to be vertically stacked. Figure 1-6 As shown, in the process of manufacturing a package substrate structure in the prior art, as Figure 1 As shown, a first copper layer 02 is first formed on the surface of the core board 01; Figure 2 As shown, a resin layer 03 is pressed on the surface of the first copper layer 02, and the resin fills the through holes of the core board 01; Figure 3 As shown, the resin layer 03 is further thinned, thereby retaining the resin in the through hole and exposing the first copper layer 02; Figure 4 As shown, the second copper layer 04 is processed on the surface of the first copper layer 02; Figure 5 As shown, a mask plate 05 is processed on the surface of the second copper layer 04; Figure 6 As shown, the hollow structure of the mask 05 is used for etching, and the first copper layer 02 and the second copper layer are partially etched to form a circuit layer, and the circuit spacing of the circuit layer is L. In the above scheme, after the resin fills the through hole, the surface resin is brushed by a general PCB brushing device to remove the surface resin and expose the resin in the hole, and then the surface is metalized and patterned to form the circuit of the Core layer. In the above scheme, a thicker first copper layer 02 must be formed on the surface of the core board 01 to ensure that the copper layer on the surface of the core board 01 is not torn during the brushing process of the brushing device for the surface resin. In addition, a second copper layer 04 is required after brushing to prevent stress from being formed in a high temperature environment. However, the sum of the thickness of the first copper layer 02 and the second copper layer 04 formed above is generally more than 25μm. In the process of etching the copper layer by etching, due to the excessive thickness of the copper layer, the circuit spacing L generally exceeds 70μm, and it is impossible to manufacture fine circuits with smaller circuit spacing. Summary of the invention

[0004] The purpose of the present application is to provide a packaging substrate structure and a manufacturing method thereof, so as to realize the manufacturing of fine circuits with smaller circuit spacing, and at the same time as realizing resin plugging holes and fine circuits, also realize a new structure of vertical stacking of core board through holes and outer layer circuit holes.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A packaging substrate structure, comprising:

[0007] A core plate having a plurality of through holes, the core plate comprising a first surface and a second surface opposite to each other along a thickness direction thereof;

[0008] a first seed layer, the first seed layer covering the inner wall of the through hole, the area around the opening of the through hole, and the local areas of the first surface and the second surface;

[0009] A core board circuit layer, an orifice pad and a metal conductive layer, wherein the orifice pad covers the first seed layer in the area around the orifice of the through hole, the metal conductive layer covers the first seed layer on the inner wall of the through hole, and the core board circuit layer covers the first seed layer at the remaining position;

[0010] A first resin layer, wherein the first resin layer fills the gap between the through hole of the core board and the circuit layer of the core board, a plurality of circuit grooves are provided on a side of the first resin layer away from the core board, and the circuit grooves opposite to the orifice pads are through grooves, and the remaining circuit grooves are blind grooves;

[0011] A second seed layer and an inner circuit layer are stacked, wherein the second seed layer covers the inner wall of the circuit groove of the first resin layer, the inner circuit layer covers the surface of the second seed layer on one side away from the core board, and the inner circuit layer is embedded in the circuit groove;

[0012] At least one multi-layer composite structure is arranged on a side of the inner circuit layer away from the core board, the multi-layer composite structure comprises a second resin layer, a third seed layer and a circuit layer arranged in sequence in a direction away from the core board, the second resin layer has a through hole, and the third seed layer and the circuit layer are stacked and arranged on a side of the second resin layer away from the core board;

[0013] A solder resist layer, the solder resist layer being arranged on a side of the multi-layer composite structure away from the core board;

[0014] A solder ball is disposed on the solder resist layer, and a bottom of the solder ball passes through the solder resist layer and contacts the outermost circuit layer.

[0015] In one implementation, the first resin layer and / or the second resin layer includes ABF resin and / or RCC.

[0016] In one implementation, the first seed layer, the second seed layer and / or the third seed layer include at least one sub-metal layer; or,

[0017] The first seed layer, the second seed layer and / or the third seed layer include multiple sub-metal layers, and the multiple sub-metal layers are made of different materials.

[0018] In one implementation, the sub-metal layer is made of titanium, copper or tungsten.

[0019] In one implementation, the solder balls include chip solder balls and substrate solder balls, the chip solder balls are arranged on the solder resist layer on one side of the core board, the substrate solder balls are arranged on the solder resist layer on the other side of the core board, the chip solder balls are used to bond with the chip, and the substrate solder balls are used to bond with the printed circuit board;

[0020] The side of the chip solder ball facing away from the core board has a flat surface; and / or the side of the substrate solder ball facing away from the core board is a spherical surface.

[0021] In the above-mentioned packaging substrate structure, the buried circuit manufacturing technology is adopted in the process of forming the inner circuit layer, that is, a circuit groove is formed in the first resin layer, and a deep hole is formed in the part of the circuit groove opposite to the hole opening of the through hole, and the depth of the deep hole reaches the hole opening pad, and the deep hole covers the entire surface of the pad and the hole opening of the plugging resin. In the manufacture of the inner circuit layer, the vertical stacking of the inner circuit layer and the hole opening pad is realized, and all subsequent circuit layers are stacked in a vertical stacking manner at the through hole. Since the inner circuit layer adopts the buried circuit process, the circuit groove is first etched in the first resin layer, and then the inner circuit layer is formed by processing, so that the spacing of the circuit grooves and the width of the circuit grooves can be controlled, and by reducing the spacing between the circuit grooves and the width of the circuit grooves, a fine circuit with a smaller spacing can be obtained, and specifically a micron-level circuit can be realized. This solves the problem in the prior art that the metal layer is etched, so that a fine circuit with a smaller spacing cannot be obtained. In addition, during the manufacturing process of the inner layer circuits, only resin plugging holes and core board circuit layers are done. The resin surface of the core board through-holes does not have the metal coverage of conventional resin plugging holes. The inner circuit layer covers the hole pads, and the through holes corresponding to the multiple circuit layers are vertically stacked with the through-holes of the core board. All circuit layers have vertically stacked hole pads, which not only realizes resin plugging holes and fine circuits, but also realizes a new structure of vertical stacking of core board through-holes and outer layer circuit holes.

[0022] A method for manufacturing a package substrate structure, comprising:

[0023] The core plate has a plurality of through holes, wherein the core plate has a first surface and a second surface opposite to each other;

[0024] forming a first seed layer on the surface of the core plate with the through hole;

[0025] forming a first mask on the surface of the structure formed in the previous step, wherein the first mask has a hollow structure, and the hollow structure of the first mask is at least opposite to the through hole of the structure formed in the previous step and the area around the opening of the through hole;

[0026] A core circuit layer, an orifice pad and a metal conductive layer are formed, a first metal layer is formed in the hollow structure of the first mask, and the first metal layer covers the inner wall of the through hole and the area around the orifice of the through hole, the first metal layer in the area around the orifice of the through hole forms the orifice pad, the first metal layer covering the inner wall of the through hole forms the metal conductive layer, and the first metal layer at the remaining position except the inner wall of the through hole and the area around the orifice of the through hole forms the core circuit layer;

[0027] removing the first mask and the first seed layer covered by the first mask;

[0028] Plug the holes and press the resin, press the resin on the first surface and the second surface of the core board, so that the resin fills the gap between the through hole of the core board and the circuit layer of the core board, and forms a first resin layer on the first surface and the second surface of the structure formed in the previous step;

[0029] forming a plurality of circuit grooves, wherein a plurality of circuit grooves are formed on the first resin layer, and the circuit grooves opposite to the through holes extend from the first resin layer to the orifice pad;

[0030] forming a second seed layer on the surface of the structure formed in the previous step;

[0031] forming a second metal layer, and forming the second metal layer on the surface of the second seed layer;

[0032] forming an inner circuit layer, removing the portion of the second metal layer not embedded in the circuit groove, and retaining the portion of the second metal layer embedded in the circuit groove to form an inner circuit layer;

[0033] Forming a second resin layer, pressing resin on both the first surface and the second surface of the structure formed in the previous step to form the second resin layer;

[0034] Drilling, processing through holes on the second resin layer;

[0035] forming a third seed layer on the surface of the structure formed in the previous step;

[0036] forming a fourth mask on the surface of the structure formed in the previous step;

[0037] forming a circuit layer, wherein the circuit layer is formed in the hollow structure of the fourth mask;

[0038] removing the fourth mask and the third seed layer covered by the fourth mask;

[0039] Repeating the step of forming a second resin layer at least once until the fourth mask and the third seed layer covered by the fourth mask are removed, so as to form at least one circuit layer;

[0040] Making a solder resist layer on the first surface and the second surface of the structure formed in the previous step, wherein the solder resist layer has connection holes corresponding to the circuit layer;

[0041] Ball planting: solder balls on the first surface and / or second surface of the structure formed in the previous step.

[0042] In one implementation, plugging the holes and pressing the resin comprises:

[0043] Plug the holes, and press the resin on the first surface and the second surface of the core board so that the resin fills the gap between the through hole of the core board and the circuit layer of the core board;

[0044] Thinning the pressed resin layer so that the resin does not cover the core board circuit layer and the orifice pad, and the thinned resin layer is flush with the orifice pad and the core board circuit layer or the core board circuit layer and the orifice pad are higher than the resin layer;

[0045] The resin is pressed again to form a first resin layer.

[0046] In one implementation, the thinning of the laminated resin layer includes: thinning the laminated resin by chemical mechanical polishing so that the resin does not cover the core board circuit layer and the hole pad; and / or the resin used in the plugging and resin laminating step includes ABF resin and / or RCC.

[0047] In one implementation, the step of forming a line groove includes:

[0048] forming a metal protective layer, wherein the metal protective layer is formed on both the first surface and the second surface of the structure formed in the previous step;

[0049] forming a second mask on the surface of the structure formed in the previous step, wherein the second mask has a hollow structure;

[0050] removing the metal protection layer not covered by the second mask;

[0051] Etching the first surface and the second surface of the structure formed in the previous step to form a circuit groove, so that the depth of the circuit groove extends from the metal protection layer to the first resin layer, and removing the second mask;

[0052] Forming a third mask, forming a third mask on the surface of the structure formed in the previous step, wherein the hollow structure of the third mask is opposite to the opening of the through hole and the surrounding area;

[0053] Etching the first surface and the second surface of the structure formed in the previous step, deepening the line groove opposite to the opening of the through hole and the surrounding area, the line groove opposite to the through hole extends from the metal protection layer to the opening pad, and removing the third mask;

[0054] Remove the metal protective layer.

[0055] In one implementation, in the step of forming the inner circuit layer, the portion of the second metal layer not embedded in the circuit groove is removed, specifically by using chemical mechanical polishing to remove the portion of the second metal layer not embedded in the circuit groove.

[0056] Compared with the prior art, the beneficial effects of the method for manufacturing the packaging substrate structure provided in the present application are the same as the beneficial effects of the above-mentioned packaging substrate structure, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0058] Figure 1 It is a schematic diagram of forming the first copper layer in the process of manufacturing a package substrate structure in the prior art;

[0059] Figure 2 It is a schematic diagram of forming a resin layer in the process of manufacturing a packaging substrate structure in the prior art;

[0060] Figure 3 It is a schematic diagram of the process of manufacturing the packaging substrate structure in the prior art after the resin layer is thinned;

[0061] Figure 4 It is a schematic diagram of the process of manufacturing a packaging substrate structure in the prior art after depositing a metal layer;

[0062] Figure 5 It is a schematic diagram of etching a mask in the process of manufacturing a packaging substrate structure in the prior art;

[0063] Figure 6 It is a schematic diagram of the process of manufacturing a packaging substrate structure in the prior art after forming a circuit layer;

[0064] Figure 7 A flow chart of a method for manufacturing a packaging substrate structure provided in an embodiment of the present application;

[0065] Figure 8 A cross-sectional view of a core plate after a through hole is provided in an embodiment of the present application;

[0066] Fig. 9 A cross-sectional view of a core board provided in an embodiment of the present application after the copper layer is removed;

[0067] Fig.10 A top view of the core board provided in an embodiment of the present application after the copper layer is removed;

[0068] Fig.11A cross-sectional view after forming a first seed layer provided in an embodiment of the present application;

[0069] Fig.12 A cross-sectional view after forming a first mask provided in an embodiment of the present application;

[0070] Fig.13 A cross-sectional view after forming a core board circuit layer and an orifice pad provided in an embodiment of the present application;

[0071] Fig.14 A cross-sectional view after removing the first mask provided in an embodiment of the present application;

[0072] Fig.15 A cross-sectional view after removing a first seed layer covered by a mask provided in an embodiment of the present application;

[0073] Fig.16 A structural diagram of the plugging hole and the first resin pressing step provided in an embodiment of the present application;

[0074] Fig.17 A cross-sectional view of the plugging hole and the first resin pressing step after the resin is thinned according to the embodiment of the present application;

[0075] Fig.18 A cross-sectional view after forming a first resin layer provided in an embodiment of the present application;

[0076] Fig.19 A cross-sectional view after a metal protective layer is formed according to an embodiment of the present application;

[0077] Fig. 20 A cross-sectional view after forming a second mask provided in an embodiment of the present application;

[0078] Fig.21 A cross-sectional view of removing the metal protection layer not covered by the second mask provided in an embodiment of the present application;

[0079] Fig. 22 A cross-sectional view of a structure formed in the process of forming a circuit groove provided in an embodiment of the present application;

[0080] Fig.23 A cross-sectional view after forming a third mask provided in an embodiment of the present application;

[0081] Fig.24 A cross-sectional view of an embodiment of the present application showing a circuit groove opposite to a through hole extending from a metal protective layer to an orifice pad;

[0082] Fig.25 A cross-sectional view after removing the metal protective layer provided in an embodiment of the present application;

[0083] Fig.26A cross-sectional view after forming a second seed layer provided in an embodiment of the present application;

[0084] Fig. 27 A cross-sectional view after forming a second metal layer provided in an embodiment of the present application;

[0085] Fig.28 A cross-sectional view after forming an inner circuit layer provided in an embodiment of the present application;

[0086] Fig.29 A cross-sectional view after forming a second resin layer provided in an embodiment of the present application;

[0087] Fig.30 A cross-sectional view after drilling provided in an embodiment of the present application;

[0088] Fig.31 A cross-sectional view after forming a third seed layer provided in an embodiment of the present application;

[0089] Fig.32 A cross-sectional view after forming a fourth mask provided in an embodiment of the present application;

[0090] Fig.33 A cross-sectional view after forming a circuit layer provided in an embodiment of the present application;

[0091] Fig.34 A cross-sectional view after removing the fourth mask provided in an embodiment of the present application;

[0092] Fig.35 A cross-sectional view after removing the third seed layer covered by the fourth mask provided in an embodiment of the present application;

[0093] Fig.36 A cross-sectional view of the embodiment of the present application after repeating the third resin pressing step at least once - removing the fourth mask and the third seed layer covered by the fourth mask;

[0094] Fig.37 A cross-sectional view after the solder mask layer is manufactured according to an embodiment of the present application;

[0095] Fig.38 A cross-sectional view after ball implantation provided in an embodiment of the present application.

[0096] Reference numerals:

[0097] 01-core board, 02-first copper layer, 03-resin layer, 04-second copper layer, 05-mask;

[0098] 1-core board, 1a-through hole, 2-first seed layer, 3-first mask, 4-core board circuit layer, 5-orifice pad, 5a-metal conductive layer, 6-first resin layer, 6a-circuit groove, 7-metal protective layer, 8-second mask, 9-third mask, 10-second seed layer, 11-second metal layer, 12-inner circuit layer, 13-second resin layer, 13a-through hole, 14-third seed layer, 15-fourth mask, 16-circuit layer, 17-solder resist layer, 18-chip solder ball, 19-substrate solder ball. DETAILED DESCRIPTION

[0099] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0100] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0101] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0102] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0103] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0104] like Fig.37 As shown, an embodiment of the present application provides a package substrate structure, which can be manufactured by any of the following manufacturing methods of the package substrate structure. The package substrate structure provided by the present application includes a core board 1, a first seed layer 2, a core board circuit layer 4, an orifice pad 5, a metal conductive layer 5a, a first resin layer 6, a second seed layer 10, an inner circuit layer 12, a multi-layer composite structure, a solder resist layer 17, and solder balls. Among them, the first seed layer 2, the core board circuit layer 4, the first resin layer 6, the second seed layer 10, the inner circuit layer 12, the multi-layer composite structure, and the solder resist layer 17 on both sides of the core board 1 are symmetrically arranged.

[0105] Among them, the core board 1 has a plurality of through holes 1a, and the core board 1 includes a first surface and a second surface opposite to each other along its thickness direction. The first surface can be an upper surface, and the second surface can be a lower surface. The through hole 1a runs through the thickness of the core board 1, one opening of the through hole 1a is located on the first surface, and the other opening of the through hole 1a is located on the second surface. The first seed layer 2 covers the inner wall of the through hole 1a of the core board 1 and the area around the opening of the through hole 1a, that is, the area around the opening on the first surface and the area around the opening on the second surface are both covered by the first seed layer 2. The first seed layer 2 also covers a local area of ​​the first surface and the second surface of the core board 1, and the local area refers to the area used to form the core board circuit layer 4.

[0106] The orifice pad 5 covers the first seed layer 2 in the area around the orifice of the through hole 1a, the metal conductive layer 5a covers the first seed layer 2 on the inner wall of the through hole 1a, and the core board circuit layer 4 covers the first seed layer 2 in the remaining positions. Among them, the orifice pad 5 is used to be electrically connected to the inner circuit layer 12. The orifice pad 5 is a metal layer, and the core board circuit layer 4 is also a metal layer. Among them, the metal layer can be a single layer of metal, and the material of the single layer of metal can be metals such as copper, tungsten or titanium. Of course, the metal layer can also include multiple sub-metal layers, and the materials of the multiple sub-metal layers can be the same or different. For example, the material of the sub-metal layer can be copper, tungsten or titanium. The thickness of the multiple sub-metal layers can be the same or different.

[0107] The first resin layer 6 fills the gap between the through hole 1a of the core board 1 and the core board circuit layer 4, and the first resin layer 6 also fills the gap between the orifice pad 5 and the core board circuit layer 4. A plurality of circuit grooves 6a are provided on the side of the first resin layer 6 facing away from the core board 1, and the circuit groove 6a opposite to the orifice pad 5 is a through groove, and the remaining circuit grooves 6a are blind grooves. That is, the circuit groove 6a opposite to the orifice pad 5 is through along the thickness direction of the first resin layer 6. The notches of the remaining circuit grooves 6a except the circuit groove 6a opposite to the orifice pad 5 are located on the surface of the side of the first resin layer 6 facing away from the core board 1, and the bottoms of the remaining circuit grooves 6a are located in the first resin layer 6. In addition, the material filling the through hole 1a of the core board 1 is a plugging material. The material of the plugging material and the material filling the gap between the core board circuit layers 4 can be the same, so that the gap between the core board circuit layers 4 can be filled while plugging the hole, simplifying the processing technology.

[0108] The second seed layer 10 and the inner circuit layer 12 are stacked. Specifically, the second seed layer 10 covers the inner wall of the circuit groove 6a, and the inner circuit layer 12 covers the surface of the second seed layer 10 on one side away from the first resin layer 6, and the inner circuit layer 12 is embedded in the circuit groove 6a. That is, the second seed layer 10 and the inner circuit layer 12 are both embedded in the circuit groove 6a, and the second seed layer 10 is located between the inner circuit layer 12 and the inner wall of the circuit groove 6a. The portion of the inner circuit layer 12 located in the circuit groove 6a opposite to the orifice pad 5 is electrically connected to the orifice pad 5. The surface of the inner circuit layer 12 can be flush with the first resin layer 6, or the surface of the inner circuit layer 12 is higher than the surface of the first resin layer 6.

[0109] At least one multilayer composite structure is arranged on the side of the inner circuit layer 12 away from the core board 1, and the multilayer composite structure includes a second resin layer 13, a third seed layer 14 and a circuit layer 16 arranged in sequence in a direction away from the core board 1. The second resin layer 13 has a through hole 13a, and the third seed layer 14 and the circuit layer 16 are stacked and arranged on the side of the second resin layer 13 away from the core board 1. The multilayer composite structure is arranged on the side of the inner circuit layer 12 away from the core board 1. When multiple multilayer composite structures are arranged on the upper side or the lower side of the core board 1, the multiple multilayer composite structures are stacked in sequence. Alternatively, a multilayer composite structure can also be arranged on the upper side or the lower side of the core board 1. The multilayer composite structure includes a second resin layer 13, a third seed layer 14 and a circuit layer 16 arranged in sequence in a direction away from the core board 1, and the second resin layer 13 has a through hole 13a, and the third seed layer 14 and the circuit layer 16 are stacked and arranged on the side of the second resin layer 13 away from the core board 1. The plurality of through holes 13 a may be respectively opposite to the plurality of orifice pads 5 , so as to facilitate the connection of the inner circuit layer 12 with the circuit layer through the through holes 13 a .

[0110] The materials of the first resin layer 6 and the second resin layer 13 may be the same or different. When the materials of the first resin layer 6 and the second resin layer 13 are the same, the boundary between the first resin layer 6 and the second resin layer 13 may not be obvious, but the first resin layer 6 and the second resin layer 13 form an integral resin layer.

[0111] The solder resist layer 17 is arranged on the side of the multilayer composite structure away from the core board 1. The solder resist layer 17 has a connection hole corresponding to the circuit layer 16, and the connection hole is used to connect with the solder ball. The solder ball is arranged on the solder resist layer 17, and the bottom of the solder ball passes through the solder resist layer 17 and contacts the outermost circuit layer. The solder ball may include a chip solder ball 18 and a substrate solder ball 19, wherein the chip solder ball 18 is arranged on the solder resist layer 17 on one side of the core board, and the substrate solder ball 19 is arranged on the solder resist layer 17 on the other side of the core board 1, the chip solder ball 18 is used to bond with the chip, and the substrate solder ball 19 is used to bond with the printed circuit board.

[0112] In the above-mentioned package substrate structure, the buried circuit manufacturing technology is adopted in the process of forming the inner circuit layer 12, that is, a circuit groove 6a is formed in the first resin layer 6, and a deep hole is formed in the part of the circuit groove 6a opposite to the hole opening of the through hole 1a, and the depth of the deep hole reaches the hole opening pad 5, and the deep hole covers the entire surface of the pad and the hole opening of the plugging resin. In the manufacture of the inner circuit layer 12, the vertical stacking of the inner circuit layer 12 and the hole opening pad 5 is realized, and all subsequent circuit layers 16 are stacked in a vertical stacking manner at the through hole 1a. Since the inner circuit layer 12 adopts the buried circuit process, the circuit groove 6a is first etched in the first resin layer 6, and then the inner circuit layer 12 is formed by processing, so that the spacing of the circuit grooves 6a and the width of the circuit grooves 6a can be controlled, and by reducing the spacing between the circuit grooves 6a and the width of the circuit grooves 6a, a fine circuit with a smaller spacing can be obtained, and specifically a micron-level circuit can be realized. It solves the problem in the prior art that the metal layer is etched, so that a fine circuit with a smaller spacing cannot be obtained. In addition, during the manufacturing process of the inner layer circuit, only resin plugging holes and core board circuit layers are made. The surface of the core board through-hole resin is not covered with metal like conventional resin plugging holes. The inner circuit layer 12 covers the hole opening pad 5, and the through holes corresponding to the multiple circuit layers are vertically stacked with the through holes 1a of the core board. All circuit layers 16 are vertically stacked with the hole opening pad 5. While realizing resin plugging holes and fine circuits, a new structure of vertical stacking of core board through holes and outer layer circuit holes is also realized.

[0113] In a specific embodiment, the first resin layer 6 may include a build-up film such as ABF (ABF Ajinomoto Build-up Film) resin and / or RCC (Resin Coated Copper) material. And / or the second resin layer 13 may include a build-up film such as ABF resin and / or RCC (Resin Coated Copper) material. Of course, the first resin layer 6 and the second resin layer 13 may also be made of other materials, such as RCC and / or photosensitive dry film insulation layer material.

[0114] The first seed layer 2, the second seed layer 10 and / or the third seed layer 14 include at least one sub-metal layer. That is, the first seed layer 2, the second seed layer 10 and / or the third seed layer 14 can be a single layer of metal, and the material of the single layer of metal can be copper, tungsten or titanium. Of course, the first seed layer 2, the second seed layer 10 and / or the third seed layer 14 can also include multiple sub-metal layers, and the materials of the multiple sub-metal layers can be the same or different. For example, the material of the sub-metal layer can be copper, tungsten or titanium. The thickness of the multiple sub-metal layers can be the same or different.

[0115] The chip solder ball 18 is used for bonding with the chip, and the side of the chip solder ball 18 facing away from the core board 1 has a flat surface to facilitate bonding with the chip.

[0116] The substrate solder ball 19 is used for bonding with the printed circuit board. The side of the substrate solder ball 19 facing away from the core board 1 is a spherical surface to facilitate bonding with the printed circuit board.

[0117] See also Figure 7 The present application also provides a method for manufacturing a package substrate structure, including the following steps:

[0118] S1: a core plate 1 is opened, a plurality of through holes 1a are opened on the core plate 1, and the core plate 1 has a first surface and a second surface opposite to each other;

[0119] like Figure 8-Figure 10 As shown, specifically, along the thickness direction, the core plate 1 has a first surface and a second surface opposite to each other, and the first surface and the second surface are both perpendicular to the thickness direction of the core plate 1. A plurality of through holes 1a are provided on the core plate 1 that penetrate the thickness thereof, one opening of the through hole 1a is located on the first surface, and the other opening of the through hole 1a is located on the second surface.

[0120] In this step, if Figure 8 As shown, the core board 1 can be a double-sided copper-clad board, and before the through hole 1a is formed, the copper layer on both sides of the double-sided copper-clad board is removed. In addition, in this step, the through hole 1a can be formed by laser.

[0121] S2: forming a first seed layer 2, forming the first seed layer 2 on the surface of the core board 1 with the through hole 1a;

[0122] like Fig.11 As shown, a first seed layer 2 is formed on the surface of the core board 1 after the hole is opened in step S1, and the first seed layer 2 covers the first surface, the second surface and the inner wall of the through hole 1a of the core board 1. Optionally, the first seed layer 2 can be formed by deposition, electroplating, etc.

[0123] In this way, a regular, dense and smooth first seed layer 2 is formed on the surface of the core plate 1, which has good brightness and level distribution, so that the adhesion between the electrolyte and the metal is enhanced and the surface uniformity of the deposit is promoted.

[0124] S3: forming a first mask 3 on the surface of the structure formed in the previous step, wherein the first mask 3 has a hollow structure, and the hollow structure of the first mask 3 is at least opposite to the through hole 1a of the structure formed in the previous step and the area around the opening of the through hole 1a;

[0125] like Fig.12 As shown, a first mask 3 is formed on the surface of the structure formed in step S2. Specifically, the first mask 3 is formed on both the first surface and the second surface of the structure formed in step S2. Among them, the first surface can be an upper surface, and the second surface can be a lower surface. The first mask 3 has a hollow structure, and the hollow structure of the first mask 3 is at least opposite to the through hole 1a of the structure formed in the previous step and the area around the opening of the through hole 1a. That is, at least the inner wall of the through hole 1a and the area around the opening of the through hole 1a are not covered by the first mask 3, and the remaining local positions of the first surface and the second surface are also not covered by the first mask 3. The inner wall of the through hole 1a and the area around the opening of the through hole 1a are used to form the opening pad 5, and the remaining areas of the first surface and the second surface not covered by the first mask 3 are used to form the core board circuit layer 4.

[0126] In this step, the first mask 3 can be formed on the surface of the structure formed in the previous step by using a photolithography method to make an electroplating mask. Specifically, a dry film is first pressed on the first surface and the second surface of the structure formed in the previous step, and then exposure and development are performed in sequence to finally form the first mask 3. The material of the dry film is a photosensitive polymer material. Of course, other methods can also be used to form the first mask 3, which is not limited here.

[0127] S4: forming a core circuit layer 4, an orifice pad 5 and a metal conductive layer 5a, forming a first metal layer in the hollow structure of the first mask 3, and the first metal layer covers the inner wall of the through hole 1a and the area around the orifice of the through hole 1a, the first metal layer in the area around the orifice of the through hole 1a forms the orifice pad 5, the first metal layer covering the inner wall of the through hole 1a forms the metal conductive layer, and the first metal layer in the remaining positions except the inner wall of the through hole 1a and the area around the orifice of the through hole 1a forms the core circuit layer 4;

[0128] like Fig.13As shown, in this step, a first metal layer is formed on the inner wall of the through hole 1a of the core board 1 and the area around the opening of the through hole 1a, as well as the remaining areas of the first surface and the second surface that are not covered by the first mask 3. Specifically, the first metal layer can be formed on the inner wall of the through hole 1a and the area around the opening of the through hole 1a by electroplating, deposition, etc. The portion of the first metal layer located in the area around the opening of the through hole 1a is the opening pad 5, which is used to connect the inner circuit layer 12. The portion of the first metal factory covering the inner wall of the through hole 1a forms a metal conductive layer, and the portion of the first metal layer located in the first surface and the second surface that are not covered by the first mask 3 is the core board circuit layer 4.

[0129] In this step, the first metal layer may be a single metal layer, and the material of the single metal layer may be copper, tungsten, titanium or other metals. Of course, the first metal layer may also include multiple sub-metal layers, and the materials of the multiple sub-metal layers may be the same or different, for example, the material of the sub-metal layer may be copper, tungsten or titanium. The thicknesses of the multiple sub-metal layers may be the same or different.

[0130] S5: removing the first mask 3 and the first seed layer 2 covered by the first mask 3;

[0131] like Figure 14-15 As shown, the first mask 3 and the first seed layer 2 covered by the first mask 3 are removed, and the first metal layer and the first seed layer 2 covered by the first metal layer are retained.

[0132] In this step, the first mask 3 and the first seed layer 2 covered by the first mask 3 can be removed in two steps, that is, the first mask 3 is first removed, and then the first seed layer 2 covered by the first mask 3 is removed. Specifically, the first mask 3 can be directly peeled off by stripping, and then the first seed layer 2 covered by the first mask 3 can be removed by wet etching or laser etching.

[0133] S6: plugging holes and pressing resin, pressing resin on both the first surface and the second surface of the core board 1, so that the resin fills the gap between the through hole 1a of the core board 1 and the core board circuit layer 4, and forms a first resin layer 6 on the first surface and the second surface of the structure formed in the previous step;

[0134] In this step, the resin is pressed so that the resin fills the through hole 1a of the core board 1, the gap between the core board circuit layer 4, and the gap between the hole pad 5 and the core board circuit layer 4, and a first resin layer 6 is formed on the first surface and the second surface of the structure formed in the previous step.

[0135] Further S6 plugging and pressing the resin includes the steps of:

[0136] S6a: plugging the holes, pressing resin on the first surface and the second surface of the core board 1 so that the resin fills the gap between the through hole 1a of the core board 1 and the core board circuit layer 4.

[0137] like Fig.16 As shown, in this step, the through hole 1a is filled with resin, that is, the through hole 1a is filled with resin. The resin is pressed on the first surface and the second surface of the core board 1 to form a resin layer on the first surface and the second surface of the core board 1. In this step, the resin used for plugging the hole includes ABF resin, PP prepreg and / or PI material and other build-up adhesive films.

[0138] S6b: thinning the pressed resin layer so that the resin does not cover the core board circuit layer 4 and the hole pad 5 , and the thinned resin layer is flush with the hole pad 5 and the core board circuit layer 4 .

[0139] like Fig.17 As shown, the resin layer can be thinned by a grinding wheel, or by chemical mechanical polishing, and further, CMP (Chemical Mechanical Polishing) can be performed after thinning to remove small scratches on the surface. The resin does not cover the core board circuit layer 4 and the orifice pad 5, that is, the resin layer is thinned until the core board circuit layer 4 and the orifice pad 5 are exposed from the resin layer, and the resin layer can be flush with the core board circuit layer 4 and the orifice pad 5, or the core board circuit layer 4 and the orifice pad 5 are higher than the resin layer, so that the first surface and the second surface of the structure are smoother.

[0140] S6c: The resin is pressed again to form a first resin layer 6 .

[0141] like Fig.18 As shown, the resin is pressed again on the core board circuit layer 4 , the orifice pad 5 and the resin layer formed in the previous step on the side facing away from the core board 1 to form a first resin layer 6 .

[0142] In the above steps S6a-S6c, the first resin layer 6 is formed by laminating the resin twice. The first laminating of the resin in step S6a ensures that the density of the resin in the through hole 1a is large enough to prevent the occurrence of short circuit between layers and ensure the transmission of signals. The second laminating of the resin in step S6c ensures the density of the first resin layer 6 and the insulation between layers.

[0143] S7 : forming a wiring groove 6 a . A plurality of wiring grooves 6 a are formed on the first resin layer 6 . The wiring grooves 6 a opposite to the through holes 1 a extend from the first resin layer 6 to the orifice pads 5 .

[0144] Specifically, the circuit groove 6a opposite to the orifice pad 5 is a through groove, and the other circuit grooves 6a are blind grooves. That is, the circuit groove 6a opposite to the orifice pad 5 penetrates along the thickness direction of the first resin layer 6. The groove openings of the other circuit grooves 6a except the circuit groove 6a opposite to the orifice pad 5 are located on the side surface of the first resin layer 6 away from the core board 1, and the groove bottoms of the other circuit grooves 6a are located in the first resin layer 6.

[0145] Furthermore, the process of forming the line groove 6a in step S7 specifically includes:

[0146] S7a: forming a metal protection layer 7, forming a metal protection layer 7 on both the first surface and the second surface of the structure formed in the previous step;

[0147] like Fig.19 As shown, a metal protective layer 7 is formed on the surface of the first resin layer 6 facing away from the core board 1. The metal protective layer 7 can be formed by magnetron sputtering or chemical plating. The metal protective layer 7 can be a single layer of metal, in which case the metal protective layer 7 can be a copper layer. Alternatively, the metal protective layer 7 can also include a copper layer and a titanium layer stacked in sequence, and the titanium layer is located between the first resin layer 6 and the copper layer.

[0148] The thickness of the metal protective layer 7 is 0.1-μm-1 μm. When the metal protective layer 7 includes only a copper layer, the thickness of the metal protective layer 7 is 0.3-μm-1 μm; when the metal protective layer 7 includes only a copper layer and a titanium layer, the thickness of the metal protective layer 7 is 0.1-μm-1 μm. Exemplarily, the thickness of the metal protective layer 7 is 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm.

[0149] S7b: forming a second mask 8, forming the second mask 8 on the surface of the structure formed in the previous step, the second mask 8 having a hollow structure;

[0150] like Fig. 20 As shown, a second mask 8 is formed on the surface of the structure formed in step S7a. Specifically, the second mask 8 is formed on both the first surface and the second surface of the structure formed in step S7a. The first surface may be an upper surface, and the second surface may be a lower surface. The second mask 8 covers the first surface and the second surface of the structure formed in the previous step, and the second mask 8 has a hollow structure.

[0151] In this step, the second mask 8 can be formed on the surface of the structure formed in the previous step by using a photolithography method to make an electroplating mask. Specifically, a dry film is first pressed on the first surface and the second surface of the structure formed in the previous step, and then exposure and development are performed in sequence to finally form the second mask 8. The material of the dry film is a photosensitive polymer material. Of course, other methods can also be used to form the second mask 8, which is not limited here.

[0152] S7c: removing the metal protection layer 7 not covered by the second mask 8;

[0153] like Fig.21As shown, the metal protection layer 7 not covered by the second mask 8 can be removed by dry etching or laser etching process, and the metal protection layer 7 covered by the second mask 8 is retained.

[0154] S7d: etching the first surface and the second surface of the structure formed in the previous step to form a circuit groove 6a, so that the depth of the circuit groove 6a extends from the metal protection layer 7 to the first resin layer 6, and removing the second mask 8;

[0155] like Fig. 22 As shown, the line groove 6a can be formed by dry etching or laser etching. Specifically, the line groove 6a on the first surface can be etched first, and then the line groove 6a on the second surface can be etched. The depth of the line groove 6a formed in step S7d relative to the surrounding area of ​​the through hole 1a has not reached the hole pad 5, and the depth of the line groove 6a extends from the metal protective layer 7 to the first resin layer 6, that is, all the line grooves 6a formed in this step are blind grooves.

[0156] In step S7d, the second mask 8 is also removed. The second mask 8 and the circuit groove 6a may be formed simultaneously, or the circuit groove 6a may be formed first and then the second mask 8 may be removed.

[0157] S7e: forming a third mask 9, forming the third mask 9 on the surface of the structure formed in the previous step, the hollow structure of the third mask 9 is opposite to the opening of the through hole 1a and the surrounding area;

[0158] like Fig.23 As shown, a third mask 9 is formed on the surface of the structure formed in step S7d. Specifically, the third mask 9 is formed on both the first surface and the second surface of the structure formed in step S7d. The first surface may be an upper surface, and the second surface may be a lower surface. The third mask 9 covers the first surface and the second surface of the structure formed in the previous step. The third mask 9 has a hollow structure. The hollow structure of the third mask 9 is opposite to the opening of the through hole 1a and the surrounding area.

[0159] In this step, the third mask 9 can be formed on the surface of the structure formed in the previous step by using a photolithography method to make an electroplating mask. Specifically, a dry film is first pressed on the first surface and the second surface of the structure formed in the previous step, and then exposure and development are performed in sequence to finally form the third mask 9. The material of the dry film is a photosensitive polymer material. Of course, other methods can also be used to form the third mask 9, which is not limited here.

[0160] S7f: etching the first surface and the second surface of the structure formed in the previous step, deepening the line groove 6a opposite to the opening of the through hole 1a and the surrounding area, the line groove 6a opposite to the through hole 1a extends from the metal protection layer 7 to the opening pad 5, and removing the third mask 9,

[0161] like Fig.24 As shown, dry etching or laser etching is used to etch the area not covered by the third mask 9, that is, the area within the hollow structure of the third mask 9 is etched to deepen the line groove 6a opposite to the opening of the through hole 1a and the surrounding area, so that the line groove 6a opposite to the through hole 1a extends from the metal protective layer 7 to the opening pad 5. Specifically, in step S7d, the third mask 9 does not cover the line groove 6a opposite to the opening and the surrounding area, and the line groove 6a is opposite to the hollow structure of the third mask 9. In the process of step S7f, the line groove 6a opposite to the opening of the through hole 1a and the surrounding area is etched to deepen the depth of the line groove 6a opposite to the opening of the through hole 1a and the surrounding area until it becomes a through groove, so that the opening pad 5 is exposed in the line groove 6a opposite to the opening of the through hole 1a and the surrounding area, which is conducive to the connection of the opening pad 5 with the inner circuit layer 12.

[0162] S7g: removing the metal protective layer 7.

[0163] like Fig.25 As shown, the metal protection layer 7 can be removed by etching, and a complete circuit groove 6a is formed on the surface of the first resin layer 6.

[0164] During the above steps S7a-S7g, two etching processes are used to form line grooves 6a with different depths, so that the line groove 6a opposite to the opening of the through hole 1a and the surrounding area is a through groove, and the depth extends to the opening pad 5; at the same time, the remaining line grooves 6a not opposite to the opening of the through hole 1a and the surrounding area are blind grooves, and the depth is shallower.

[0165] S8: forming a second seed layer 10, forming the second seed layer 10 on the surface of the structure formed in the previous step;

[0166] like Fig.26 As shown, a second seed layer 10 is formed on the surface of the structure formed in step S7, specifically, the second seed layer 10 is formed on the surface of the first resin layer 6 of the structure formed in the previous step away from the core board 1, and the second seed layer 10 covers the surface of the first resin layer 6 away from the core board 1 and the inner wall of the circuit groove 6a. Optionally, the second seed layer 10 can be formed by deposition, electroplating, etc.

[0167] S9: forming a second metal layer 11, forming the second metal layer 11 on the surface of the second seed layer 10;

[0168] like Fig. 27 As shown, in this step, a second metal layer 11 is formed on the side of the second seed layer 10 away from the core board 1, a part of the second metal layer 11 is embedded in the circuit groove 6a, and at the same time, a metal layer is formed on the side of the first resin layer 6 away from the core board 1. Specifically, the second metal layer 11 can be formed by electroplating, deposition, etc.

[0169] In this step, the second metal layer 11 can be a single metal layer, and the material of the single metal layer can be copper, tungsten, titanium or other metals. Of course, the second metal layer 11 can also include multiple sub-metal layers, and the materials of the multiple sub-metal layers can be the same or different. For example, the material of the sub-metal layer can be copper, tungsten or titanium. The thickness of the multiple sub-metal layers can be the same or different.

[0170] S10: forming an inner circuit layer 12, removing the portion of the second metal layer 11 not embedded in the circuit groove 6a, and retaining the portion of the second metal layer 11 embedded in the circuit groove 6a to form the inner circuit layer 12;

[0171] like Fig.28 As shown, in this step, the second metal layer 11 outside the circuit groove 6a can be removed by chemical mechanical polishing or etching, that is, the part of the second metal layer 11 not embedded in the circuit groove 6a is removed by chemical mechanical polishing, and the part of the second metal layer 11 embedded in the circuit groove 6a is retained to form the inner circuit layer 12. In this step, the inner circuit layer 12 is embedded in the circuit groove 6a, and the inner circuit layer 12 in the circuit groove 6a in the orifice and the surrounding area is connected to the orifice pad 5.

[0172] S11: forming a second resin layer 13, the first surface and the second surface of the structure formed in the previous step are both pressed with resin to form the second resin layer 13;

[0173] like Fig.29 As shown, the inner circuit layer 12 of the structure formed in the previous step is pressed and filled with resin on the side away from the core board 1 to form a second resin layer 13. That is, resin is pressed on the first surface and the second surface of the structure formed in the previous step to form the second resin layer 13. The material of the second resin layer 13 and the first resin layer 6 can be the same or different.

[0174] S12: drilling, processing a through hole 13a on the second resin layer 13;

[0175] like Fig.30 As shown, a plurality of through holes 13a are formed in the second resin layer 13, which penetrate the thickness of the second resin layer 13. The plurality of through holes 13a can be respectively opposite to the plurality of orifice pads 5, so as to facilitate the connection between the inner circuit layer 12 and the circuit layer through the through holes 13a. Preferably, the through holes 13a can be formed in the second resin layer 13 by laser technology.

[0176] S13: forming a third seed layer 14, forming the third seed layer 14 on the surface of the structure formed in the previous step;

[0177] like Fig.31As shown, a third seed layer 14 is formed on the surface of the structure formed in step S12, specifically, the third seed layer 14 is formed on the surface of the second resin layer 13 of the structure formed in the previous step away from the core board 1, and the third seed layer 14 is required on both the upper and lower sides of the structure formed in the previous step, and the third seed layer 14 covers the surface of the second resin layer 13 away from the core board 1. Optionally, the third seed layer 14 can be formed by deposition, electroplating, etc.

[0178] S14: forming a fourth mask 15, forming a fourth mask 15 on the surface of the structure formed in the previous step;

[0179] like Fig.32 As shown, a fourth mask 15 is formed on the surface of the structure formed in step S13. Specifically, the fourth mask 15 is formed on both the first surface and the second surface of the structure formed in step S13. The first surface may be an upper surface, and the second surface may be a lower surface. The fourth mask 15 covers the first surface and the second surface of the structure formed in the previous step. The fourth mask 15 has a hollow structure, and the hollow structure of the fourth mask 15 is used to form a circuit layer 16.

[0180] In this step, the fourth mask 15 can be formed on the surface of the structure formed in the previous step by using a photolithography method to make an electroplating mask. Specifically, a dry film is first pressed on the first surface and the second surface of the structure formed in the previous step, and then exposure and development are performed in sequence to finally form the fourth mask 15. The material of the dry film is a photosensitive polymer material. Of course, other methods can also be used to form the fourth mask 15, which is not limited here.

[0181] S15: forming a circuit layer 16, forming the circuit layer 16 in the hollow structure of the fourth mask 15;

[0182] like Fig.33 As shown, in this step, a circuit layer 16 is formed in the hollow structure of the fourth mask 15. Specifically, the circuit layer 16 can be formed in the hollow structure of the fourth mask 15 by electroplating, deposition, etc.

[0183] In this step, the material of the circuit layer 16 can be copper, tungsten or titanium.

[0184] S16: removing the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15;

[0185] like Figure 34-Figure 35 As shown, the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15 are removed, and the circuit layer 16 and the third seed layer 14 covered by the circuit layer 16 are retained.

[0186] In this step, the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15 can be removed in two steps, that is, the fourth mask 15 is first removed, and then the third seed layer 14 covered by the fourth mask 15 is removed. Specifically, the fourth mask 15 can be directly peeled off by stripping, and then the third seed layer 14 covered by the fourth mask 15 can be removed by wet etching or laser etching.

[0187] S17: Repeat the steps at least once to form the second resin layer 13 until the fourth mask 15 and the third seed layer 14 covered by the fourth mask 15 are removed, so as to form at least one circuit layer 16;

[0188] like Fig.36 As shown, steps S11 - S16 are repeated at least once, thereby manufacturing a multi-layer wiring layer 16 .

[0189] S18: forming a solder resist layer 17 on the first surface and the second surface of the structure formed in the previous step, and the solder resist layer 17 has connection holes corresponding to the circuit layer 16;

[0190] like Fig.37 As shown, in this step, a solder resist layer 17 is made on the first surface and the second surface of the structure formed in the previous step, that is, a solder resist layer 17 is made on the outermost circuit layer 16 on the upper and lower sides of the structure formed in the previous step, and the solder resist layer 17 has connecting holes corresponding to the circuit layer 16, and the connecting holes are used to connect with the solder balls.

[0191] S19: Ball planting: soldering balls on the first surface and / or second surface of the structure formed in the previous step.

[0192] Specifically, chip solder balls 18 and substrate solder balls 19 may be respectively disposed on the first surface and the second surface of the structure formed in the previous step. The chip solder balls 18 are used for bonding with the chip, and the substrate solder balls 19 are used for bonding with the printed circuit board.

[0193] like Fig.38 As shown, a chip solder ball 18 is arranged on the first surface of the structure formed in the previous step, and a substrate solder ball 19 is arranged on the second surface of the structure formed in the previous step, and the bottom of the solder ball corresponds to the connection hole. The chip solder ball 18 is used for bonding with the chip, and the side of the chip solder ball 18 facing away from the core board 1 has a flat surface to facilitate bonding with the chip. The substrate solder ball 19 is used for bonding with the printed circuit board, and the side of the substrate solder ball 19 facing away from the core board 1 is a spherical surface to facilitate bonding with the printed circuit board.

[0194] In the packaging substrate structure formed by the manufacturing method of the packaging substrate structure, the orifice pad 5 is vertically stacked with the inner circuit layer 12. After the resin plugging, the inner circuit layer 12 adopts the buried circuit process, firstly etching the first resin layer 6 to form the circuit groove 6a, and then processing to form the inner circuit layer 12, so that the spacing of the circuit groove 6a and the width of the circuit groove 6a can be controlled, and by reducing the spacing between the circuit grooves 6a and the width of the circuit groove 6a, a fine circuit with a smaller spacing can be obtained, specifically a micron-level circuit can be realized. This solves the problem in the prior art that the metal layer is etched, so that a fine circuit with a smaller spacing cannot be obtained.

[0195] In the manufacturing method of the above-mentioned packaging substrate structure, the hole pad 5 is vertically stacked with the inner circuit layer 12, and two metal layer depositions can form a four-layer circuit. Compared with the conventional vertical stacked hole substrate in the prior art, which requires two metallizations to manufacture two layers of metal circuits, the processing efficiency is improved, the process flow is shortened, the wiring density is increased, and the number of wiring layers is reduced.

[0196] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0197] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A packaging substrate structure, characterized in that: include: A core plate having a plurality of through holes, the core plate comprising a first surface and a second surface opposite to each other along a thickness direction thereof; a first seed layer, the first seed layer covering the inner wall of the through hole, the area around the opening of the through hole, and the local areas of the first surface and the second surface; A core board circuit layer, an orifice pad and a metal conductive layer, wherein the orifice pad covers the first seed layer in the area around the orifice of the through hole, the metal conductive layer covers the first seed layer on the inner wall of the through hole, and the core board circuit layer covers the first seed layer at the remaining position; A first resin layer, wherein the first resin layer fills the gap between the through hole of the core board and the circuit layer of the core board, a plurality of circuit grooves are provided on a side of the first resin layer away from the core board, and the circuit grooves opposite to the orifice pads are through grooves, and the remaining circuit grooves are blind grooves; A second seed layer and an inner circuit layer are stacked, wherein the second seed layer covers the inner wall of the circuit groove of the first resin layer, the inner circuit layer covers the surface of the second seed layer on one side away from the core board, and the inner circuit layer is embedded in the circuit groove; At least one multi-layer composite structure is arranged on a side of the inner circuit layer away from the core board, the multi-layer composite structure comprises a second resin layer, a third seed layer and a circuit layer arranged in sequence in a direction away from the core board, the second resin layer has a through hole, and the third seed layer and the circuit layer are stacked and arranged on a side of the second resin layer away from the core board; A solder resist layer, the solder resist layer being arranged on a side of the multi-layer composite structure away from the core board; A solder ball is disposed on the solder resist layer, and a bottom of the solder ball passes through the solder resist layer and contacts the outermost circuit layer.

2. The packaging substrate structure according to claim 1, characterized in that: The first resin layer and / or the second resin layer include ABF resin and / or RCC.

3. The packaging substrate structure according to claim 1, characterized in that: The first seed layer, the second seed layer and / or the third seed layer include at least one sub-metal layer; or, The first seed layer, the second seed layer and / or the third seed layer include multiple sub-metal layers, and the multiple sub-metal layers are made of different materials.

4. The packaging substrate structure according to claim 3, characterized in that: The material of the sub-metal layer is titanium, copper or tungsten.

5. The packaging substrate structure according to claim 1, characterized in that: The solder balls include chip solder balls and substrate solder balls. The chip solder balls are arranged on the solder resist layer on one side of the core board, and the substrate solder balls are arranged on the solder resist layer on the other side of the core board. The chip solder balls are used for bonding with the chip, and the substrate solder balls are used for bonding with the printed circuit board.

6. A method for manufacturing a packaging substrate structure, characterized in that: include: The core plate has a plurality of through holes, wherein the core plate has a first surface and a second surface opposite to each other; forming a first seed layer on the surface of the core plate with the through hole; forming a first mask on the surface of the structure formed in the previous step, wherein the first mask has a hollow structure, and the hollow structure of the first mask is at least opposite to the through hole of the structure formed in the previous step and the area around the opening of the through hole; A core circuit layer, an orifice pad and a metal conductive layer are formed, a first metal layer is formed in the hollow structure of the first mask, and the first metal layer covers the inner wall of the through hole and the area around the orifice of the through hole, the first metal layer in the area around the orifice of the through hole forms the orifice pad, the first metal layer covering the inner wall of the through hole forms the metal conductive layer, and the first metal layer at the remaining position except the inner wall of the through hole and the area around the orifice of the through hole forms the core circuit layer; removing the first mask and the first seed layer covered by the first mask; Plug the holes and press the resin, press the resin on the first surface and the second surface of the core board, so that the resin fills the gap between the through hole of the core board and the circuit layer of the core board, and forms a first resin layer on the first surface and the second surface of the structure formed in the previous step; forming a plurality of circuit grooves, wherein a plurality of circuit grooves are formed on the first resin layer, and the circuit grooves opposite to the through holes extend from the first resin layer to the orifice pad; forming a second seed layer on the surface of the structure formed in the previous step; forming a second metal layer, and forming the second metal layer on the surface of the second seed layer; forming an inner circuit layer, removing the portion of the second metal layer not embedded in the circuit groove, and retaining the portion of the second metal layer embedded in the circuit groove to form an inner circuit layer; Forming a second resin layer, pressing resin on both the first surface and the second surface of the structure formed in the previous step to form the second resin layer; Drilling, processing through holes on the second resin layer; forming a third seed layer on the surface of the structure formed in the previous step; forming a fourth mask on the surface of the structure formed in the previous step; forming a circuit layer, wherein the circuit layer is formed in the hollow structure of the fourth mask; removing the fourth mask and the third seed layer covered by the fourth mask; Repeating the step of forming a second resin layer at least once until the fourth mask and the third seed layer covered by the fourth mask are removed, so as to form at least one circuit layer; Making a solder resist layer on the first surface and the second surface of the structure formed in the previous step, wherein the solder resist layer has connection holes corresponding to the circuit layer; Ball planting: solder balls on the first surface and / or second surface of the structure formed in the previous step.

7. The method for manufacturing a packaging substrate structure according to claim 6, characterized in that: The plugging and pressing resin comprises: Plug the holes, and press the resin on the first surface and the second surface of the core board so that the resin fills the gap between the through hole of the core board and the circuit layer of the core board; Thinning the pressed resin layer so that the resin does not cover the core board circuit layer and the orifice pad, and the thinned resin layer is flush with the orifice pad and the core board circuit layer or the core board circuit layer and the orifice pad are higher than the resin layer; The resin is pressed again to form a first resin layer.

8. The method for manufacturing a packaging substrate structure according to claim 7, characterized in that: The thinning and laminating resin layer comprises: thinning the laminating resin by chemical mechanical polishing so that the resin does not cover the core board circuit layer and the hole pad; and / or, the resin used in the plugging and laminating resin step comprises ABF resin and / or RCC.

9. The method for manufacturing a package substrate structure according to claim 6, characterized in that: The step of forming the line groove comprises: forming a metal protective layer, wherein the metal protective layer is formed on both the first surface and the second surface of the structure formed in the previous step; forming a second mask on the surface of the structure formed in the previous step, wherein the second mask has a hollow structure; removing the metal protection layer not covered by the second mask; Etching the first surface and the second surface of the structure formed in the previous step to form a circuit groove, so that the depth of the circuit groove extends from the metal protection layer to the first resin layer, and removing the second mask; Forming a third mask, forming a third mask on the surface of the structure formed in the previous step, wherein the hollow structure of the third mask is opposite to the opening of the through hole and the surrounding area; Etching the first surface and the second surface of the structure formed in the previous step, deepening the line groove opposite to the opening of the through hole and the surrounding area, the line groove opposite to the through hole extends from the metal protection layer to the opening pad, and removing the third mask; Remove the metal protective layer.

10. The method for manufacturing a package substrate structure according to claim 6, characterized in that: In the step of forming the inner circuit layer, the portion of the second metal layer not embedded in the circuit groove is removed, specifically, by using chemical mechanical polishing to remove the portion of the second metal layer not embedded in the circuit groove.

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