Thin film transistor with low contact resistance and preparation method thereof

Abstract

The invention discloses a low contact resistance thin film transistor and a preparation method thereof, and the thin film transistor comprises a substrate; a gate electrode on the substrate; the gate dielectric layer is positioned on the gate electrode; the channel layer and the source and drain electrodes are located on the gate dielectric layer; the source electrode and the drain electrode are separated by the channel layer, and the channel particle layers are located between the source electrode and the drain electrode and the channel layer respectively. The metal oxide layer is formed on the contact interface of the channel layer and the source and drain electrodes of the thin film transistor, so that the contact resistance of the thin film transistor is greatly reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of display driving, and in particular relates to a low contact resistance thin film transistor and a preparation method thereof. Background Art

[0002] Amorphous oxide thin film transistors (AOS TFTs) have the advantages of low preparation cost, good large-area uniformity, high mobility, low off-state current, and visible light transparency, which makes them widely used in the display field.

[0003] At present, among AOS TFTs, IGZO TFTs are widely used in the commercial field with excellent performances such as high mobility, low off-state current, and uniformity of large-area preparation. Companies such as Sharp, Samsung, Panda, Apple, and LG Electronics have developed IGZO TFTLCDs. However, as high-end displays have higher and higher requirements for resolution and refresh rate, TFTs with higher mobility are needed to drive them, and IGZO can no longer meet such requirements. At present, among AOS TFTs, ITZO is the most promising alternative to IGZO and will become the next generation of thin film transistor materials.

[0004] The electrical performance of AOS TFT is significantly affected by defects. At present, many studies have optimized the process, used plasma treatment and other methods to control the defect density in the channel to improve the performance of the device. However, an important performance indicator has been overlooked in many reports, that is, the contact resistance between SD / AOS. In particular, as the device shrinks, the contact resistance has an increasingly greater impact on the device. Therefore, in order to improve the performance of small devices, the interface contact resistance must be controlled. The source-drain (SD) electrode serves as the entry / exit of carrier transmission in the device. The existence of the contact interface and related potential barriers between them makes this a performance adjustment knob. Studies have shown that the presence of the potential barrier makes the lateral electric field in the device unevenly distributed, thereby affecting the mobility and output characteristics of the device, and the degree of influence is closely related to the interface contact barrier. This further shows that the study of interface contact is an indispensable part of the research on new channel materials.

[0005] Currently, the commonly used SD electrode materials are metal and transparent conductive oxide (TCO). Metal electrodes have low contact resistance, high stability and high compatibility, but they are opaque and not suitable for transparent or flexible electronic devices. TCO electrodes have high transparency, low cost and easy preparation, but they have high contact resistance and are easily affected by environmental factors.

[0006] Currently commonly used methods to reduce contact resistance and improve mobility include but are not limited to: inserting a buffer layer between the SD electrode and the channel layer, such as aluminum oxide, silicon oxide, tin oxide, etc., to reduce the contact barrier and improve the contact quality.

[0007] By using the co-sputtering method, a certain proportion of IGZO is doped into the SD electrode to increase the concentration of oxygen vacancies and improve the interface matching between the SD electrode and the channel layer. By using the post-annealing method, the device is subjected to high-temperature treatment after the SD electrode is prepared to promote atomic diffusion and the generation of oxygen vacancies between the SD electrode and the channel layer. By using the laser annealing method, the device is locally heated after the SD electrode is prepared to achieve crystallization of the SD electrode and activation of the channel layer. The above methods can effectively reduce the SD electrode contact resistance of the IGZO TFT, thereby improving the electrical performance and reliability of the device. However, these methods also have some limitations, such as the thickness and material selection of the buffer layer, the proportion and parameters of co-sputtering, the temperature and time of annealing, etc., which will affect the performance and stability of the device. Summary of the invention

[0008] The present invention provides a low contact resistance thin film transistor. A layer of nanocrystal is formed at the contact interface between the channel layer and the source-drain electrode of the thin film transistor by using metal induced structure formation technology, so that the contact resistance of the thin film transistor is greatly reduced.

[0009] The present invention provides a low contact resistance thin film transistor, comprising: substrate; A gate electrode, located on the substrate; A gate dielectric layer, located on the gate electrode; A channel layer and a source-drain electrode, wherein the channel layer and the source-drain electrode are located on the gate dielectric layer, and the source-drain electrode is located on the channel layer and separated by the channel layer; The channel particle layer is located between the source and drain electrodes and the channel layer.

[0010] The channel particle layer provided by the present invention increases the order at the interface, reduces the contact resistance of the thin film transistor, and improves the mobility of the thin film transistor.

[0011] Preferably, the channel particle layer comprises ordered nanoparticles. The ordered nanoparticles effectively reduce the contact resistance.

[0012] Preferably, the material of the channel particle layer is the same as that of the channel layer. The present invention does not insert a new layer between the channel layer and the source-drain electrode, but forms the channel particle layer on the existing channel layer, which can improve the mobility and avoid the generation of a large number of defects.

[0013] Preferably, the material of the channel layer is one or more of indium gallium zinc oxide, gallium oxide, zinc oxide, indium oxide, and tin oxide.

[0014] Preferably, the thickness of the channel layer is 20-50 nm.

[0015] Preferably, the material of the portion of the source-drain electrode in contact with the channel particle layer is Al or Ta.

[0016] Further preferably, the source and drain electrodes are Al, Ta, Al and Ta stacked on each other, or material A, the material A is that the part in contact with the channel particle layer is Al or Ta, and the part away from the channel particle layer is material a, and the material a is Al, Ta, Mo, ITO, Pt, Au, W, Ag or Cr.

[0017] The Al or Ta used in the present invention has very low electronegativity. When used as source and drain electrodes, combined with an annealing process, an ordered channel particle layer can be induced to form between the channel layer and the electrode, thereby effectively reducing the contact resistance.

[0018] Preferably, the material of the substrate is silicon wafer, glass, plastic, nitride, sapphire, quartz or carbide, the nitride is gallium nitride or aluminum nitride, the carbide is silicon carbide, and the thickness of the substrate is 100 μm-100 mm.

[0019] Preferably, the material of the gate electrode is Au, W, ITO, Pt, Ag, Cr, Ta, Mo or Ti, and the thickness of the gate electrode is 10 nm-200 nm.

[0020] Preferably, the gate dielectric layer is made of SiO2, Al2O3, HfO x , Co2O3, MgO or CaO, and the thickness of the gate dielectric layer is 5 nm-200 nm.

[0021] On the other hand, the present invention also provides a method for preparing the low contact resistance thin film transistor, comprising: A gate electrode layer and a gate dielectric layer are sequentially formed on a substrate by using a vacuum coating technique.

[0022] A channel layer is formed on the gate dielectric layer.

[0023] The channel layer is patterned by a first mask photolithography process, and then subjected to a first annealing treatment. The present invention forms a desired channel shape by patterning, and eliminates defects in forming the channel shape by the first annealing.

[0024] An electrode photoresist array is formed on the surface of the patterned channel layer by a second mask photolithography process, and after the electrode is deposited by magnetron sputtering, the photoresist is cleaned and then a second annealing process is performed. The present invention eliminates some electrode / channel interface defects through the second annealing process and induces the formation of a channel particle layer with an ordered structure.

[0025] Preferably, the temperature of the first annealing treatment is 300-400° C. and the time is 1-2 hours.

[0026] Preferably, the temperature of the second annealing treatment is 100-250°C and the time is 1-2 hours. By controlling the temperature and time of the second annealing, defects can be effectively eliminated, and an ordered, nanocrystalline channel particle layer can be induced to form, and the growth of grains and even film damage can be avoided.

[0027] Preferably, the first mask lithography process adopts hydroiodic acid etching, the mass fraction of the hydroiodic acid is 55.0-58.0%, and the etching time is 5-10s.

[0028] Compared with the prior art, the present invention has the following beneficial effects: The present invention forms a channel particle layer at the contact interface between the channel layer and the source-drain electrode through the source-drain metal induced effect. The ordered channel particle layer can reduce the contact resistance of the contact interface, avoid the large barrier height generated by the contact between the traditional source-drain electrode and the channel layer, and improve the mobility of the thin film transistor.

[0029] The method for preparing a thin film transistor provided by the present invention performs annealing after the electrode is deposited, thereby promoting the formation and ordering of a channel particle layer between a channel layer of the thin film transistor and an electrode, while eliminating a large number of interface defects that have been formed. Compared with the prior art, no additional induction layer needs to be introduced, and a thin film transistor with lower contact resistance can be prepared. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of a thin film transistor provided in a specific embodiment of the present invention; Figure 2 The transfer curve diagram of the thin film transistors prepared in Comparative Examples 1 and 2 and Examples 1-5 of the present invention; Figure 3 The contact resistance curves of the thin film transistors prepared in Comparative Examples 1 and 2 and Examples 1-5 of the present invention are shown; Figure 4 TEM morphology images of thin film transistors prepared in Comparative Examples 1 and 2 and Example 2 of the present invention; Among them, there are a substrate 1, a gate electrode 2, a gate dielectric layer 3, a channel layer 4, a channel particle layer 5, a source electrode 6, and a drain electrode 7. DETAILED DESCRIPTION

[0031] In order to further describe the technical solution of the present invention in detail, the following will be explained in conjunction with the accompanying drawings and specific implementation cases.

[0032] A specific embodiment of the present invention provides a low contact resistance thin film transistor, such as Figure 1As shown, it includes a substrate 1, a gate electrode 2, a gate dielectric layer 3, a channel layer 4, a channel particle layer 5, a source electrode 6 and a drain electrode 7.

[0033] The gate electrode 2 provided in the specific embodiment of the present invention is located on the substrate 1, the gate dielectric layer 3 is located on the gate electrode 2, and the contact interface between the channel layer 4 and the source electrode 6 and the drain electrode 7 forms a channel particle layer 5. The channel layer 4, the source electrode 6 and the drain electrode 7 are all located on the gate dielectric layer 3.

[0034] Embodiment 1: The present invention provides a method for preparing a low contact resistance thin film transistor, comprising: (1) A p+-Si / SiO2 thermally oxidized silicon wafer is obtained as substrate 1, and a clean silicon wafer is used as a companion wafer. It is cleaned in an ultrasonic machine using acetone, alcohol, and deionized water for 5 min, 5 min, and 8 min respectively, and dried using N2. The purpose of this process is to provide a pollution-free growth substrate for the subsequent channel layer. In addition, since the p+-Si / SiO2 thermally oxidized silicon wafer has an oxide layer of about 100 nm on the surface, it can be used as substrate 1, gate electrode 2, and gate dielectric layer 3 at the same time, which simplifies the process.

[0035] (2) A 2cm*2cm p+-Si / SiO2 thermally oxidized silicon wafer was taken, and IGZO (In:Ga:Zn=1:1:1, i.e., the atomic number ratio of In, Ga, and Zn was 1:1:1) was used as the target material. In an argon-oxygen gas flow ratio of 30:3sccm, the sputtering power was 80W, and an amorphous indium gallium zinc oxide film was grown on the thermally oxidized silicon wafer using a DC magnetron sputtering technique to obtain a channel layer 4. The sputtering time was about 13 minutes, and the film thickness was about 30nm.

[0036] (3) Through the first mask photolithography process, a channel photoresist array is formed on the channel surface. Pre-bake at 95°C for 3 minutes, exposure time for 9 seconds, and development time for 40 seconds. The etching solution uses HI acid with a mass fraction of 55.0-58.0%, and the etching time is 5-10 seconds. Then the first annealing is performed at 350°C for 1 hour to obtain a patterned channel layer.

[0037] (4) Through the second mask photolithography process, an electrode photoresist array is formed on the patterned channel surface. The baking process is: baking at 105°C for 1min45s, exposure for 3s; the second baking: baking at 112°C for 3min30s, exposure for 40s and development for 40s, to obtain a sample with an electrode photoresist array.

[0038] (5) The sample obtained in step (4) is deposited by magnetron sputtering to obtain an Al electrode layer, the photoresist on the sample is cleaned off with an ethanol solution, and then a second annealing is performed. The second annealing process is to anneal at 100° C. for 1 hour to obtain a thin film transistor.

[0039] Example 2: Compared with Example 1, the difference is that the temperature of the second annealing is 150°C, and the remaining steps are the same as Example 1.

[0040] Example 3: Compared with Example 1, the difference is that the temperature of the second annealing is 250°C, and the remaining steps are the same as Example 1.

[0041] Embodiment 4: Compared with Embodiment 1, the difference is that the source and drain electrode materials are replaced with Ta, the temperature of the second annealing is 200° C., and the remaining steps are the same as Embodiment 1.

[0042] Example 5: Compared with Example 1, the difference is that the source and drain electrode materials are Al / Ta stacked layers, Al is 40nm, Ta is 40nm, the second annealing temperature is 150°C, and the remaining steps are the same as Example 1.

[0043] Comparative Example 1: Compared with Example 1, the difference is that the source and drain electrode materials are replaced with Mo, the temperature of the second annealing is 150° C., and the remaining steps are the same as Example 1.

[0044] Comparative Example 2: Compared with Example 1, the difference is that the source and drain electrode materials are replaced with ITO, the temperature of the second annealing is 150° C., and the remaining steps are the same as Example 1.

[0045] Performance analysis: A semiconductor parameter analyzer was used to characterize and analyze the electrical performance of the thin film transistors of the embodiments / comparative examples, and to calculate their contact resistance.

[0046] The morphology of the thin film transistors of the embodiments / comparative examples was characterized and analyzed using a transmission electron microscope.

[0047] like Figure 2 The source-drain voltage V DS =10.1V transfer characteristic curve, from Figure 2 It can be seen that the on-state currents of Examples 1-5 are relatively high, the on-state current of Example 2 is the highest, the threshold voltage is near 0 V, and the electrical performance is optimal.

[0048] Figure 3 The contact resistance of Comparative Examples 1, 2 and Examples 1-5 varies with gate voltage. The contact resistance of the thin film transistors prepared in Examples 1-5 of the present invention is relatively low, while the contact resistance of Comparative Examples 1 and 2 is relatively high. Among them, the contact resistance of Example 2, Example 4 and Example 5 tends to drop sharply under high gate voltage.

[0049] Figure 4 The cross-sectional morphology of comparative examples 1 and 2 and embodiment 2 under a transmission electron microscope is shown. It is clearly observed that in embodiment 2, a particle layer exists at the interface between the electrode and the channel, and some particles are crystallized. After calculating the crystal plane intercept, the composition is InGaZnO4; while in comparative examples 1 and 2, the contact interface between the channel and the electrode is flat and has no crystallization, and no particle layer is formed. This indicates that the formation and crystallization of the particle layer increase the order at the interface, reduce the contact resistance of the thin film transistor, and improve the mobility of the thin film transistor.

[0050] The above embodiments are combined with the accompanying drawings to express and explain the present invention. It should be pointed out that the above description only represents the specific implementation mode of the present invention, and is therefore only illustrative and should not be limiting. A person skilled in the art, inspired by this invention, shall make modifications, improvements and similar substitutions based on this invention within the scope of protection of the present invention.

Claims

1. A low contact resistance thin film transistor, characterized in that: include: substrate; A gate electrode, located on the substrate; A gate dielectric layer, located on the gate electrode; A channel layer and a source-drain electrode, wherein the channel layer and the source-drain electrode are located on the gate dielectric layer, and the source-drain electrode is located on the channel layer and separated by the channel layer; The channel particle layer is located between the source and drain electrodes and the channel layer.

2. The low contact resistance thin film transistor according to claim 1, characterized in that: The channel particle layer includes ordered nanoparticles.

3. The low contact resistance thin film transistor according to claim 1, characterized in that: The material of the channel particle layer is the same as that of the channel layer. The material of the channel layer is one or more of indium gallium zinc oxide, gallium oxide, zinc oxide, indium oxide, and tin oxide.

4. The low contact resistance thin film transistor according to claim 1, characterized in that: The material of the source-drain electrode in contact with the channel particle layer is Al or Ta.

5. The low contact resistance thin film transistor according to claim 1 or 4, characterized in that: The source and drain electrodes are Al, Ta, Al and Ta stacked on each other, or material A, wherein the material A is Al or Ta in contact with the channel particle layer, and the part away from the channel particle layer is material a, and the material a is Al, Ta, Mo, ITO, Pt, Au, W, Ag, or Cr.

6. The low contact resistance thin film transistor according to claim 1, characterized in that: The material of the substrate is silicon wafer, glass, plastic, nitride, sapphire, quartz or carbide, the nitride is gallium nitride or aluminum nitride, the carbide is silicon carbide, and the thickness of the substrate is 100 μm-100 mm.

7. The low contact resistance thin film transistor according to claim 1, characterized in that: The material of the gate electrode is Au, W, ITO, Pt, Ag, Cr, Ta, Mo or Ti, and the thickness of the gate electrode is 10 nm-200 nm.

8. The low contact resistance thin film transistor according to claim 1, characterized in that: The gate dielectric layer is made of SiO2, Al2O3, HfO x , Co2O3, MgO or CaO, and the thickness of the gate dielectric layer is 5 nm-200 nm.

9. A method for preparing a low contact resistance thin film transistor according to any one of claims 1 to 8, characterized in that: include: A gate electrode layer and a gate dielectric layer are sequentially formed on the substrate by using a vacuum coating technology; forming a channel layer on the gate dielectric layer; Performing patterning on the channel layer through a first mask photolithography process, and then performing a first annealing process; An electrode photoresist array is formed on the surface of the patterned channel layer through a second mask photolithography process. After the electrode is deposited by magnetron sputtering, the photoresist is cleaned and then a second annealing process is performed.

10. The method for preparing a low contact resistance thin film transistor according to claim 9, characterized in that: The temperature of the second annealing treatment is 100-250° C. and the time is 1-2 hours.

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