Avalanche photodetector chip and preparation method thereof

Abstract

The invention provides an avalanche photodetector chip, which can be applied to the technical field of optoelectronic devices, and comprises a substrate; the epitaxial layer is located on the substrate, the epitaxial layer comprises an N-type contact layer, a multiplication layer, a charge layer, a first transition layer, an absorption layer, a second transition layer, a cap layer and a P-type contact layer which are sequentially arranged, the epitaxial layer comprises an inclined mesa structure, and the top surface of the inclined mesa structure is the surface, away from the substrate, of the P-type contact layer; and the bottom surface of the inclined mesa structure is an N-type contact layer. Through the design of the inclined mesa structure, the opposite area between the layers of the upper mesa and the lower mesa can be reduced, the parasitic capacitance of the chip is reduced, the high-speed characteristic of the chip is improved, no extra process is added, and the preparation is simpler. The invention also provides a preparation method of the avalanche photodetector chip.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic devices, and in particular to an avalanche photodetector chip and a preparation method thereof. Background Art

[0002] In today's digital age, the rapid development of information technology has driven the continuous pursuit of improved data transmission speed and coverage. Instant transmission and processing of data has become a key requirement for business, scientific research, education, and daily life. As a high-speed, large-capacity communication method, optical communication has become the backbone of modern communication networks. With the rise of emerging applications such as 5G networks, the Internet of Things (IoT), telemedicine, and online education, the demand for optical communication technology will become more urgent.

[0003] Photodetectors play a vital role in optical communication systems, converting optical signals into electrical signals. Their performance directly affects the performance of optical communication systems. Compared with PIN-structured photodetectors, avalanche photodiodes (APDs) can improve the sensitivity of the system without sacrificing speed, and can achieve the characteristics of high sensitivity and high response speed at the same time. They are widely used in long-distance, high-speed optical communication systems. They can detect very weak optical signals, thereby improving the performance and reliability of communication systems. With the growing demand for optical communication technology, the performance requirements for avalanche photodetectors are also increasing. However, current high-speed avalanche detectors have problems such as low light responsivity caused by excessive dark current, and the introduction of excess noise during multiplication, which limits the data transmission rate. Therefore, it is very important to reduce the dark current of avalanche detectors and increase the response rate. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In order to solve at least one of the above technical problems of avalanche photodetectors in the prior art, the embodiments of the present invention provide an avalanche photodetector chip and a method for preparing the same, which increases the accuracy of Zn diffusion and improves chip reliability by optimizing the epitaxial structure of the chip. At the same time, by changing the process route and controlling the diffusion area and the setting angle of the table, the dark current and noise of the chip are reduced, and the high-speed characteristics of the chip are enhanced.

[0006] (II) Technical solution

[0007] In view of the above technical problems, an embodiment of the present invention provides an avalanche photodetector chip and a method for preparing the same.

[0008] According to a first aspect of the present invention, an avalanche photodetector chip is provided, comprising: a substrate; and an epitaxial layer, located on the surface of the substrate, wherein the epitaxial layer comprises: an N-type contact layer, located on the surface of the substrate; a multiplication layer, located on the side of the N-type contact layer away from the substrate; a charge layer, located on the side of the multiplication layer away from the substrate; a first transition layer, located on the side of the charge layer away from the substrate; an absorption layer, located on the side of the first transition layer away from the substrate; a second transition layer, located on the side of the absorption layer away from the substrate; a cap layer, located on the side of the second transition layer away from the substrate; and a P-type contact layer, located on the side of the cap layer away from the substrate, wherein the epitaxial layer comprises an inclined mesa structure, the top surface of the inclined mesa structure is the surface of the P-type contact layer away from the substrate; and the bottom surface of the inclined mesa structure is the N-type contact layer.

[0009] In some exemplary embodiments, the material of the multiplication layer includes one of aluminum arsenic antimony, aluminum gallium arsenic antimony, or aluminum indium arsenic antimony.

[0010] In some exemplary embodiments, the material of the P-type contact layer includes InGaAs.

[0011] In some exemplary embodiments, the material of the second transition layer includes weakly P-type doped indium aluminum gallium arsenide with a doping concentration of 1×10 15 cm -3 -1×10 16 cm -3 .

[0012] In some exemplary embodiments, the second transition layer, the cap layer, and the intermediate region of the P-type contact layer include a cylindrical zinc-doped region.

[0013] In some exemplary embodiments, the mesa inclination angle of the inclined mesa structure is less than 45°, and the surface dark current and parasitic capacitance are adjusted by adjusting the size of the mesa inclination angle.

[0014] In some exemplary embodiments, it also includes: an N-electrode located on a side of the N-type contact layer away from the substrate; a P-electrode located on a side of the P-type contact layer away from the substrate; a passivation layer located on the outer surface of the epitaxial layer and a portion of the side of the substrate, and the passivation layer is disconnected at the N-electrode and the P-electrode.

[0015] In some exemplary embodiments, at least one of the following features is included: the thickness of the N-type contact layer is 0.2μm-1μm; the thickness of the multiplication layer is 50nm-200nm; the thickness of the charge layer is 30nm-200nm; the thickness of the first transition layer is 20nm-100nm; the thickness of the absorption layer is 0.3μm-1μm; the thickness of the second transition layer is 20nm-100nm; the thickness of the cap layer is 0.2μm-1μm; the thickness of the P-type contact layer is 0.1μm-1μm.

[0016] According to a second aspect of the present invention, a method for preparing an avalanche photodetector chip is provided, comprising: growing an epitaxial layer: epitaxially growing an N-type contact layer, a multiplication layer, a charge layer, a first transition layer, an absorption layer, a second transition layer, a cap layer, and a P-type contact layer on a substrate in sequence to obtain a sample containing an epitaxial layer; opening a diffusion hole: growing silicon dioxide as a diffusion barrier layer, etching the diffusion barrier layer by photolithography and etching processes to form a diffusion hole region; preparing a zinc-doped region: spin-coating a zinc diffusion source on the outer surface of the diffusion hole, and forming a zinc-doped region in the diffusion hole region by a rapid thermal annealing process; and etching a tilted terrace: growing silicon dioxide as a diffusion barrier layer, etching the diffusion barrier layer by photolithography and etching processes to form a diffusion hole region. The method comprises the following steps: using a mask as a mask, etching the mask through photolithography and etching processes, and forming an inclined terrace structure in the epitaxial layer area; isolating the terrace etching: growing silicon dioxide as a mask, and etching to the substrate through photolithography and etching processes to isolate the chip; growing a passivation layer: growing a passivation layer on the outer surface of the epitaxial layer and a part of the side of the substrate; preparing electrode windows: preparing an N-electrode window and a P-electrode window on the passivation layer through photolithography and etching processes; and preparing electrodes: using photolithography, electron beam evaporation, and annealing processes to prepare an N-electrode on the side of the N-type contact layer away from the substrate and a P-electrode on the side of the P-type contact layer away from the substrate.

[0017] In some exemplary embodiments, the temperature of the rapid thermal annealing process is 500° C.-600° C.; and / or the mesa inclination angle of the inclined mesa structure is less than 45°.

[0018] (III) Beneficial effects

[0019] It can be seen from the above technical solutions that an avalanche photodetector chip and a method for preparing the same provided by the embodiments of the present invention have at least the following beneficial effects:

[0020] (1) The inclined mesa structure proposed in the embodiment of the present invention can not only reduce the facing area between the upper and lower mesa layers, reduce the parasitic capacitance of the chip, and improve the high-speed characteristics of the chip, but also does not add additional processes, making the preparation simpler.

[0021] (2) A common way to reduce parasitic capacitance is to add a step to the absorption layer to form a three-table structure. However, this method adds a step of table etching process, which not only increases the cost of chip preparation, but also easily introduces new problems during the preparation process. The present invention adopts the method of regional diffusion, which can effectively reduce the surface electric field, thereby reducing the surface dark current of the chip. The preparation process is simple and the preparation cost is low.

[0022] (3) The multiplication layer uses low-k value materials, such as aluminum arsenic antimony (AlAsSb), aluminum gallium arsenic antimony (AlGaAsSb) or aluminum indium arsenic antimony (AlInAsSb), so that the prepared avalanche detector chip can obtain lower noise and improve the sensitivity and response characteristics of the avalanche diode.

[0023] (4) The P-type contact layer uses a material with a high zinc (Zn) diffusion coefficient, such as indium gallium arsenide (InGaAs), which can increase the surface doping concentration, obtain a better ohmic contact effect, reduce the resistance of the chip, and increase the response rate.

[0024] (5) The second transition layer is made of a material with a low Zn diffusion coefficient, such as indium aluminum gallium arsenide (InAlGaAs), and the second transition layer is weakly P-doped when growing the epitaxial structure, with a doping concentration of 10 15 cm -3 -10 16 cm -3 , which can prevent Zn from continuing to diffuse downward to a certain extent, increase the accuracy of Zn diffusion, and effectively improve the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic diagram of the structure of an avalanche photodetector chip according to an embodiment of the present invention is shown;

[0027] Figure 2 A schematic diagram schematically shows a process flow of a method for preparing an avalanche photodetector chip according to an embodiment of the present invention; and

[0028] Figure 3 The structure diagram of an avalanche photodetector chip manufacturing process according to an embodiment of the present invention is schematically shown, wherein: Figure 3 (a) schematically shows a schematic structural diagram of an avalanche photodetector chip after growing an epitaxial layer in a preparation process according to an embodiment of the present invention; Figure 3 (b) schematically shows a schematic structural diagram of the avalanche photodetector chip after the zinc diffusion region is prepared in the preparation process according to an embodiment of the present invention; Figure 3 (c) schematically shows a schematic diagram of the structure after the inclined terrace is etched during the preparation process of the avalanche photodetector chip according to an embodiment of the present invention; Figure 3 (d) schematically shows a schematic structural diagram of an avalanche photodetector chip after etching the isolation mesa in the preparation process according to an embodiment of the present invention; Figure 3 (e) schematically shows a schematic structural diagram of an avalanche photodetector chip after a passivation layer is grown in the preparation process according to an embodiment of the present invention; and Figure 3 (f) schematically shows a structural diagram of the avalanche photodetector chip after the electrodes are prepared in the preparation process according to an embodiment of the present invention.

[0029] Reference numerals:

[0030] 1-substrate; 2-N-type contact layer; 3-multiplication layer; 4-charge layer; 5-first transition layer; 6-absorption layer; 7-second transition layer; 8-cap layer; 9-P-type contact layer; 10-zinc-doped region; 11-passivation layer; 12-N electrode; 13-P electrode. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Figure 1 The schematic diagram shows the structure of an avalanche photodetector chip according to an embodiment of the present invention.

[0033] like Figure 1 As shown, an avalanche photodetector chip according to an embodiment of the present invention comprises: a substrate 1; and an epitaxial layer located on the substrate 1, wherein the epitaxial layer comprises: an N-type contact layer 2 located on the substrate 1; a multiplication layer 3 located on the side of the N-type contact layer 2 away from the substrate 1; a charge layer 4 located on the side of the multiplication layer 3 away from the substrate 1; a first transition layer 5 located on the side of the charge layer 4 away from the substrate 1; an absorption layer 6 located on the side of the first transition layer 5 away from the substrate 1; a second transition layer 7 located on the side of the absorption layer 6 away from the substrate 1; a cap layer 8 located on the side of the second transition layer 7 away from the substrate 1; and a P-type contact layer 9 located on the side of the cap layer 8 away from the substrate 1, wherein the epitaxial layer comprises an inclined mesa structure, the top surface of the inclined mesa structure is the surface of the P-type contact layer 9 away from the substrate 1, and the diameter is L; and the bottom surface of the inclined mesa structure is the N-type contact layer 2. The inclined mesa structure can not only reduce the facing area between the upper and lower mesa layers, reduce the parasitic capacitance of the chip, and improve the high-speed characteristics of the chip, but also does not add additional processes, and the preparation is simpler.

[0034] In some exemplary embodiments, the middle area of ​​the second transition layer 7, the cap layer 8, and the P-type contact layer 9 includes a cylindrical zinc-doped region 10, the diameter of the zinc-doped region 10 is W, and the inclination angle of the inclined mesa structure is θ. For two chips with the same W and the bottom of the mesa structure, when the angle θ is large, the difference LW between the upper mesa and the diffusion hole is large, and the surface dark current is small. When the angle θ is small, the upper mesa L is small, which reduces the facing area of ​​the upper and lower mesas, thereby reducing the parasitic capacitance and improving the response characteristics. Different θ angles can be selected according to actual applications during the preparation process. Optionally, W is less than 20μm, L does not exceed 30μm, and θ is less than 45°. The surface dark current and parasitic capacitance are adjusted by adjusting the size of the mesa inclination angle.

[0035] In some exemplary embodiments, the avalanche photodetector chip further includes: an N electrode 12, located on a side of the N-type contact layer 2 away from the substrate 1; a P electrode 12, located on a side of the P-type contact layer 9 away from the substrate 1 and located on the zinc-doped region 10; a passivation layer 11, located on the outer surface of the epitaxial layer and a portion of the side of the substrate 1, and the passivation layer 11 is disconnected at the N electrode 12 and the P electrode 12. Optionally, the material of the passivation layer 11 includes aluminum oxide.

[0036] In some exemplary embodiments, the material of the substrate 1 includes indium phosphide (InP) or gallium antimonide (GaSb), the material of the multiplication layer 3 matches the lattice of the material of the substrate 1, and the material of the multiplication layer 3 is selected from low-k value materials, such as AlAsSb, AlGaAsSb or AlInAsSb. The k value refers to the ratio of the hole impact ionization coefficient to the electron impact ionization coefficient of the material or the ratio of the electron impact ionization coefficient to the hole impact ionization coefficient of the material. The smaller value of the hole impact ionization coefficient and the electron impact ionization coefficient is divided by the larger value to finally obtain a value less than 1. When the k value of the material is low, most of the avalanche multiplication effect is generated by one carrier, and the prepared avalanche detector chip can obtain lower noise, which can improve the sensitivity and response characteristics of the avalanche diode.

[0037] In some exemplary embodiments, the material of the P-type contact layer 9 is a material with a high Zn diffusion coefficient, such as InGaAs, which can increase the surface doping concentration, obtain a better ohmic contact effect, reduce the resistance value of the chip, and increase the response rate.

[0038] In some exemplary embodiments, the material of the second transition layer 7 is a material with a low Zn diffusion coefficient, for example, weakly P-type doped InAlGaAs with a doping concentration of 1×10 15 cm -3 -1×10 16 cm -3. It can prevent Zn from continuing to diffuse downward to a certain extent, increase the accuracy of Zn diffusion, and effectively improve the reliability of the chip. Optionally, the doping type of the charge layer 4 is P-type doping, and the carrier concentration is 1×10 16 cm -3 -1×10 18 cm -3 .

[0039] In some exemplary embodiments, at least one of the following features is included: the thickness of the N-type contact layer 2 is 0.2μm-1μm; the thickness of the multiplication layer 3 is 50nm-200nm; the thickness of the charge layer 4 is 30nm-200nm; the thickness of the first transition layer 5 is 20nm-100nm; the thickness of the absorption layer 6 is 0.3μm-1μm; the thickness of the second transition layer 7 is 20nm-100nm; the thickness of the cap layer 8 is 0.2μm-1μm; the thickness of the P-type contact layer 9 is 0.1μm-1μm.

[0040] Figure 2 The flowchart of a method for preparing an avalanche photodetector chip according to an embodiment of the present invention is schematically shown.

[0041] like Figure 2 As shown, a method for preparing an avalanche photodetector chip according to an embodiment of the present invention includes steps S110-S180.

[0042] In step S110, epitaxial layers are grown: an N-type contact layer 2, a multiplication layer 3, a charge layer 4, a first transition layer 5, an absorption layer 6, a second transition layer 7, a cap layer 8, and a P-type contact layer 9 are sequentially epitaxially grown on a substrate 1 to obtain a sample including an epitaxial layer. The structure of the obtained epitaxial layer is shown in FIG. Figure 3 (a) in the figure.

[0043] In step S120, a diffusion hole is formed: silicon dioxide is grown as a diffusion barrier layer, and the diffusion barrier layer is etched by photolithography and etching processes to form a diffusion hole region.

[0044] For example, SiO with a thickness of 300 nm is grown by plasma enhanced chemical vapor deposition (PECVD). 2 Acting as a diffusion barrier layer, the barrier layer is then etched using photolithography and reactive ion etching (RIE) processes to open a diffusion hole, the diameter of the diffusion hole being W, and optionally, W being less than 20 μm.

[0045] In step S130, a zinc doped region 10 is prepared: a zinc diffusion source is spin-coated on the outer surface of the diffusion hole, and a zinc doped region 10 is formed in the diffusion hole region by a rapid thermal annealing process. The regional diffusion method can effectively reduce the surface electric field, thereby reducing the surface dark current of the chip.

[0046] For example, Zn diffusion source ZPDC is spin-coated on the surface, and the thickness of the diffusion source after spin coating is about 2um by changing the spin coating speed and time. After spin coating, oxygen plasma is used for 5 minutes at 300W to remove organic matter in the film. After oxygen plasma treatment, zinc doping area 10 is formed in the diffusion hole area by rapid thermal annealing. The temperature of rapid thermal annealing is 500℃-600℃. The chip structure after diffusion is shown in FIG. Figure 3 (b) in the figure.

[0047] In step S140, the inclined mesa is etched: silicon dioxide is grown as a mask, and the mask is etched by photolithography and etching processes to form an inclined mesa structure in the epitaxial layer area. The inclined mesa structure can not only reduce the facing area between the upper and lower mesa layers, reduce the parasitic capacitance of the chip, and improve the high-speed characteristics of the chip, but also does not add additional processes, making the preparation simpler. The structure after etching is shown in FIG. Figure 3 (c) in.

[0048] For example, PECVD is used to grow SiO with a thickness of 500 nm. 2 The layer acts as an etching mask, and then the mask is etched using photolithography and ICP etching processes to form an inclined table with an inclination angle of θ and an upper table diameter of L. Optionally, the upper table diameter L does not exceed 30um, and the table inclination angle θ is less than 45°. For two chips with the same W and table structure bottom, when the θ angle is large, the difference LW between the upper table and the diffusion hole is large, and the surface dark current is small. When the θ angle is small, the upper table L is small, which reduces the facing area of ​​the upper and lower tables, thereby reducing parasitic capacitance and improving response characteristics. Different θ angles can be selected according to actual applications during the preparation process.

[0049] In step S150, isolation mesa etching: growing silicon dioxide as a mask, etching to substrate 1 through photolithography and etching process, for isolating the chip, the structure after etching is shown in FIG. Figure 3 (d) in.

[0050] For example, PECVD is used to grow SiO with a thickness of 500 nm. 2 The layer acts as an etching mask, and then photolithography and ICP etching processes are used to isolate the chips, this time etching to the semi-insulating substrate 1 layer.

[0051] In step S160, a passivation layer 11 is grown: the passivation layer 11 is grown on the outer surface of the epitaxial layer and a portion of the side surface of the substrate 1. The structure after the passivation layer 11 is grown is shown in FIG. Figure 3 (e) in.

[0052] For example, the atomic layer deposition (ALD) process is used to grow Al with a thickness of 30nm. 2 O 3The passivation layer 11 is preferably formed by using organic solvents such as acetone, isopropanol, hydrofluoric acid solution, and deionized water to clean the sample surface before growing the passivation layer 11. After cleaning, the sample surface is treated at 530° C. for 9 minutes in a vacuum environment, and then Al is grown. 2 O 3 The passivation layer 11 can achieve a better passivation effect.

[0053] In step S170 , electrode windows are prepared: an N electrode 12 window and a P electrode 12 window are prepared on the passivation layer 11 by photolithography and etching processes.

[0054] For example, photolithography and RIE etching processes are used to prepare N-electrode 12 and P-electrode 12 windows on the passivation layer 11 . The P-electrode 12 window must be on the diffusion region, and the N-electrode 12 window must be located on the N-type contact layer 2 .

[0055] In step S180, electrodes are prepared: an N-electrode 12 is prepared on the side of the N-type contact layer 2 away from the substrate 1 and a P-electrode 12 is prepared on the side of the P-type contact layer 9 away from the substrate 1 by using photolithography, electron beam evaporation, and annealing processes. The structure after electrode preparation is shown in FIG. Figure 3 (f) in.

[0056] The high-speed detector chip prepared by the method according to the embodiment of the present invention has the characteristics of low dark current, high response speed and simple preparation, and has great application prospects in optical communication systems.

[0057] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An avalanche photodetector chip, characterized in that: include: substrate; as well as an epitaxial layer, located on the surface of the substrate, Wherein, the epitaxial layer comprises: An N-type contact layer is located on the surface of the substrate; a multiplication layer, located on a side of the N-type contact layer away from the substrate; A charge layer, located on a side of the multiplication layer away from the substrate; A first transition layer, located on a side of the charge layer away from the substrate; an absorption layer, located on a side of the first transition layer away from the substrate; A second transition layer, located on a side of the absorption layer away from the substrate; a cap layer, located on a side of the second transition layer away from the substrate; and A P-type contact layer is located on a side of the cap layer away from the substrate, The epitaxial layer includes an inclined mesa structure, the top surface of the inclined mesa structure is the surface of the P-type contact layer away from the substrate; and the bottom surface of the inclined mesa structure is the N-type contact layer.

2. The avalanche photodetector chip according to claim 1, characterized in that: The material of the multiplication layer includes one of aluminum arsenic antimony, aluminum gallium arsenic antimony or aluminum indium arsenic antimony.

3. The avalanche photodetector chip according to claim 1, characterized in that: The material of the P-type contact layer includes InGaAs.

4. The avalanche photodetector chip according to claim 1, characterized in that: The material of the second transition layer includes weakly P-type doped indium aluminum gallium arsenide with a doping concentration of 1×10 15 cm -3 -1×10 16 cm -3 .

5. The avalanche photodetector chip according to any one of claims 1 to 4, characterized in that: The middle area among the second transition layer, the cap layer and the P-type contact layer comprises a cylindrical zinc-doped area.

6. The avalanche photodetector chip according to any one of claims 1 to 4, characterized in that: The inclined table top angle of the inclined table top structure is less than 45°, and the surface dark current and parasitic capacitance can be adjusted by adjusting the size of the table top inclination angle.

7. The avalanche photodetector chip according to any one of claims 1 to 4, characterized in that: Also includes: An N electrode, located at a side of the N-type contact layer away from the substrate; A P electrode, located on a side of the P-type contact layer away from the substrate; A passivation layer is located on the outer surface of the epitaxial layer and a portion of the side surface of the substrate, and the passivation layer is disconnected at the N electrode and the P electrode.

8. The avalanche photodetector chip according to any one of claims 1 to 4, characterized in that: Includes at least one of the following features: The thickness of the N-type contact layer is 0.2 μm-1 μm; The thickness of the multiplication layer is 50nm-200nm; The thickness of the charge layer is 30nm-200nm; The thickness of the first transition layer is 20nm-100nm; The thickness of the absorption layer is 0.3 μm-1 μm; The thickness of the second transition layer is 20nm-100nm; The thickness of the cap layer is 0.2 μm-1 μm; The thickness of the P-type contact layer is 0.1 μm-1 μm.

9. A method for preparing an avalanche photodetector chip, characterized in that: include: Growing epitaxial layers: epitaxially growing an N-type contact layer, a multiplication layer, a charge layer, a first transition layer, an absorption layer, a second transition layer, a cap layer, and a P-type contact layer on a substrate in sequence to obtain a sample including an epitaxial layer; Opening diffusion holes: growing silicon dioxide as a diffusion barrier layer on the sample containing the epitaxial layer, and etching the diffusion barrier layer by photolithography and etching processes to form a diffusion hole region; Prepare the zinc-doped region: spin-coat a zinc diffusion source on the outer surface of the diffusion hole, and form a zinc-doped region in the diffusion hole region by a rapid thermal annealing process; Inclined mesa etching: growing silicon dioxide as a mask, etching the mask through photolithography and etching processes, and forming an inclined mesa structure in the epitaxial layer region; Isolation mesa etching: growing silicon dioxide as a mask, etching to the substrate through photolithography and etching processes to isolate the chip; Growing a passivation layer: growing a passivation layer on the outer surface of the epitaxial layer and a portion of the side surface of the substrate; Preparation of electrode windows: Preparation of N-electrode windows and P-electrode windows on the passivation layer by photolithography and etching processes; as well as Preparing electrodes: using photolithography, electron beam evaporation, and annealing processes to prepare an N electrode on a side of the N-type contact layer away from the substrate and a P electrode on a side of the P-type contact layer away from the substrate.

10. The method according to claim 9, characterized in that The temperature of the rapid thermal annealing process is 500° C.-600° C.; and / or The table top inclination angle of the inclined table top structure is less than 45°.

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