A modulation strategy for neutral point potential balance in a three-level three-phase four-leg inverter

Abstract

The present invention discloses a modulation strategy for balancing the midpoint potential of a three-level, three-phase, four-bridge-arm inverter, and belongs to the field of photovoltaic power generation. The modulation strategy includes the following steps: sampling the three-phase original modulation wave and the superimposed original zero-sequence modulation wave; splitting the original modulation waves of the remaining phases according to the phase with the smallest zero-level duty cycle; and generating a PWM signal to drive the inverter to work. In view of the problems that the midpoint potential of the three-level, three-phase, four-bridge-arm inverter fluctuates greatly, the existing control is complex, the DC side voltage utilization rate is low, and it is not conducive to promotion to engineering applications, the present invention balances the midpoint potential of the three-level, three-phase, four-bridge-arm inverter by splitting the original modulation wave to generate a new modulation wave without adding or changing any hardware. The calculation is simple, and it can be well combined with other modulation strategies. In addition, while having a good midpoint potential balancing effect, the DC side voltage utilization rate is also relatively high.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic power generation, and in particular to a modulation strategy for midpoint potential balance of a three-level three-phase four-bridge-arm inverter. Background Art

[0002] As a sustainable and clean energy, solar energy has many advantages. In recent years, photovoltaic power generation technology, as a method to effectively utilize solar energy resources, has received widespread attention and support.

[0003] In photovoltaic systems, three-level inverters offer a range of advantages over traditional two-level inverters, including lower output harmonic content, reduced losses, higher switching frequencies, lower costs, reduced electromagnetic interference, improved stability, and higher reliability. The three-phase, four-leg inverter topology is widely used in photovoltaic power generation systems due to its unbalanced load handling capabilities, flexible control, high DC voltage utilization, and compact size and weight.

[0004] However, due to the limitations of the three-phase four-leg inverter's topology, when the bridge arm output state is zero level, current will flow into the midpoint of the DC side capacitor, causing fluctuations in the midpoint potential. The midpoint potential fluctuation will affect the output waveform quality. If it is not controlled, it may cause excessive midpoint imbalance, causing the inverter to malfunction and further cause the entire device to crash and shut down. Therefore, the midpoint balance problem of the three-level three-phase four-leg inverter is the core issue for the inverter to work properly. Many experts and scholars have studied the suppression of midpoint balance and proposed many solutions:

[0005] The Chinese invention patent disclosure specification "A midpoint voltage balancing method for a three-phase four-bridge-arm three-level inverter" (CN118074554A) provides a three-phase four-bridge-arm midpoint voltage balancing method that adjusts the size of the modulation wave by real-time sampling of various electrical quantities and closed-loop calculation of the positive and negative equalizing loop gains. This method can balance the midpoint voltage within the full power factor range, but the auxiliary circuit and control are too complex, and due to the limitations of the control, the midpoint potential always fluctuates to a certain extent, which increases the cost of selecting DC side capacitors. In addition, the fourth bridge arm is used to balance the midpoint potential and cannot be used as a zero-sequence channel, which also makes the utilization rate of the DC side voltage low.

[0006] The Chinese invention patent disclosure specification "A method for suppressing midpoint potential drift in a three-phase, four-leg, three-level inverter" (CN101510736A) proposes a modulation strategy that separately selects the switching states of the first three bridge arms and the fourth bridge arm and uses paired long vectors to replace the midpoint vector to suppress midpoint potential fluctuations. This can make the current flowing into the midpoint of the DC side capacitor have an average value of zero within one cycle. However, the vector control algorithm is relatively complex and the fourth bridge arm is also used to balance the midpoint potential, so it cannot be used as a zero-sequence channel, resulting in a relatively low utilization rate of the DC side voltage.

[0007] In summary, the prior art still has the following problems:

[0008] 1. In the existing modulation method, the fourth bridge arm is used to balance the midpoint potential and cannot be used as a zero-sequence channel. The utilization rate of the DC side voltage is relatively low.

[0009] 2. The existing modulation method has a cumbersome calculation process, a complex implementation algorithm, high cost, and is difficult to implement and apply to engineering projects;

[0010] 3. The existing modulation method cannot be combined with other modulation strategies to optimize two control objectives at the same time; Summary of the Invention

[0011] The technical problems to be solved by the present invention are the problems existing in the above-mentioned prior art. Specifically, based on the three-level three-phase four-leg inverter topology, a modulation strategy is proposed without adding or changing any hardware to balance the midpoint potential of the three-level three-phase four-leg inverter.

[0012] The object of the present invention is achieved in this way. The present invention provides a modulation strategy for balancing the midpoint potential of a three-level three-phase four-bridge-leg inverter. The three-level three-phase four-bridge-leg inverter includes a DC voltage source V DC , two DC bus capacitors, a bridge arm system and a load system; the two DC bus capacitors are connected in series and then connected to a DC voltage source V DC Between the DC positive bus and the DC negative bus, and the connection point of the two DC bus capacitors is marked as point Q;

[0013] The bridge arm system includes 12 switch tubes with anti-parallel diodes, which are denoted as switch tubes S kj , where k represents the phase sequence, k = a, b, c, n; j represents the serial number of the switch tube, j = 1, 2, 3, 4; where the switch tube S k1 , switch tube S k2 , switch tube S k3 and switch tube S k4 The k-phase bridge arm is formed. Specifically, the switch tube S k1 The collector of is connected to the DC positive bus, and the switch tube S k1 The emitter and the switch tube Sk3 The collector of the switch tube S k4 The collector of the k , switch tube S k3 The emitter and the switch tube S k2 The emitter of the switch S K2 The collector of the switch is connected to point Q, and the switch tube S k4 The emitter is connected to the DC negative bus;

[0014] The load system includes an inductor L a , L b , L c , L n , capacitor C a , C b , C c and load Z a , Z b , Z c , where load Z a , Z b , Z c Connect one end of the resistor and mark the junction as point N, and connect the other end to the inductor L according to the phase sequence. a , L b , L c , inductance L a , L b , L c The other end is connected to the point P of the same phase sequence k Inductance L n One end contact point P n , the other end is connected to point N; capacitor C a , C b , C c One end of the resistors is connected together and to point N, and the other end is connected between the inductor and the load in the same phase sequence;

[0015] The modulation strategy includes the following steps:

[0016] Step 1: Sample the three-phase original modulation wave and the superimposed original zero-sequence modulation wave

[0017] The a-phase bridge arm, the b-phase bridge arm and the c-phase bridge arm are recorded as the three-phase bridge arm, and the n-phase bridge arm is recorded as the fourth bridge arm; the three-phase original modulation wave U is obtained by sampling from the three-phase bridge arm. a , U b , U c , respectively, the three-phase original modulation wave U a , U b , U c The three-phase output zero-level duty cycle d is obtained by intersecting with the carrier a0 , d b0 , d c0;

[0018] According to the value of the three-phase output zero-level duty cycle d a0 , d b0 , d c0 Denoted as the maximum zero-level duty cycle d max0 , intermediate zero-scale duty cycle d mid0 and minimum zero-scale duty cycle d min0 and the maximum zero-scale duty cycle d max0 The corresponding original modulation wave is recorded as the zero-level duty cycle maximum phase modulation wave U max , intermediate zero-scale duty cycle d mid0 The corresponding original modulation wave is recorded as the zero-level duty cycle intermediate phase modulation wave U mid , minimum zero-level duty cycle d min0 The corresponding original modulation wave is recorded as the zero-level duty cycle minimum phase modulation wave U min ; The original zero-sequence modulation wave U is obtained by sampling from the fourth bridge arm n and intercepted with the carrier to obtain the fourth bridge arm output zero-level duty cycle d n0 ;

[0019] Step 2: Split the original modulation waves of the remaining phases according to the phase with the minimum zero-level duty cycle

[0020] Let the minimum zero-level duty cycle d be maintained after splitting min0 unchanged, the intermediate zero-level duty cycle d mid0 , maximum zero-level duty cycle d max0 And the fourth bridge arm outputs zero-level duty cycle d n0 After splitting, the following conditions should be met:

[0021] d max0 =d mid0 =d n0 =d min0

[0022] in,

[0023] According to the zero-level duty cycle minimum phase modulation wave U min Split zero level duty cycle maximum phase modulation wave U max , zero-level duty cycle intermediate phase modulation wave U mid and the original zero-sequence modulation wave U n , the situation after splitting is as follows:

[0024] By splitting, the zero-level duty cycle maximum phase modulation wave U max Split into the maximum phase modulation wave U maxp and the maximum phase modulation wave U maxd , where the maximum phase modulation wave U maxp>0, maximum phase modulation wave U maxd ≤0, and satisfy:

[0025]

[0026] By splitting, the zero-level duty cycle intermediate phase modulation wave U mid Split into intermediate phase modulation wave U midp and the intermediate phase down-modulation wave U midd , where the intermediate phase modulation wave U midp >0, intermediate phase modulated wave U midd ≤0, and satisfy:

[0027]

[0028] By splitting, the original zero-sequence modulation wave U n Split into zero sequence up-modulation wave U np and zero sequence modulation wave U nd , where the zero sequence modulation wave U np >0, zero sequence modulation wave U nd ≤0, and satisfy:

[0029]

[0030] In addition, the zero-level duty cycle minimum phase modulation wave U will not be split min According to the following method, the minimum phase modulation wave U is obtained. minp and the minimum phase modulation wave U mind :

[0031]

[0032] The upper modulation wave and the lower modulation wave obtained after the above splitting and processing are restored to the corresponding three-phase bridge arm and the fourth bridge arm to obtain the upper modulation wave U kp And the down-modulation wave U kd , where the upper modulation wave U kp The range is (0, 1], the modulated wave U kd The range is [-1, 0];

[0033] Step 3: Generate PWM signal to drive the inverter

[0034] The carrier is divided into upper carrier T p and download Wave T d , where the upper carrier T p The range is (0, 1], download wave T d The range is [-1, 0]; the upper modulation wave U kp With upper carrier T p The PWM signal generated by the intersection drives the switch tube Sk1 , switch tube S k2 and switch tube S k3 Working, down-modulation wave U kd Download Wave T d The PWM signal generated by the intersection drives the switch tube S k2 , switch tube S k3 and switch tube S k4 Work.

[0035] Preferably, the carrier wave is two stacked triangular carrier waves.

[0036] Compared with the prior art, the beneficial effects of the present invention are embodied in:

[0037] 1. In the modulation strategy of the present invention, the fourth bridge arm can be used as a zero-sequence channel and can be combined with multiple modulation strategies. The DC side voltage utilization rate is relatively high, and multiple control objectives can be optimized simultaneously.

[0038] 2. The modulation strategy of the present invention can balance the midpoint potential of a three-level three-phase four-leg inverter without adding or modifying any hardware.

[0039] 3. The modulation strategy of the present invention has a simple algorithm, does not require additional configuration and complex calculations, is easy to apply to engineering practice, and is applicable to both open-loop and closed-loop control. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 4 is a topology diagram of a three-level, three-phase, four-leg inverter in an embodiment of the present invention.

[0041] Figure 2 Flowchart of the modulation strategy of the present invention.

[0042] Figure 3 This is a waveform diagram of the modulation wave after the traditional saddle wave modulation is split using the modulation strategy of the present invention in an embodiment of the present invention.

[0043] Figure 4 This is a simulated waveform diagram of the midpoint potential after the modulation wave is split by using the modulation strategy of the present invention in an embodiment of the present invention to modulate the traditional saddle wave modulation.

[0044] Figure 5 This is a simulated waveform diagram of the midpoint potential using the traditional saddle wave modulation strategy in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0046] Figure 1 is a topology diagram of a three-level three-phase four-leg inverter according to an embodiment of the present invention, Figure 1It can be seen that the three-level three-phase four-bridge-arm inverter includes a DC voltage source V DC , two DC bus capacitors, a bridge arm system and a load system; the two DC bus capacitors are connected in series and then connected to a DC voltage source V DC Between the DC positive bus and the DC negative bus, and the connection point of the two DC bus capacitors is marked as point Q;

[0047] The bridge arm system includes 12 switch tubes with anti-parallel diodes, which are denoted as switch tubes S kj , where k represents the phase sequence, k = a, b, c, n; j represents the serial number of the switch tube, j = 1, 2, 3, 4; where the switch tube S k1 , switch tube S k2 , switch tube S k3 and switch tube S k4 The k-phase bridge arm is formed. Specifically, the switch tube S k1 The collector of is connected to the DC positive bus, and the switch tube S k1 The emitter and the switch tube S k3 The collector of the switch tube S k4 The collector of the k , switch tube S k3 The emitter and the switch tube S k2 The emitter of the switch S K2 The collector of the switch is connected to point Q, and the switch tube S k4 The emitter is connected to the DC negative bus;

[0048] The load system includes an inductor L a , L b , L c , L n , capacitor C a , C b , C c and load Z a , Z b , Z c , where load Z a , Z b , Z c Connect one end of the resistor and mark the junction as point N, and connect the other end to the inductor L according to the phase sequence. a , L b , L c , inductance L a , L b , L c The other end is connected to the point P of the same phase sequence k Inductance L n One end contact point P n , the other end is connected to point N; capacitor C a , C b , Cc One end of the resistors is connected together and to point N, and the other end is connected between the inductor and the load in the same phase sequence;

[0049] exist Figure 1 In FIG, C1 is the first DC bus capacitor, C2 is the second DC bus capacitor, LEG is the bridge arm system, and LOAD is the load system.

[0050] Figure 2 Flowchart of the modulation strategy of the present invention. As can be seen from the figure, the modulation strategy includes the following steps:

[0051] Step 1: Sample the three-phase original modulation wave and the superimposed original zero-sequence modulation wave

[0052] The a-phase bridge arm, the b-phase bridge arm and the c-phase bridge arm are recorded as the three-phase bridge arm, and the n-phase bridge arm is recorded as the fourth bridge arm; the three-phase original modulation wave U is obtained by sampling from the three-phase bridge arm. a , U b , U c , respectively, the three-phase original modulation wave U a , U b , U c The three-phase output zero-level duty cycle d is obtained by intersecting with the carrier a0 , d b0 , d c0 ;

[0053] According to the value of the three-phase output zero-level duty cycle d a0 , d b0 , d c0 Denoted as the maximum zero-level duty cycle d max0 , intermediate zero-scale duty cycle d mid0 and minimum zero-scale duty cycle d min0 and the maximum zero-scale duty cycle d max0 The corresponding original modulation wave is recorded as the zero-level duty cycle maximum phase modulation wave U max , intermediate zero-scale duty cycle d mid0 The corresponding original modulation wave is recorded as the zero-level duty cycle intermediate phase modulation wave U mid , minimum zero-level duty cycle d min0 The corresponding original modulation wave is recorded as the zero-level duty cycle minimum phase modulation wave U min ; The original zero-sequence modulation wave U is obtained by sampling from the fourth bridge arm n and intercepted with the carrier to obtain the fourth bridge arm output zero-level duty cycle d n0 ;

[0054] Step 2: Split the original modulation waves of the remaining phases according to the phase with the minimum zero-level duty cycle

[0055] Let the minimum zero-level duty cycle d be maintained after splitting min0unchanged, the intermediate zero-level duty cycle d mid0 , maximum zero-level duty cycle d max0 And the fourth bridge arm outputs zero-level duty cycle d n0 After splitting, the following conditions should be met:

[0056] d max0 =d mid0 =d n0 =d min0

[0057] in,

[0058] According to the zero-level duty cycle minimum phase modulation wave U min Split zero level duty cycle maximum phase modulation wave U max , zero-level duty cycle intermediate phase modulation wave U mid and the original zero-sequence modulation wave U n , the situation after splitting is as follows:

[0059] By splitting, the zero-level duty cycle maximum phase modulation wave U max Split into the maximum phase modulation wave U maxp and the maximum phase modulation wave U maxd , where the maximum phase modulation wave U maxp >0, maximum phase modulation wave U maxd ≤0, and satisfy:

[0060]

[0061] By splitting, the zero-level duty cycle intermediate phase modulation wave U mid Split into intermediate phase modulation wave U midp and the intermediate phase down-modulation wave U midd , where the intermediate phase modulation wave U midp >0, intermediate phase modulated wave U midd ≤0, and satisfy:

[0062]

[0063] By splitting, the original zero-sequence modulation wave U n Split into zero sequence up-modulation wave U np and zero sequence modulation wave U nd , where the zero sequence modulation wave U np >0, zero sequence modulation wave U nd ≤0, and satisfy:

[0064]

[0065] In addition, the zero-level duty cycle minimum phase modulation wave U will not be split minAccording to the following method, the minimum phase modulation wave U is obtained. minp and the modulation wave U under minimum phase mind :

[0066]

[0067] The upper modulation wave and the lower modulation wave obtained after the above splitting and processing are restored to the corresponding three-phase bridge arm and the fourth bridge arm to obtain the upper modulation wave U kp and down-modulation wave U kd , where the upper modulation wave U kp The range is (0, 1], the modulated wave U kd The range is [-1, 0];

[0068] Step 3: Generate PWM signal to drive the inverter

[0069] The carrier is divided into upper carrier T p and download Wave T d , where the upper carrier T p The range is (0, 1], download wave T d The range is [-1, 0]; the upper modulation wave U kp With upper carrier T p The PWM signal generated by the intersection drives the switch tube S k1 , switch tube S k2 and switch tube S k3 Working, down-modulation wave U kd Download Wave T d The PWM signal generated by the intersection drives the switch tube S k2 , switch tube S k3 and switch tube S k4 Work.

[0070] In this embodiment, the carrier wave is two stacked triangular carrier waves.

[0071] In order to verify the proposed modulation strategy's ability to balance the midpoint potential of a three-level three-phase four-leg inverter, a MATLAB / Simulink simulation model of a three-level three-phase four-leg inverter was built. The simulation parameters are as follows: DC voltage source V DC The voltage value is 700V, the capacitance of capacitors C1 and C2 are both 50uF, and the inductor L a , L b , L c , L n The inductance value is 0.1mH, the capacitor C a , C b , C c The capacitance value is 16uF, and the load Z a , Z b , Zc The load resistance is 10Ω and the PWM switching frequency is 5kHz.

[0072] Figure 3 This is a waveform diagram of the modulation wave after the modulation strategy of the present invention is used to split the modulation wave of the traditional saddle wave modulation in an embodiment of the present invention. It can be seen that the modulation wave corresponding to each phase bridge arm is split into an upper modulation wave and a lower modulation wave. Figure 4 This is a simulated waveform diagram of the midpoint potential after the modulation wave is split by the traditional saddle wave modulation using the modulation strategy of the present invention in an embodiment of the present invention. It can be seen that the DC side bus capacitor voltage is stable at about half of the DC side voltage source voltage, and the midpoint potential fluctuation range of the three-level three-phase four-leg inverter is within ±2.5V. Figure 5 This is a simulated waveform diagram of the midpoint potential using the traditional saddle wave modulation strategy in an embodiment of the present invention. The midpoint potential fluctuation range of the three-level three-phase four-leg inverter is about ±25V. It can be seen that the modulation strategy of the present invention has a good inhibitory effect on the midpoint potential fluctuation of the three-level three-phase four-leg inverter.

Claims

1. A modulation strategy for neutral point potential balance of a three-level three-phase four-leg inverter, wherein the three-level three-phase four-leg inverter includes a DC voltage source V DC , two DC bus capacitors, a bridge arm system and a load system; the two DC bus capacitors are connected in series and then connected to a DC voltage source V DC The DC positive bus and DC negative bus are connected, and the point where the two DC bus capacitors meet is marked as point Q ; The bridge arm system includes 12 switch tubes with anti-parallel diodes, which are recorded as switch tubes S kj ,in k Indicates the phase sequence, k = a , b , c , n ; j Indicates the serial number of the switch tube, j = 1 , 2 , 3 , 4 ;in, Switching tube S k1 , switch tube S k2 , switch tube S k3 and switch tube S k4 constitute k Phase bridge arm, specifically, switch tube S k1 The collector of the switch is connected to the DC positive bus. S k1 The emitter and switch tube S k3 Collector, switch tube S k4 The collector of P k ,in, k Indicates the phase sequence, k = a , b , c , n ; Switching tube S k3 The emitter and switch tube S k2 The emitter connection of the switch tube S K2 The collector is connected to the point Q , switch tube S k4 The emitter is connected to the DC negative bus; The load system includes an inductor L a , L b , L c , L n ,capacitance C a , C b , C c and load Z a , Z b , Z c , where load Z a , Z b , Z c Connect one end of the N , the other end is connected to the inductor according to the phase sequence L a , L b , L c ,inductance L a , L b , L c The other end is connected to the points of their respective phase sequences P k ;inductance L n One end contact P n , the other end is connected to point N ;capacitance C a , C b , C c Connect one end together and connect to point N , the other end is connected between the inductor and the load of each phase sequence; It is characterized in that the modulation strategy includes the following steps: Step 1: Sample the three-phase original modulation wave and the superimposed original zero-sequence modulation wave Will a Phase bridge arm, b Phase bridge arm and c The bridge arm is recorded as a three-phase bridge arm. n The phase bridge arm is recorded as the fourth bridge arm; the three-phase original modulation wave is obtained by sampling from the three-phase bridge arm U a , U b , U c , respectively, the three-phase original modulation wave U a , U b , U c The three-phase output zero-level duty cycle is obtained by intersecting with the carrier d a0 , d b0 , d c0 ; The three-phase output zero-level duty cycle is set according to its value d a0 , d b0 , d c0 The maximum zero-level duty cycle d max0 , intermediate zero-scale duty cycle d mid0 and minimum zero-scale duty cycle d min0 and the maximum zero-scale duty cycle d max0 The corresponding original modulation wave is recorded as the zero-level duty cycle maximum phase modulation wave U max , intermediate zero-scale duty cycle d mid0 The corresponding original modulation wave is recorded as the zero-level duty cycle intermediate phase modulation wave U mid , minimum zero-scale duty cycle d min0 The corresponding original modulation wave is recorded as the zero-level duty cycle minimum phase modulation wave U min ; The original zero-sequence modulation wave is obtained by sampling from the fourth bridge arm U n And the fourth bridge arm outputs zero-level duty cycle by intersecting with the carrier d n0 ; Step 2: Split the original modulation waves of the remaining phases according to the phase with the minimum zero-level duty cycle Keep the minimum zero-level duty cycle after splitting d min0 Unchanged, intermediate zero-level duty cycle d mid0 , maximum zero-scale duty cycle d max0 And the fourth bridge arm outputs zero-level duty cycle d n0 After splitting, the following conditions should be met: ； in, ; According to the zero-level duty cycle minimum phase modulation wave U min Split zero-level duty cycle maximum phase modulation wave U max , zero-level duty cycle intermediate phase modulation wave U mid and the original zero-sequence modulation wave U n , the situation after splitting is as follows: By splitting the zero-level duty cycle to maximize the phase modulation wave U max Split into maximum phase modulation wave U maxp and the modulation wave at maximum phase U maxd , where the maximum phase modulation wave U maxp >0, maximum phase modulation wave U maxd ≤0, and satisfy: ； By splitting, zero-level duty cycle interphase modulated wave U mid Split into intermediate phase modulated waves U midp and mid-phase down-modulation wave U midd , where the intermediate phase modulated wave U midp >0, mid-phase down-modulation wave U midd ≤0, and satisfy: ； By splitting, the original zero-sequence modulation wave U n Split into zero sequence up-modulation wave U np and zero sequence modulated wave U nd , where the zero sequence modulation wave U np >0, zero sequence modulated wave U nd ≤0, and satisfy: ； In addition, the zero-level duty cycle minimum phase modulation wave will not be split U min According to the following method, the minimum phase modulation wave is obtained U minp and the minimum phase modulation wave U mind : ； The upper modulation wave and the lower modulation wave obtained after the above splitting and processing are restored to the corresponding three-phase bridge arm and the fourth bridge arm to obtain the upper modulation wave U kp and down-modulation wave U kd , where the up-modulation wave U kp The range is (0,1], the modulated wave U kd The range is [-1,0]; Step 3: Generate PWM signal to drive the inverter Divide the carrier into upper carrier T p and download waves T d , where the upper carrier T p The range is (0,1], download wave T d The range is [-1,0]; the upper modulation wave U kp With upper carrier T p Intersection generates PWM signal to drive the switch tube S k1 , switch tube S k2 and switch tube S k3 Working, down-modulation wave U kd With Download Wave T d Intersection generates PWM signal to drive the switch tube S k2 , switch tube S k3 and switch tube S k4 Work.

2. The modulation strategy for neutral point potential balance of a three-level three-phase four-leg inverter according to claim 1, characterized in that: The carrier waves are two stacked triangular carrier waves.

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