Self-recovery single-particle-resistant multi-bit upset latch circuit structure

Abstract

The invention discloses a self-recovery single-particle-resistant multi-bit upset latch circuit structure. The self-recovery single-particle-resistant multi-bit upset latch circuit structure comprises a clock control inverter circuit, a latch unit, an SEU monitoring unit, an output control unit and an inverter circuit. The output end of the first clock control inverter circuit is connected with the input end of the first latch unit and the input end of the SEU monitoring unit; the output end of the second clock control inverter circuit is connected with the input end of the first latch unit and the input end of the SEU monitoring unit; the output end of the first latch unit is connected with the input end of the SEU monitoring unit and the input end of the output control unit; the output end of the third clock control inverter circuit and the output end of the fourth clock control inverter circuit are connected with the two input ends of the second latch unit respectively. The output end of the second latch unit is connected with the input end of the output control unit; and the output end of the SEU monitoring unit is connected with the input end of the output control unit. The method has good single-particle reinforcement capability, and single-particle multi-bit upset reinforcement can be realized.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and in particular relates to a self-recovering single-particle resistant multi-bit flip latch circuit structure. Background Art

[0002] Single event upset (SEU) refers to the phenomenon that the sensitive area of ​​an integrated circuit device is bombarded by a single high-energy particle, causing the logical state of the device to flip. Single particle upsets mainly occur in sequential circuits. When high-energy particles bombard the sensitive nodes of the sequential circuit, the charged particles interact with the semiconductor material to generate electron-hole pairs. These carriers move under the action of concentration gradients and electric fields and accumulate at sensitive nodes. When they reach a certain level, they will change the electrical level at the sensitive node, and the storage state of the sequential circuit will change, which is a single particle upset. The erroneous data generated by single particle upsets may lead to erroneous instructions and cause system dysfunction, and in severe cases, catastrophic accidents may occur.

[0003] In integrated circuit design, latch circuit is one of the most basic units, and its radiation resistance is very critical and important. With the reduction of process size, the storage charge of sensitive nodes is reduced, and the single particle incident trajectory covers multiple devices. These problems affect the ability of integrated circuits to resist single particle upsets. The radiation resistance reinforcement technology for single particle upsets will become the focus of research.

[0004] At present, widely used circuit structures to enhance resistance to single-particle upsets, such as DICE structure, triple-mode redundant structure, transistor stacking, etc., have been proven to be effective in resisting single-particle upsets. However, with the advancement of technology and the reduction of device size, the reinforcement effect of these structures has become increasingly poor, and they cannot be used to resist single-particle multi-bit upsets. They cannot meet the single-particle reinforcement requirements under advanced nanotechnology. Summary of the invention

[0005] The technology of the present invention solves the problem: overcomes the shortcomings of the prior art and provides a self-recovering single-particle multi-bit flip-resistant latch circuit structure, aiming to achieve multi-bit single-particle flip-resistant reinforcement.

[0006] In order to solve the above technical problems, the present invention discloses a self-recovering single-particle multi-bit flip-over resistant latch circuit structure, comprising: a clock-controlled inverter circuit, a latch unit, an output control unit, an SEU monitoring unit and an inverter circuit; wherein the clock-controlled inverter circuit comprises: a first clock-controlled inverter circuit, a second clock-controlled inverter circuit, a third clock-controlled inverter circuit and a fourth clock-controlled inverter circuit; the latch unit comprises: a first latch unit and a second latch unit;

[0007] An output terminal of the first clock-controlled inverter circuit is connected to an input terminal in1 of the first latch unit and an input terminal in1 of the SEU monitoring unit;

[0008] The output terminal of the second clock-controlled inverter circuit is connected to the input terminal in2 of the first latch unit and the input terminal in3 of the SEU monitoring unit;

[0009] An output terminal of the third clock-controlled inverter circuit is connected to an input terminal in1 of the second latch unit;

[0010] An output terminal of the fourth clock-controlled inverter circuit is connected to an input terminal in2 of the second latch unit;

[0011] The output terminal out1 of the first latch unit is connected to the input terminal in1 of the output control unit and the input terminal in2 of the SEU monitoring unit; the output terminal out2 of the first latch unit is connected to the input terminal in4 of the SEU monitoring unit;

[0012] The output terminal out1 of the second latch unit is connected to the input terminal in2 of the output control unit;

[0013] The output terminal S1 and the output terminal S1N of the SEU monitoring unit are respectively connected to the input terminal S1 and the input terminal S1N of the output control unit;

[0014] The inverter circuit is used to provide a clock signal CK1 and a clock signal CK2 to the clock control inverter circuit, the latch unit and the SEU monitoring unit.

[0015] In the above-mentioned self-recovering single-particle resistant multi-bit flip latch circuit structure, the inverter circuit includes: a first inverter circuit and a second inverter circuit; wherein the first inverter circuit and the second inverter circuit are connected in series; the first inverter circuit is used to provide a clock signal CK1 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit; the second inverter circuit is used to provide a clock signal CK2 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit.

[0016] In the above-mentioned self-recovering single-particle resistant multi-bit flip latch circuit structure, the input end of the first inverter circuit is connected to the input clock signal CLK; the first inverter circuit outputs the clock signal CK1, and the second inverter circuit outputs the clock signal CK2; wherein, the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is the inverted signal of the clock signal CLK, and the clock signal CK2 is the inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the latch circuit.

[0017] In the above self-recovering single-particle multi-bit flip-over latch circuit structure, the clock-controlled inverter circuit is: an inverter circuit controlled by a set of complementary clock signals, including: a PMOS tube P21, a PMOS tube P22, an NMOS tube N22 and an NMOS tube N21;

[0018] The PMOS tube P21, the PMOS tube P22, the NMOS tube N22 and the NMOS tube N21 are connected in series in sequence;

[0019] The gate of the PMOS tube P22 is connected to the clock signal CK2;

[0020] The gate of the NMOS tube N22 is connected to the clock signal CK1;

[0021] The gate of the PMOS transistor P21 and the gate of the NMOS transistor N21 serve together as the input terminal of the clock control inverter circuit for receiving an input signal.

[0022] In the above self-recovering single-particle multi-bit flip-over resistant latch circuit structure, the latch unit is a DICE structure, including: inverter D31, inverter D32, inverter D33 and inverter D34; wherein, inverter D31 includes: PMOS tube P31 and NMOS tube N31 connected in series; inverter D32 includes: PMOS tube P32, PMOS tube P33, NMOS tube N33 and NMOS tube N32 connected in series in sequence; inverter D33 includes: PMOS tube P34 and NMOS tube N34 connected in series; inverter D34 includes: PMOS tube P35, PMOS tube P36, NMOS tube N36 and NMOS tube N35 connected in series in sequence;

[0023] The input signal in1 is connected to the drain of the PMOS tube P33, the drain of the NMOS tube N33, the gate of the PMOS tube P34 and the gate of the NMOS tube N31;

[0024] The input signal in2 is connected to the drain of the PMOS tube P36, the drain of the NMOS tube N36, the gate of the PMOS tube P31 and the gate of the NMOS tube N34;

[0025] The output signal out1 is connected to the drain of the PMOS tube P34, the drain of the NMOS tube N34, the gate of the PMOS tube P35 and the gate of the NMOS tube N32;

[0026] The output signal out2 is connected to the drain of the PMOS tube P31, the drain of the NMOS tube N31, the gate of the PMOS tube P32 and the gate of the NMOS tube N35;

[0027] The gate of the PMOS tube P33 and the gate of the PMOS tube P36 are connected to the clock signal CK1;

[0028] The gate of the NMOS transistor N33 and the gate of the NMOS transistor N36 are connected to the clock signal CK2.

[0029] In the above self-recovering single-particle anti-multi-bit flip latch circuit structure, the output control unit includes: an inverter D41, an inverter D42 and an inverter D43; wherein the inverter D41 includes: a PMOS tube P41, a PMOS tube P42, an NMOS tube N42 and an NMOS tube N41 connected in series in sequence; the inverter D42 includes: a PMOS tube P43, a PMOS tube P44, an NMOS tube N44 and an NMOS tube N43 connected in series in sequence; the inverter D43 includes: a PMOS tube P45 and an NMOS tube N45 connected in series;

[0030] The input signal in1 is connected to the gate of the PMOS tube P41 and the gate of the NMOS tube N41;

[0031] The input signal in2 is connected to the gate of the PMOS tube P43 and the gate of the NMOS tube N43;

[0032] The gate of the PMOS transistor P42 and the gate of the NMOS transistor N44 are connected to the input control signal S1;

[0033] The gate of the NMOS transistor N42 and the gate of the PMOS transistor P44 are connected to the input control signal S1N;

[0034] The output end of the inverter D41 and the output end of the inverter D42 are commonly connected to the input end of the inverter D43;

[0035] The output terminal of the inverter D43 serves as the output terminal out of the output control unit.

[0036] In the above-mentioned self-recovery single-particle anti-multi-bit flip latch circuit structure, for the output control unit, when the input control signal S1 is a low level "0" and the input control signal S1N is a high level "1", the PMOS tube P42 and the NMOS tube N42 are in the on state, the PMOS tube P44 and the NMOS tube N44 are in the off state, and the state of the input signal in1 is transmitted to the output terminal out through the inverter D41 and the inverter D43; conversely, when the input control signal S1 is a high level "1" and the input control signal S1N is a low level "0", the PMOS tube P42 and the NMOS tube N42 are in the off state, the PMOS tube P44 and the NMOS tube N44 are in the on state, and the state of the input signal in2 is transmitted to the output terminal out through the inverter D42 and the inverter D43.

[0037] In the above self-recovering single-particle multi-bit flip latch circuit structure, the SEU monitoring unit includes: XOR gate XOR1, XOR gate XOR2, XOR gate XOR3, inverter D51, inverter D52, inverter D53, inverter D54, inverter D55, inverter D56 and OR gate OR1; wherein the inverter D51 includes: PMOS tube P51, NMOS tube N51 and NMOS tube N53; the drain of PMOS tube P51, the drain of NMOS tube N51 and the drain of NMOS tube N53 are used as the output end of inverter D51; inverter D52 includes: PMOS tube P5 2. NMOS tube N52 and NMOS tube N54; the drain of PMOS tube P52, the drain of NMOS tube N52 and the drain of NMOS tube N54 are used as the output end of inverter D52; inverter D53 includes: PMOS tube P55, PMOS tube P56, NMOS tube N56 and NMOS tube N55 connected in series in sequence; inverter D54 includes: PMOS tube P57 and NMOS tube N57 connected in series; inverter D55 includes: PMOS tube P58 and NMOS tube N58 connected in series; inverter D56 includes: PMOS tube P59 and NMOS tube N59 connected in series;

[0038] The input signals in1 and in2 are connected to the two input terminals of the XOR gate XOR1 respectively; the output terminal of the XOR gate XOR1 is connected to the input terminal of the inverter D51, that is, the gate of the PMOS tube P51;

[0039] The input signals in3 and in4 are connected to the two input terminals of the XOR gate XOR2 respectively; the output terminal of the XOR gate XOR2 is connected to the input terminal of the inverter D52, that is, the gate of the PMOS tube P52;

[0040] Input signals in2 and in4 are connected to the two input terminals of XOR gate XOR3 respectively;

[0041] The output terminal of the inverter D51 is connected to the gate of the PMOS tube P55 and the gate of the NMOS tube N55;

[0042] The output terminal of the inverter D52 is connected to the gate of the PMOS tube P56 and the gate of the NMOS tube N56;

[0043] The output end of the inverter D53 and the output end of the XOR gate XOR3 are respectively connected to the two input ends of the OR gate OR1; in addition, the output end of the inverter D53 is connected to the input end of the inverter D54;

[0044] The output terminal of the inverter D54 is connected to the gate of the NMOS tube N51 and the gate of the NMOS tube N52;

[0045] The output terminal of the OR gate OR1 is connected to the gate of the PMOS tube P58;

[0046] The gate of the NMOS tube N53, the gate of the NMOS tube N54 and the gate of the NMOS tube N58 are used as the clock input terminal of the SEU monitoring unit, and are used to receive the clock signal CK1;

[0047] The inverter D55 outputs a control signal S1 , and the inverter D56 outputs a control signal S1N; wherein the control signal S1 and the control signal S1N are complementary signals, that is, the signal S1N is an inverted signal of the signal S1 .

[0048] In the above-mentioned self-recovering single-particle multi-bit flip latch circuit structure, for the SEU monitoring unit, when the clock signal CK1 is at a high level "1", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in an on state, the output control signal S1 maintains a low level "0", and the output control signal S1N maintains a high level "1". At this time, the SEU monitoring unit is in a functional off state; when the clock signal CK1 is at a low level "0", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in an off state, and the SEU monitoring unit function is turned on.

[0049] In the above self-recovering single-particle-resistant multi-bit flip latch circuit structure, the latch uses a combination of circuit reinforcement technology and layout reinforcement technology to achieve single-particle flip resistance reinforcement of internal nodes.

[0050] The present invention has the following advantages:

[0051] (1) The present invention discloses a self-recovering single-particle multi-bit flip-resistant latch circuit structure, which determines whether an irreversible single-particle flip occurs in a latch unit through an SEU monitoring unit. If so, the output control unit circuit automatically switches to a spare latch unit to achieve single-particle flip reinforcement.

[0052] (2) The present invention discloses a self-recovering single-particle multi-bit flip-resistant latch circuit structure, in which the latch unit has the ability to self-recover from soft errors and has a good reinforcement effect on single-particle flips occurring at a single node.

[0053] (3) The present invention discloses a self-recovering single-particle-resistant multi-bit flip latch circuit structure, which can achieve single-particle flip reinforcement of up to three nodes.

[0054] (4) The present invention discloses a self-recovering single-particle resistant multi-bit flip latch circuit structure, which adopts a combination of circuit design and layout design and has a good reinforcement effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Schematic diagram of a self-recovering single-particle resistant multi-bit flip latch circuit structure in an embodiment of the present invention;

[0056] Figure 2 is a circuit structure diagram of a clock-controlled inverter circuit in an embodiment of the present invention;

[0057] Figure 3 is a circuit structure diagram of a latch unit in an embodiment of the present invention;

[0058] Figure 4 is a circuit structure diagram of an output control unit in an embodiment of the present invention;

[0059] Figure 5 It is a circuit structure diagram of a SEU monitoring unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments disclosed in the present invention will be further described in detail below with reference to the accompanying drawings.

[0061] The present invention discloses a self-recovering single-particle multi-bit flip-resistant latch circuit structure, which mainly includes a clock-controlled inverter circuit, a latch unit, an output control unit, an SEU monitoring unit and an inverter circuit. The latch unit has the ability to self-recover from soft errors. The SEU monitoring unit is used to monitor whether a single-particle flip occurs in the latch unit. The output control unit is used to control the opening or closing of the outputs of two latch units according to the monitoring results of the SEU monitoring unit. The inverter circuit is used to invert the clock input signal CLK. The latch structure implemented by the present invention has a strong single-particle multi-bit flip-resistant characteristic.

[0062] like Figure 1As shown, in this embodiment, the self-recovering single-particle multi-bit flip-resistant latch circuit structure includes: a clock-controlled inverter circuit, a latch unit, an output control unit 107, an SEU monitoring unit 108, and an inverter circuit. The clock-controlled inverter circuit includes: a first clock-controlled inverter circuit 101, a second clock-controlled inverter circuit 102, a third clock-controlled inverter circuit 103, and a fourth clock-controlled inverter circuit 104; the latch unit includes: a first latch unit 105 and a second latch unit 106. The output terminal of the first clock-controlled inverter circuit 101 is connected to the input terminal in1 of the first latch unit 105 and the input terminal in1 of the SEU monitoring unit 108; the output terminal of the second clock-controlled inverter circuit 102 is connected to the input terminal in2 of the first latch unit 105 and the input terminal in3 of the SEU monitoring unit 108; the output terminal of the third clock-controlled inverter circuit 103 is connected to the input terminal in1 of the second latch unit 106; the output terminal of the fourth clock-controlled inverter circuit 104 is connected to the input terminal in2 of the second latch unit 106; the output terminal out1 of the first latch unit 105 is connected to the output control The input terminal in1 of the unit 107 and the input terminal in2 of the SEU monitoring unit 108; the output terminal out2 of the first latch unit 105 is connected to the input terminal in4 of the SEU monitoring unit 108; the output terminal out1 of the second latch unit 106 is connected to the input terminal in2 of the output control unit 107; the output terminal S1 and the output terminal S1N of the SEU monitoring unit 108 are respectively connected to the input terminal S1 and the input terminal S1N of the output control unit 107; the inverter circuit is used to provide the clock signal CK1 and the clock signal CK2 for the clock control inverter circuit, the latch unit and the SEU monitoring unit 108.

[0063] In this embodiment, the inverter circuit includes: a first inverter circuit 109 and a second inverter circuit 110. The first inverter circuit 109 and the second inverter circuit 110 are connected in series; the first inverter circuit 109 is used to provide a clock signal CK1 for the clock control inverter circuit, the latch unit and the SEU monitoring unit 108; the second inverter circuit 110 is used to provide a clock signal CK2 for the clock control inverter circuit, the latch unit and the SEU monitoring unit 108.

[0064] Preferably, the input end of the first inverter circuit 109 is connected to the input clock signal CLK; the first inverter circuit 109 outputs the clock signal CK1, and the second inverter circuit 110 outputs the clock signal CK2; wherein the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is the inverted signal of the clock signal CLK, and the clock signal CK2 is the inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the latch circuit.

[0065] In this embodiment, the clock-controlled inverter circuit is an inverter circuit controlled by a set of complementary clock signals. Figure 2 The clock-controlled inverter circuit includes: a PMOS tube P21, a PMOS tube P22, an NMOS tube N22 and an NMOS tube N21. The PMOS tube P21, the PMOS tube P22, the NMOS tube N22 and the NMOS tube N21 are connected in series in sequence; the gate of the PMOS tube P22 is connected to the clock signal CK2; the gate of the NMOS tube N22 is connected to the clock signal CK1; the gate of the PMOS tube P21 and the gate of the NMOS tube N21 are used as the input end of the clock-controlled inverter circuit for receiving the input signal.

[0066] In this embodiment, the latch unit is a DICE structure, which is composed of a pair of cross-coupled inverter structures and is mainly used to realize the function of storing data according to the timing signal. Figure 3 The latch unit includes an inverter D31, an inverter D32, an inverter D33 and an inverter D34. The inverter D31 includes a PMOS tube P31 and an NMOS tube N31 connected in series; the inverter D32 includes a PMOS tube P32, a PMOS tube P33, an NMOS tube N33 and an NMOS tube N32 connected in series in sequence; the inverter D33 includes a PMOS tube P34 and an NMOS tube N34 connected in series; the inverter D34 includes a PMOS tube P35, a PMOS tube P36, an NMOS tube N36 and an NMOS tube N35 connected in series in sequence. The input signal in1 is connected to the drain of the PMOS tube P33, the drain of the NMOS tube N33, the gate of the PMOS tube P34 and the gate of the NMOS tube N31; the input signal in2 is connected to the drain of the PMOS tube P36, the drain of the NMOS tube N36, the gate of the PMOS tube P31 and the gate of the NMOS tube N34; the output signal out1 is connected to the drain of the PMOS tube P34, the drain of the NMOS tube N34, the gate of the PMOS tube P35 and the gate of the NMOS tube N32; the output signal out2 is connected to the drain of the PMOS tube P31, the drain of the NMOS tube N31, the gate of the PMOS tube P32 and the gate of the NMOS tube N35; the gate of the PMOS tube P33 and the gate of the PMOS tube P36 are connected to the clock signal CK1; the gate of the NMOS tube N33 and the gate of the NMOS tube N36 are connected to the clock signal CK2.

[0067] Preferably, for the latch unit, when the clock signal CK1 is at a high level "1" and the clock signal CK2 is at a low level "0", the PMOS tube P33, the NMOS tube N33, the PMOS tube P36 and the NMOS tube N36 are all in a closed state. Since no cross-coupled inverter structure is formed, a single particle bombarding all single nodes inside the latch unit will only generate SET and will not generate SEU. When the clock signal CK1 is at a low level "0" and the clock signal CK2 is at a high level "1", the PMOS tube P33, the NMOS tube N33, the PMOS tube P36 and the NMOS tube N36 are all in an open state, and the data signal can be latched.

[0068] Preferably, for the latch unit, when the clock signal CK1 is at a low level "0" and the clock signal CK2 is at a high level "1", the storage unit will flip only when the data of the sensitive node pair is changed at the same time. When only the data of one sensitive node is changed, the latch unit will not flip. The dual-mode redundant structure of the internal node can realize self-recovery of soft errors, and has a good reinforcement effect on single-particle flips of a single node.

[0069] Preferably, for the latch unit, in combination with layout reinforcement technology, by increasing the distance between the sensitive node pair in1 and in2, or increasing the distance between the sensitive node pair out1 and out2, the probability of being simultaneously flipped is reduced, thereby achieving the purpose of enhancing the resistance to single particle upset.

[0070] In this embodiment, the output control unit has two data input terminals, two control signal input terminals and one data signal output terminal. Figure 4 As shown, the output control unit includes: an inverter D41, an inverter D42 and an inverter D43. Among them, the inverter D41 includes: a PMOS tube P41, a PMOS tube P42, an NMOS tube N42 and an NMOS tube N41 connected in series in sequence; the inverter D42 includes: a PMOS tube P43, a PMOS tube P44, an NMOS tube N44 and an NMOS tube N43 connected in series in sequence; the inverter D43 includes: a PMOS tube P45 and an NMOS tube N45 connected in series. The input signal in1 is connected to the gate of the PMOS tube P41 and the gate of the NMOS tube N41; the input signal in2 is connected to the gate of the PMOS tube P43 and the gate of the NMOS tube N43; the gate of the PMOS tube P42 and the gate of the NMOS tube N44 are connected to the input control signal S1; the gate of the NMOS tube N42 and the gate of the PMOS tube P44 are connected to the input control signal S1N; the output end of the inverter D41 and the output end of the inverter D42 are connected to the input end of the inverter D43; the output end of the inverter D43 serves as the output end out of the output control unit.

[0071] Preferably, for the output control unit, for the output control unit, when the input control signal S1 is a low level "0" and the input control signal S1N is a high level "1", the PMOS tube P42 and the NMOS tube N42 are in an on state, the PMOS tube P44 and the NMOS tube N44 are in an off state, and the state of the input signal in1 is transmitted to the output terminal out through the inverter D41 and the inverter D43; conversely, when the input control signal S1 is a high level "1" and the input control signal S1N is a low level "0", the PMOS tube P42 and the NMOS tube N42 are in an off state, the PMOS tube P44 and the NMOS tube N44 are in an on state, and the state of the input signal in2 is transmitted to the output terminal out through the inverter D42 and the inverter D43.

[0072] In this embodiment, the SEU monitoring unit has four data input terminals, one clock signal input terminal and two control signal output terminals. Figure 5As shown, the SEU monitoring unit includes: XOR gate XOR1, XOR gate XOR2, XOR gate XOR3, inverter D51, inverter D52, inverter D53, inverter D54, inverter D55, inverter D56 and OR gate OR1. Inverter D51 includes: PMOS tube P51, NMOS tube N51 and NMOS tube N53; the drain of PMOS tube P51, the drain of NMOS tube N51 and the drain of NMOS tube N53 serve as the output end of inverter D51; inverter D52 includes: PMOS tube P52, NMOS tube N52 and NMOS tube N54; the drain of PMOS tube P52, the drain of NMOS tube N52 and the drain of NMOS tube N54 The drain electrodes serve together as the output end of the inverter D52; the inverter D53 includes: a PMOS tube P55, a PMOS tube P56, an NMOS tube N56 and an NMOS tube N55 connected in series in sequence; the inverter D54 includes: a PMOS tube P57 and an NMOS tube N57 connected in series; the inverter D55 includes: a PMOS tube P58 and an NMOS tube N58 connected in series; the inverter D56 includes: a PMOS tube P59 and an NMOS tube N59 connected in series. Input signals in1 and in2 are connected to the two input terminals of XOR gate XOR1 respectively; the output terminal of XOR gate XOR1 is connected to the input terminal of inverter D51, that is, the gate of PMOS tube P51; input signals in3 and in4 are connected to the two input terminals of XOR gate XOR2 respectively; the output terminal of XOR gate XOR2 is connected to the input terminal of inverter D52, that is, the gate of PMOS tube P52; input signals in2 and in4 are connected to the two input terminals of XOR gate XOR3 respectively; the output terminal of inverter D51 is connected to the gate of PMOS tube P55 and the gate of NMOS tube N55; the output terminal of inverter D52 is connected to the gate of PMOS tube P56 and the gate of NMOS tube N56; the output terminal of inverter D53 is connected to the gate of XOR gate XOR2; the output terminal of inverter D54 is connected to the gate of PMOS tube P55 and the gate of NMOS tube N55; the output terminal of inverter D54 is connected to the gate of PMOS tube P56 and the gate of NMOS tube N56; the output terminal of inverter D54 is connected to the gate of inverter D54 ... inverter D54; the output terminal of inverter D54 is connected to the gate of inverter D54; the output terminal of inverter D54 is connected to the gate of inverter D54. The output end of the OR gate XOR3 is connected to the two input ends of the OR gate OR1 respectively; in addition, the output end of the inverter D53 is connected to the input end of the inverter D54; the output end of the inverter D54 is connected to the gate of the NMOS tube N51 and the gate of the NMOS tube N52; the output end of the OR gate OR1 is connected to the gate of the PMOS tube P58; the gate of the NMOS tube N53, the gate of the NMOS tube N54 and the gate of the NMOS tube N58 are used as the clock input end of the SEU monitoring unit, which is used to receive the clock signal CK1; the inverter D55 outputs the control signal S1, and the inverter D56 outputs the control signal S1N; the control signal S1 and the control signal S1N are complementary signals, that is, the signal S1N is the inverted signal of the signal S1.

[0073] Preferably, for the SEU monitoring unit, when the clock signal CK1 is at a high level "1", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in a conducting state, the internal nodes d, e and S2 of the SEU monitoring unit maintain a low level "0", the output control signal S1 maintains a low level "0", and the output control signal S1N maintains a high level "1", and the SEU monitoring unit is in a functionally closed state. The purpose is to shield the false detection when the state of the data input signal D changes normally.

[0074] Preferably, for the SEU monitoring unit, when the clock signal CK1 is at a low level “0”, the NMOS transistor N53 , the NMOS transistor N54 , and the NMOS transistor N58 are in a closed state, and the SEU monitoring unit function is turned on.

[0075] Preferably, for the SEU monitoring unit, its internal node changes and SEU detection principles are as follows:

[0076] XOR1 detects the sensitive nodes N1 and N2 of the first latch unit 105. When it is detected that the logic states of nodes N1 and N2 are the same in a very short time, it indicates that SEU occurs in node N1 or node N2. The internal node a of the SEU monitoring unit changes from a high level "1" to a low level "0", and the PMOS tube P51 becomes conductive. Since node S2 is initially at a low level "0", the NMOS transistor N51 is in a closed state, and node d changes from an initial low level "0" to a high level "1" and remains until the state of the internal node S2 or the clock signal CK1 changes. Similarly, XOR2 detects the sensitive nodes N3 and N4 of the first latch unit 105. When it is detected that the logic states of nodes N3 and N4 are the same in a very short time, it indicates that SEU occurs in node N3 or N4. The internal node b of the SEU monitoring unit changes from a high level "1" to a low level "0", and the PMOS tube P52 becomes conductive. Since the node S2 is initially at a low level “0”, the NMOS transistor N52 is in a closed state, and the node e changes from the initial low level “0” to a high level “1” and remains there until the state of the internal node S2 or the clock signal CK1 changes.

[0077] When nodes d and e are all at low level "0", it means that no sensitive nodes inside the first latch unit have changed, and all internal nodes of the SEU monitoring unit remain unchanged. The SEU monitoring unit output control signal S1 remains at low level "0", and the output control signal S1N remains at high level "1".

[0078] When the states of node d and node e are different (one is low level "0" and the other is high level "1"), it means that only one sensitive node in the first latch unit has changed its data, and the latch unit will not flip. The dual-mode redundant structure of the internal node can realize self-recovery of soft errors. In the inverter D53, there must be a PMOS tube and an NMOS tube (PMOS tube P55 and NMOS tube N56, or, PMOS tube P56 and NMOS tube N55) in the off state, and the inverter D53 is not turned on. The internal node f of the SEU monitoring unit maintains a high level "1" state, the OR gate OR1 outputs a high level "1", the PMOS tube P58 is in a closed state, the SEU monitoring unit output control signal S1 maintains a low level "0", and the output control signal S1N maintains a high level "1".

[0079] When both nodes d and e are at high level “1”, NMOS transistors N56 and NMOS transistors N55 are turned on, and node f changes from high level “1” to low level “0”. At this time, XOR gate XOR3 detects the sensitive node pair N2 and N4 of the first latch unit 105 .

[0080] When the logic states of the nodes N2 and N4 are different, it means that the data of the two sensitive nodes in the first latch unit 105 have changed, but the flip of the previous sensitive node has been restored, and the first latch unit 105 will not flip. At this time, the XOR gate XOR3 outputs a high level "1", the OR gate OR1 outputs a high level "1", the PMOS tube P58 is in the off state, the SEU monitoring unit output control signal S1 maintains a low level "0", and the output control signal S1N maintains a high level "1".

[0081] When the logic states of the nodes N2 and N4 are the same, it means that the data of the two sensitive nodes inside the first latch unit 105 have all changed, and a single-particle upset occurs in the first latch unit 105. At this time, the XOR gate XOR3 outputs a low level "0", the OR gate OR1 outputs a low level "0", the PMOS tube P58 is in the on state, the SEU monitoring unit output control signal S1 becomes a high level "1", and the output control signal S1N becomes a low level "0". Furthermore, through the output control unit, the data transmission channel is switched from the first latch unit 105 to the second latch unit 106, realizing the anti-single-particle multi-bit upset characteristic.

[0082] When nodes d and e are all high level "1", NMOS transistors N56 and NMOS transistors N55 are in the on state, node f changes from high level "1" to low level "0", and node S2 changes from low level "0" to high level "1". At this time, NMOS transistors N51 and NMOS transistors N52 are turned on, nodes d and e are reset to low level "0", node f changes to high level "1", node S2 changes to low level "0", NMOS transistors N51 and NMOS transistors N52 are turned off again, and node g changes to high level "1". At this point, the internal nodes d, e, f, g and S2 of the SEU monitoring unit are all reset, and SEU detection is restarted.

[0083] In this embodiment, the self-recovering single-particle upset resistant multi-bit latch circuit structure adopts a combination of circuit reinforcement technology and layout reinforcement technology to achieve single-particle upset resistant reinforcement of internal nodes.

[0084] In this embodiment, the self-recovering single-particle multi-bit upset resistant latch circuit structure can achieve single-particle upset resistance in all cases except the case where single-particle upset occurs in all the first latch unit and the second latch unit, and has a strong single-particle multi-bit upset resistance characteristic.

[0085] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0086] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.

Claims

1. A self-recovering single-event multi-bit flip latch circuit structure, characterized in that: include: A clock-controlled inverter circuit, a latch unit, an output control unit (107), an SEU monitoring unit (108) and an inverter circuit; wherein the clock-controlled inverter circuit comprises: a first clock-controlled inverter circuit (101), a second clock-controlled inverter circuit (102), a third clock-controlled inverter circuit (103) and a fourth clock-controlled inverter circuit (104); the latch unit comprises: a first latch unit (105) and a second latch unit (106); An output terminal of the first clock-controlled inverter circuit (101) is connected to an input terminal in1 of a first latch unit (105) and an input terminal in1 of an SEU monitoring unit (108); An output terminal of the second clock-controlled inverter circuit (102) is connected to an input terminal in2 of the first latch unit (105) and an input terminal in3 of the SEU monitoring unit (108); An output terminal of the third clock-controlled inverter circuit (103) is connected to an input terminal in1 of the second latch unit (106); The output terminal of the fourth clock-controlled inverter circuit (104) is connected to the input terminal in2 of the second latch unit (106); The output terminal out1 of the first latch unit (105) is connected to the input terminal in1 of the output control unit (107) and the input terminal in2 of the SEU monitoring unit (108); the output terminal out2 of the first latch unit (105) is connected to the input terminal in4 of the SEU monitoring unit (108); The output terminal out1 of the second latch unit (106) is connected to the input terminal in2 of the output control unit (107); The output terminal S1 and the output terminal S1N of the SEU monitoring unit (108) are respectively connected to the input terminal S1 and the input terminal S1N of the output control unit (107); The inverter circuit is used for providing a clock signal CK1 and a clock signal CK2 to a clock control inverter circuit, a latch unit and an SEU monitoring unit (108).

2. The self-recovering single-event multi-bit flip-proof latch circuit structure according to claim 1 is characterized in that: The inverter circuit comprises: a first inverter circuit (109) and a second inverter circuit (110); wherein the first inverter circuit (109) and the second inverter circuit (110) are connected in series; the first inverter circuit (109) is used to provide a clock signal CK1 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit (108); and the second inverter circuit (110) is used to provide a clock signal CK2 for the clock-controlled inverter circuit, the latch unit and the SEU monitoring unit (108).

3. The self-recovering single-event multi-bit flip-proof latch circuit structure according to claim 2 is characterized in that: The input end of the first inverter circuit (109) is connected to the input clock signal CLK; the first inverter circuit (109) outputs a clock signal CK1, and the second inverter circuit (110) outputs a clock signal CK2; wherein the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is an inverted signal of the clock signal CLK, and the clock signal CK2 is an inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the latch circuit.

4. The self-recovering single-event multi-bit flip-proof latch circuit structure according to claim 1 is characterized in that: The clock-controlled inverter circuit is an inverter circuit controlled by a set of complementary clock signals, including: a PMOS tube P21, a PMOS tube P22, an NMOS tube N22 and an NMOS tube N21; The PMOS tube P21, the PMOS tube P22, the NMOS tube N22 and the NMOS tube N21 are connected in series in sequence; The gate of the PMOS tube P22 is connected to the clock signal CK2; The gate of the NMOS tube N22 is connected to the clock signal CK1; The gate of the PMOS transistor P21 and the gate of the NMOS transistor N21 serve together as the input terminal of the clock control inverter circuit for receiving an input signal.

5. The self-recovering single-event multi-bit flip-proof latch circuit structure according to claim 1 is characterized in that: The latch unit is a DICE structure, including: an inverter D31, an inverter D32, an inverter D33 and an inverter D34; wherein the inverter D31 includes: a PMOS tube P31 and an NMOS tube N31 connected in series; the inverter D32 includes: a PMOS tube P32, a PMOS tube P33, an NMOS tube N33 and an NMOS tube N32 connected in series in sequence; the inverter D33 includes: a PMOS tube P34 and an NMOS tube N34 connected in series; the inverter D34 includes: a PMOS tube P35, a PMOS tube P36, an NMOS tube N36 and an NMOS tube N35 connected in series in sequence; The input signal in1 is connected to the drain of the PMOS tube P33, the drain of the NMOS tube N33, the gate of the PMOS tube P34 and the gate of the NMOS tube N31; The input signal in2 is connected to the drain of the PMOS tube P36, the drain of the NMOS tube N36, the gate of the PMOS tube P31 and the gate of the NMOS tube N34; The output signal out1 is connected to the drain of the PMOS tube P34, the drain of the NMOS tube N34, the gate of the PMOS tube P35 and the gate of the NMOS tube N32; The output signal out2 is connected to the drain of the PMOS tube P31, the drain of the NMOS tube N31, the gate of the PMOS tube P32 and the gate of the NMOS tube N35; The gate of the PMOS tube P33 and the gate of the PMOS tube P36 are connected to the clock signal CK1; The gate of the NMOS transistor N33 and the gate of the NMOS transistor N36 are connected to the clock signal CK2.

6. The self-recovering single-event multi-bit flip-proof latch circuit structure according to claim 1 is characterized in that: The output control unit includes an inverter D41, an inverter D42 and an inverter D43; wherein the inverter D41 includes a PMOS tube P41, a PMOS tube P42, an NMOS tube N42 and an NMOS tube N41 connected in series in sequence; the inverter D42 includes a PMOS tube P43, a PMOS tube P44, an NMOS tube N44 and an NMOS tube N43 connected in series in sequence; the inverter D43 includes a PMOS tube P45 and an NMOS tube N45 connected in series; The input signal in1 is connected to the gate of the PMOS tube P41 and the gate of the NMOS tube N41; The input signal in2 is connected to the gate of the PMOS tube P43 and the gate of the NMOS tube N43; The gate of the PMOS transistor P42 and the gate of the NMOS transistor N44 are connected to the input control signal S1; The gate of the NMOS transistor N42 and the gate of the PMOS transistor P44 are connected to the input control signal S1N; The output end of the inverter D41 and the output end of the inverter D42 are commonly connected to the input end of the inverter D43; The output terminal of the inverter D43 serves as the output terminal out of the output control unit.

7. The self-recovering single-event multi-bit flip-proof latch circuit structure according to claim 6 is characterized in that: For the output control unit, when the input control signal S1 is at a low level "0" and the input control signal S1N is at a high level "1", the PMOS tube P42 and the NMOS tube N42 are in a conducting state, the PMOS tube P44 and the NMOS tube N44 are in a closed state, and the state of the input signal in1 is transmitted to the output terminal out through the inverter D41 and the inverter D43; conversely, when the input control signal S1 is at a high level "1" and the input control signal S1N is at a low level "0", the PMOS tube P42 and the NMOS tube N42 are in a closed state, the PMOS tube P44 and the NMOS tube N44 are in a conducting state, and the state of the input signal in2 is transmitted to the output terminal out through the inverter D42 and the inverter D43.

8. The self-recovering single-event-resistant multi-bit flip latch circuit structure according to claim 1, characterized in that: The SEU monitoring unit includes: an XOR gate XOR1, an XOR gate XOR2, an XOR gate XOR3, an inverter D51, an inverter D52, an inverter D53, an inverter D54, an inverter D55, an inverter D56 and an OR gate OR1; wherein the inverter D51 includes: a PMOS tube P51, an NMOS tube N51 and an NMOS tube N53; the drain of the PMOS tube P51, the drain of the NMOS tube N51 and the drain of the NMOS tube N53 serve as the output end of the inverter D51; the inverter D52 includes: a PMOS tube P52, an NMOS tube N52 and an NMOS tube N53; MOS tube N54; the drain of PMOS tube P52, the drain of NMOS tube N52 and the drain of NMOS tube N54 are used as the output end of inverter D52; inverter D53 includes: PMOS tube P55, PMOS tube P56, NMOS tube N56 and NMOS tube N55 connected in series in sequence; inverter D54 includes: PMOS tube P57 and NMOS tube N57 connected in series; inverter D55 includes: PMOS tube P58 and NMOS tube N58 connected in series; inverter D56 includes: PMOS tube P59 and NMOS tube N59 connected in series; The input signals in1 and in2 are connected to the two input terminals of the XOR gate XOR1 respectively; the output terminal of the XOR gate XOR1 is connected to the input terminal of the inverter D51, that is, the gate of the PMOS tube P51; The input signals in3 and in4 are connected to the two input terminals of the XOR gate XOR2 respectively; the output terminal of the XOR gate XOR2 is connected to the input terminal of the inverter D52, that is, the gate of the PMOS tube P52; Input signals in2 and in4 are connected to the two input terminals of XOR gate XOR3 respectively; The output terminal of the inverter D51 is connected to the gate of the PMOS tube P55 and the gate of the NMOS tube N55; The output terminal of the inverter D52 is connected to the gate of the PMOS tube P56 and the gate of the NMOS tube N56; The output end of the inverter D53 and the output end of the XOR gate XOR3 are respectively connected to the two input ends of the OR gate OR1; in addition, the output end of the inverter D53 is connected to the input end of the inverter D54; The output terminal of the inverter D54 is connected to the gate of the NMOS tube N51 and the gate of the NMOS tube N52; The output terminal of the OR gate OR1 is connected to the gate of the PMOS tube P58; The gate of the NMOS tube N53, the gate of the NMOS tube N54 and the gate of the NMOS tube N58 are used as the clock input terminal of the SEU monitoring unit, and are used to receive the clock signal CK1; The inverter D55 outputs a control signal S1 , and the inverter D56 outputs a control signal S1N; wherein the control signal S1 and the control signal S1N are complementary signals, that is, the signal S1N is an inverted signal of the signal S1 .

9. The self-recovering single-event-resistant multi-bit flip latch circuit structure according to claim 8, characterized in that: For the SEU monitoring unit, when the clock signal CK1 is at a high level "1", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in the on state, the output control signal S1 maintains a low level "0", and the output control signal S1N maintains a high level "1". At this time, the SEU monitoring unit is in a functional off state; when the clock signal CK1 is at a low level "0", the NMOS transistor N53, the NMOS transistor N54 and the NMOS transistor N58 are in a off state, and the SEU monitoring unit function is turned on.

10. The self-recovering single-event multi-bit flip-proof latch circuit structure according to claim 1, characterized in that: The latch adopts a combination of circuit reinforcement technology and layout reinforcement technology to achieve single-particle upset resistance of internal nodes.

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