Solid-state imaging device having high charge transport capability

Abstract

A solid-state imaging device comprising an array of pixels wherein each pixel of the pixel array (1201) comprises: a photodiode for converting electromagnetic radiation into an electric charge; a transfer gate device for transferring the charge from the photodiode to a floating diffusion node, where the transfer gate device comprises an embedded portion (102) embedded in the pixel array (1201), a first wall on a side of the embedded portion (102) facing the floating diffusion node and a second wall on a side of the embedded portion (102) not facing the floating diffusion node have different shapes.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device, and more particularly to a solid-state imaging device including a pixel structure having a high charge transfer capability. Background Art

[0002] An important issue associated with solid-state imaging devices is to increase the full well capacity, where the full well capacity is the upper limit of the capacity for storing charge generated by converting the detected electromagnetic radiation into photocharge. Since the charge exceeding the full well capacity cannot be detected as a signal, a small full well capacity results in a low dynamic range (DR) and a low signal-to-noise ratio (SNR) under a large amount of electromagnetic radiation. On the contrary, a large full well capacity helps to reproduce a high-definition image due to the detected electromagnetic radiation, thereby achieving a true restoration of the image. Therefore, a higher full well capacity is always desired.

[0003] Another important issue associated with solid-state imaging devices is to reduce the pixel size. However, this also results in a smaller full well capacity of the solid-state imaging device. Therefore, it is designed to enlarge the photodiode in a direction perpendicular to the surface of the solid-state imaging device (i.e., in the depth direction) to increase the full well capacity while reducing the pixel size. In order to achieve a high charge transfer capability to transfer all the charges stored in such a deep photodiode, a vertical transfer gate (VTG) has been proposed, which has a structure extending in the depth direction rather than a planar structure set on the surface of the solid-state imaging device.

[0004] Since the charge transfer capability of a vertical transfer element (VTG) is proportional to the bottom area of ​​the VTG, it is desirable to increase the bottom area of ​​the VTG. In order to increase the bottom area of ​​the VTG, a cup-shaped VTG is proposed (US009041071B2). However, the cup-shaped VTG is very large and may cause defects, and may also cause problems in subsequent manufacturing processes due to the cup-shaped steps, such as source / drain sidewall spacer formation and back end of line (BEOL).

[0005] To this end, a technology has been designed to improve the charge transfer capability of the VTG by providing a shallow photodiode adjacent to the VTG and transferring charge from the sidewalls of the VTG while reducing the pixel size by reducing the bottom area of ​​the VTG (US2020 / 0344333A1). However, the pixel size reduction is limited by the need to provide a shallow photodiode next to the VTG. In addition, due to the small bottom area of ​​the VTG, the charge from the deep part of the photodiode cannot be fully read out.

[0006] In addition, increasing the bottom area of ​​the VTG will cause another problem, namely "blooming". Blooming is a phenomenon in which multiple pixel defects appear on the reproduced image, because the photodiode of the pixel illuminated by strong light cannot store charge, so the excess charge diffuses to the surrounding pixels. In order to prevent blooming, an anti-blooming path is provided through which the excess charge is discharged from the photodiode to the floating diffusion node (US11,195,873B2). However, since the VTG has two columnar electrodes to configure the anti-blooming path, the pixel size cannot be reduced.

[0007] Therefore, given the limited space in solid-state imaging devices, there is an urgent need to increase the full well capacity as much as possible. Summary of the invention

[0008] An object of the present invention is to solve the above-mentioned problems in the field of solid-state imaging devices.

[0009] According to a first aspect of the present invention, there is provided a solid-state imaging device comprising a pixel array, wherein each pixel of the pixel array comprises:

[0010] photodiodes for converting electromagnetic radiation into electrical charge;

[0011] a transfer gate device for transferring the charge from the photodiode to a floating diffusion node,

[0012] The transmission gate device includes an embedded portion embedded in the pixel array, and a first wall of the embedded portion facing the floating diffusion node and a second wall of the embedded portion not facing the floating diffusion node have different shapes.

[0013] According to a first possible implementation of the first aspect of the present invention, the embedded portion includes a surface of the pixel array and a bottom surface between the photodiodes, each pixel includes a P-type doped region between the bottom surface and the photodiode, and also includes an N-type doped region between the P-type doped region and the photodiode.

[0014] According to a second possible implementation manner of the first aspect of the present invention, the P-type doping region further extends to one side of the transmission gate device.

[0015] According to a third possible implementation manner of the first aspect of the present invention, the embedded portion includes a surface of the pixel array and a bottom surface between the photodiodes, and each pixel includes a P-type doped region between the bottom surface and the photodiode.

[0016] According to a fourth possible implementation manner of the first aspect of the present invention, the P-type doping region further extends to one side of the transmission gate device.

[0017] According to a fifth possible implementation manner of the first aspect of the present invention, the P-type doping region and the N-type doping region are self-aligned.

[0018] According to a sixth possible implementation manner of the first aspect of the present invention, the P-type well between the embedded portion and the pixel device is deeper than the P-type well between the embedded portion and the floating diffusion node.

[0019] According to a seventh possible implementation manner of the first aspect of the present invention, a cross section of the embedded portion parallel to the surface of the pixel array is a combination of a polygon or a curve.

[0020] According to an eighth possible implementation of the first aspect of the present invention, the transmission gate device also includes a protrusion formed on the surface of the pixel array, and in the cross-section of the embedded portion parallel to the surface of the pixel array, part or all of the polygonal edges or the multiple curves are located outside the area of ​​the protrusion.

[0021] According to a ninth possible implementation manner of the first aspect of the present invention, the pixel array includes a pixel unit, the pixel unit includes four pixels coupled to the same floating diffusion node, and the embedded portion included in the pixel unit is arranged in a ring shape.

[0022] According to a tenth possible implementation manner of the first aspect of the present invention, the embedded portion included in the pixel unit is arranged to be 90 degrees rotationally symmetric or 180 degrees rotationally symmetric with respect to the same floating diffusion node.

[0023] According to an eleventh possible implementation manner of the first aspect of the present invention, in a cross-section of the embedded portion parallel to the surface of the pixel array, the first wall has a first arc including a first center and a first radius, the second wall has a second arc including a second center and a second radius, and wherein the first center and the second center are both between the floating diffusion node and the transmission gate device, and the first radius is smaller than the second radius.

[0024] According to a twelfth possible implementation manner of the first aspect of the present invention, the transmission gate device also includes a protrusion formed on the surface of the pixel array; the first wall and the second wall are arranged opposite to each other, and the embedded portion also includes a third wall and a fourth wall, and the third wall and the fourth wall are respectively connected to the first wall and the second wall; in a cross-section of the embedded portion parallel to the surface of the pixel array, part or all of one or more of the first wall, the second wall, the third wall and the fourth wall are located outside the area of ​​the protrusion.

[0025] According to a thirteenth possible implementation manner of the first aspect of the present invention, a cross section of the embedded portion perpendicular to the surface of the pixel array is any one of the following shapes:

[0026] square;

[0027] a trapezoidal shape narrowing toward the bottom surface;

[0028] a trapezoidal shape that widens toward the bottom surface;

[0029] Parallelogram;

[0030] is generally rectangular in shape, with rounded corners on one side of said bottom surface;

[0031] The pixel array is generally rectangular in shape and has rounded corners on one side of the surface.

[0032] According to a fourteenth possible implementation manner of the first aspect of the present invention, part of the overflow path is formed between the bottom surface of the embedded portion and the photodiode, or is formed below the bottom surface of the embedded portion inside the photodiode.

[0033] According to a fifteenth possible implementation manner of the first aspect of the present invention, the overflow path is a path for transferring photoelectric charges exceeding a full well capacity of the photodiode to the floating diffusion node.

[0034] According to a second aspect of the present invention, there is provided an electronic device, comprising the solid-state imaging device according to the first aspect or any one of the first to twelfth possible implementations of the first aspect.

[0035] [Effects of the invention]

[0036] With the solid-state imaging device of the present invention, it is possible to increase the full well capacity while reducing the pixel size.

[0037] Furthermore, according to the solid-state imaging device of the present invention, there is no problem of residual image in the readout stage, and a high pixel charge transfer capability from the photoconversion region to the floating diffusion node can be achieved.

[0038] Furthermore, according to the solid-state imaging device of the present invention, blooming in the pixel charge integration stage can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments or background technologies of the present application, the drawings used to describe the embodiments or background technologies of the present application are introduced below. It is obvious that the drawings in the following description only show some embodiments of the present application, and ordinary technicians in this field can still obtain other drawings based on these drawings without creative work.

[0040] Figure 1 FIG. 4 is a top view of a pixel unit including four photodiodes formed on a semiconductor substrate according to a first embodiment of the present invention.

[0041] Figure 2A A top view and a cross-sectional view of a single pixel formed on a semiconductor substrate according to the related art are shown.

[0042] Figure 2B A top view and a cross-sectional view of a single pixel formed on a semiconductor substrate according to a first embodiment of the present invention are shown.

[0043] Figure 3 Shown along Figure 1 Cross-sectional view along line A-A'.

[0044] Figure 4 1 and 2 show top views of various shapes of a VTG according to a second embodiment of the present invention.

[0045] Figure 5 1 and 2 show top views of various shapes of a VTG according to a third embodiment of the present invention.

[0046] Figure 6 1 and 2 show top views of various arrangements of a VTG according to a fourth embodiment of the present invention.

[0047] Figure 7 Cross-sectional views showing various shapes of a VTG according to a fifth embodiment of the present invention.

[0048] Figure 8 Cross-sectional views showing various shapes of a VTG according to a sixth embodiment of the present invention.

[0049] Fig. 9 Cross-sectional views showing various shapes of PDs according to a seventh embodiment of the present invention.

[0050] Fig.10 Various circuits of a shared pixel device according to an eighth embodiment of the present invention are shown.

[0051] Fig.11 Various circuits of a pixel device according to a ninth embodiment of the present invention are shown.

[0052] Fig.12 An exemplary pixel array to which an embodiment of the present invention is applied is shown.

[0053] Fig.13 A cross-sectional view showing a portion of an exemplary pixel array to which an embodiment of the present invention is applied.

[0054] Fig.14A schematic structural diagram showing an exemplary solid-state imaging device to which an embodiment of the present invention is applied.

[0055] Fig.15 A schematic block diagram of an exemplary electronic device to which an embodiment of the present invention is applied is shown.

[0056] Fig.16 Exemplary technical fields to which embodiments of the present invention are applied are shown.

[0057] Fig.17 An example in which the embodiment of the present invention is applied to a vehicle is shown. DETAILED DESCRIPTION

[0058] The terms used in this application are only used to describe specific possible implementations, rather than to limit this application. The terms "one", "said" and "said" used in this application, including the attached claims, for singular forms are also intended to include plural forms, unless otherwise explicitly stated. It should also be understood that the term "and / or" used in this article refers to any or all possible combinations of one or more listed related items. It should also be understood that the term "including" used in this article specifies the presence of features, data, information, entities, steps, operations, equipment, units, elements and / or components, without excluding the presence or addition of one or more other features, data, information, entities, steps, operations, equipment, units, elements, components and / or combinations thereof.

[0059] It should be understood that, although the terms "first", "second", etc. may be used to describe various devices or units in the embodiments of the present application, these devices or units should not be limited by the terms. These terms are only used to distinguish devices or units. For example, without departing from the scope of the embodiments of the present application, the first device and the first unit may be referred to as the second device and the second unit, respectively. Similarly, the second device and the second unit may be referred to as the first device and the first unit, respectively.

[0060] It should be noted that the order of the steps in this application can be freely arranged, that is, this application does not limit the order of the steps.

[0061] The technical solutions in the embodiments of the present application are described below in conjunction with the accompanying drawings.

[0062] In the following description and drawings, electrons or holes are the main carriers in the region represented by N or P, respectively. The region represented by N or P is called an N-type doped region or a P-type doped region, or simply referred to as N-type or P-type, or an N-region or a P-region. For an N or P region marked with "+", that is, a region represented by N+ or P+, it means that the doping concentration of the region is higher than that of a region not represented by "+". For an N or P region marked with "-", that is, a region represented by N- or P-, it means that the doping concentration of the region is lower than that of a region not represented by "-". Although the following discussion describes the case where the signal charge includes electrons and all transistors are N-type transistors, in other embodiments, the signal charge may include holes and some transistors may be P-type transistors.

[0063] Figure 1 FIG. 1 shows a top view of a pixel unit 100 including four photodiodes PD1 to PD4 formed on a semiconductor substrate according to a first embodiment of the present invention. Figure 1 In the embodiment, four photodiodes PD1 to PD4 share a pixel device. Photodiodes PD1 to PD4 are separated by deep trench isolation (DTI) and / or doping isolation. Pixel devices are separated by shallow trench isolation (STI) and / or doping isolation. Pixel devices include a vertical transfer gate (VTG) device, a floating diffusion node (FD), a reset (RST) device, a dual conversion gain (DCG) device, an amplifier (AMP) device, and a selector (SEL). VTG, RST, DCG, AMP, and SEL can be implemented by complementary metal oxide semiconductor (CMOS) transistors.

[0064] Each of the photodiodes PD1 to PD4 is connected to AVSS1, which is grounded or a negative voltage in the range of –5.0V to 0V. Each of the photodiodes PD1 to PD4 detects electromagnetic radiation and converts the detected electromagnetic radiation into electrons. As long as the VTG is not in a conductive state, the electrons remain between each of the photodiodes PD1 to PD4 and the corresponding VTG. When the VTG receives a transmission signal from a control circuit (not shown) and is in a conductive state (ON), the VTG transmits the electrons to the FD. The FD receives the electrons and stores the charge generated by the electrons.

[0065] FD is connected to the gate of an amplifier (AMP) device, and the change in the charge stored in FD is amplified by the AMP. SEL receives a row selection signal from a control circuit, then becomes a conductive state (ON), and outputs a voltage corresponding to the charge stored in FD at Vout. The reset (RST) device selectively resets the charge stored on PD and / or FD. In some embodiments, the signal is acquired by performing correlated double sampling (CDS). CDS uses the difference between the reset level and the signal level to reduce fixed pattern noise and reset noise. In some embodiments, the charge-to-voltage conversion is performed by an AMP with a gain equal to or less than 1 using a source follower operation. In some embodiments, the charge-to-voltage conversion is performed by an AMP with a gain greater than 1, where a differential amplification mode can be adopted.

[0066] In some embodiments, Vout can be greater than 2, and at least two rows can be read out simultaneously.

[0067] The dual conversion gain (DCG) device switches between two conversion gains. When the DCG is in a conductive state (ON), the FD of the pixel unit 100 is connected to the FD of another pixel unit to provide a low conversion gain (LCG) mode suitable for a high dynamic range (HDR). When the DCG is in a non-conductive state (OFF), the FD of the pixel unit 100 is not connected to the FD of another pixel unit to provide a high conversion gain (HCG) mode suitable for a high signal-to-noise ratio.

[0068] Supply voltages AVDD1 and AVDD2 provide power to the pixel device. AVDD1 and AVDD2 may have the same or different potentials.

[0069] exist Figure 1 In the example of FIG. 1 , the pixel unit 100 includes 4 photodiodes PD1 to PD4 and 4 corresponding VTGs, but the number of photodiodes and VTGs included in one pixel unit 100 may be more or less than 4. A pixel array may also be formed by arranging a plurality of pixel units 100 in rows and columns. The solid-state imaging device according to the present invention includes such a pixel array.

[0070] The VTG of each of the photodiodes PD1 to PD4 has a protruding portion 101 represented by a solid hexagon and an embedded portion 102 represented by a dotted line. The protruding portion 101 is a portion protruding from the surface of the pixel array (i.e., the surface of the semiconductor substrate forming the pixel unit 100), and the embedded portion 102 is a portion embedded in the pixel array (i.e., the inside of the semiconductor substrate forming the pixel unit 100).

[0071] From a top view, the cross-section of the embedded portion 102 is a shape surrounded by two arcs and two straight lines. This shape makes the bottom area of ​​the embedded portion 102 of the VTG larger than that of a traditional circle, rectangle, square, etc. The two arcs are parts of different circles, and the radius of each circle is different. The center of each circle may be the same or different and is located between the FD and the embedded portion 102. Alternatively, the centers of the arcs forming the cross-section of the embedded portion 102 corresponding to different PDs may be different or the same. This configuration of the embedded portion 102 increases the bottom area of ​​the VTG, thereby improving the charge transfer capability of the VTG, thereby achieving a high full well capacity.

[0072] The four embedded parts 102 included in the pixel unit 100 may be arranged in an annular space. For example, the four embedded parts 102 may be arranged on a circumference, and the center of the circle may be located at or near the FD, or between the FD and the embedded parts 102 .

[0073] The shape of the embedded portion 102 is not limited to Figure 1 For convenience, Figure 1 The electrode (black square) of the VTG shown is called the center of the embedded portion 102, and the side close to the adjacent PD is called one end of the embedded portion 102. At this time, the closer the point on the arc is to the center of the embedded portion 102, the greater the distance between the surface of the embedded portion 102 and the FD, and the closer the point on the arc is to the end of the embedded portion 102, the smaller the distance between the surface of the embedded portion 102 and the FD. In this way, the distance between the embedded portion 102 and the FD is as far as possible.

[0074] Such a shape and arrangement of the embedded portion 102 increases the distance between the embedded portion 102 of the VTG and the FD, thereby reducing the electric field strength between the VTG and the FD. Therefore, the leakage current from the VTG to the FD, which causes severe fixed pattern noise, can be reduced.

[0075] Figure 2AA top view (above) and a cross-sectional view (below) of a single pixel formed on a semiconductor substrate according to the related art are shown. As shown in the cross-sectional view (below), both sides of the N-type PD (N-PD) have deep trench isolation (DTI) to separate the N-PD from the adjacent N-PD. On the left side of the DTI, there is a shallow trench isolation (STI) to separate the photodiode region from the adjacent pixel device. In some embodiments, the separation between devices can be achieved by STI or doping isolation.

[0076] In some embodiments, some of the reset (RST) device, the dual conversion (DCG) device, the amplifier (AMP) device, or the selector (SEL) device (see also Figure 1 ) can be formed on a separate wafer that is coupled to the wafer on which PD, VTG and FD are formed.

[0077] Figure 2A The illustrated embodiment shows a partial deep trench isolation (DTI), but in other embodiments, a complete DTI may be formed, with the depth of the DTI being equal to or greater than the thickness of the photoconverting material.

[0078] FD is shown as an N+ region. Figure 2A The cross-section of the VTG is circular (as shown in the top view (above)), and horizontal T-shaped (as shown in the cross-sectional view (below)), formed deep into the N-PD, with an N-region on the N-PD on the left side of the VTG. The charges stored in the N-PD are guided to the N-region (path 201') and carried to the FD through the VTG side (path 201). Path 201' is a side view of path 201. Path 201 or path 201' is used as an anti-blooming path to discharge excess charge from the N-PD to the FD to prevent blooming. As Figure 2A As shown, path 201 is directed to FD while bypassing VTG, thus increasing the length of the path and achieving only low anti-blooming capability.

[0079] Figure 2B 1 shows a top view (top) and a cross-sectional view (bottom) of a single pixel formed on a semiconductor substrate according to a first embodiment of the present invention. As shown in the top view (top), Figure 2B The VTG has a similar Figure 1 The cross section of the VTG is shown in FIG. 1 , and as shown in the cross section (below), the VTG has a shallower embedded portion (corresponding to Figure 1 102) instead of Figure 2A VTG. Figure 2A Compared with VTG, Figure 2B The VTG has a larger cross-sectional area in the top view and a shallower cross-sectional area in the side view. The N-region is disposed within the N-PD and between the VTG and the N-PD, rather than being disposed right next to the VTG. The charge stored in the N-PD is directed to the N-region (path 202') and is carried to the FD under the VTG (the dashed portion of path 202), and the FD is represented as N+. Path 202' is a side view of path 202. Path 202 or 202' is used as an anti-blooming path to discharge excess charge from the N-PD to the FD to prevent blooming. As Figure 2B As shown, path 202 is transmitted to FD under VTG, thereby providing Figure 2A The path 201 in the image has a shorter distance and higher anti-blooming capability.

[0080] Figure 2B The N-region and P-region provided between the VTG and the N-PD as shown can be formed using a self-aligned doping process. This process is very robust and can achieve high yields.

[0081] Figure 3 Shown along Figure 1 Cross-sectional view along line A-A'. Figure 3 In addition to Figure 2B The area of ​​the pixel device outside. Figure 3 , the maximum width W of the embedded portion of the VTG is less than twice the height H of the pixel devices on the surface of the pixel array except the VTG. That is, W<2H. This relationship can avoid the problem in the related art, that is, because the VTG is too wide, a slit is formed in the VTG during the manufacturing process of the VTG. Figure 3 The VTG shown is robust because it has no slits.

[0082] Figure 4 1 and 2 show top views of various shapes of a VTG according to a second embodiment of the present invention. Figure 4 (A) shows a similar Figure 1 The hexagonal protrusion 101 has an octagonal embedded portion 102 in a “[” shape. Figure 4 (B) shows the pentagonal protrusion 101 and the L-shaped embedding portion 102 . Figure 4 (C) shows the Figure 1 A similar hexagonal protrusion 101 and an inset 102 having three interconnected circles. Figure 4 (D) shows a similar Figure 1A hexagonal protrusion 101 and an embedded portion 102 having three interconnected ellipses. Each of the shapes shown in (A) to (D) can be determined to increase the bottom area of ​​the embedded portion 102 while spatially separating the embedded portion 102 and the FD as much as possible. By increasing the bottom area of ​​the VTG, a high pixel charge transfer capability can be achieved. The shape and cross-sectional area of ​​the cross section of the protrusion 101, the shape and cross-sectional area of ​​the cross section of the embedded portion 102, the relative position of the protrusion 101 and the embedded portion 102, the relative position of the protrusion 101 and the PD, the relative position of the embedded portion 102 and the PD, etc. can be changed as needed. For example, the cross sections of the protrusion 101 and the embedded portion 102 may include shapes different from Figure 4 The shape of the polygons or curves shown, or a combination of straight lines and curves.

[0083] Figure 5 FIG. 2 shows a top view of various shapes of a VTG according to a third embodiment of the present invention. Figure 5 In (A), the end of the embedded portion 102 on the adjacent PD side is located outside the end of the protruding portion 101. Figure 5 In (B), the end of the embedded portion 102 opposite to the FD is outside the end of the protruding portion 101. Figure 5 In (C), the end of the embedded portion 102 on the FD side is located outside the end of the protruding portion 101. These shapes make it possible to reduce the pixel size by reducing the protruding portion 101 without reducing the VTG embedded portion 102. In addition, reducing the protruding portion 101 can improve the degree of freedom of layout.

[0084] Figure 6 A top view of various arrangements of a VTG according to a fourth embodiment of the present invention is shown. Figure 6 In (A), the distance between the embedded parts 102 of the VTGs of PD1 and PD2 or the distance between the embedded parts 102 of the VTGs of PD3 and PD4 is smaller than the distance between the embedded parts 102 of the VTGs of PD1 and PD3 or the distance between the embedded parts 102 of the VTGs of PD2 and PD4. Figure 6 The protrusion 101 and / or the embedded portion 102 in (A) are arranged to be 180 degrees rotationally symmetrical with respect to FD. In other words, Figure 6 The protruding portion 101 and / or the embedded portion 102 in (A) are arranged to be linearly symmetrical with respect to a vertical line or a horizontal line passing through FD.

[0085] exist Figure 6 In (B), the distances between the embedded portions 102 of the VTGs of adjacent PDs remain equal, and each embedded portion 102 is offset relative to the corresponding protruding portion 101 . Figure 6 The protruding portion 101 and / or the embedded portion 102 in (B) are arranged to be rotationally symmetrical at 90 degrees with respect to the FD.

[0086] like Figure 6 As shown in (A) and (B) of FIG. 1 , the asymmetric arrangement of the VTG increases the freedom of the circuit layout of the pixel array. Other asymmetric arrangements of the VTG may be applied as needed.

[0087] exist Figures 4 to 6 In the example of , the pixel unit includes 4 VTGs, corresponding to 4 photodiodes PD1 to PD4, but the number of photodiodes and VTGs included in a pixel unit may be greater than or less than 4.

[0088] Figure 7 2 shows cross-sectional views of various shapes of a VTG according to a fifth embodiment of the present invention. Figure 7 In the example shown in (A), the P-well on the left side of the photodiode N-PD is deeper than the P-well on the right side of the N-PD, that is, the P-well on the FD side (indicated by N+). With this arrangement, the charge stored in the N-PD is efficiently transferred from the bottom of the VTG through the N- region to the inside of the VTG and to the FD, thereby improving the residual image.

[0089] exist Figure 7 In the example shown in (B), the embedded portion of VTG is shallow, and the P-region and N-region between VTG and N-PD and the P-well on the left side of N-PD do not enter the inside of N-PD. Therefore, the P-region under VTG does not directly contact the N-PD, thereby preventing dark current.

[0090] exist Figure 7 In the example shown in (C), the N-region between VTG and N-PD is omitted (see Figure 7 (B)), thereby reducing the manufacturing cost. Since the N-region between the embedded portion of the VTG and the FD is in contact with the N-PD, an anti-blooming path is formed from the N-PD through the N-region to the FD.

[0091] exist Figure 7 In the example shown in (D), the N-region between VTG and N-PD is omitted (see Figure 7 (B)), and the N-region between VTG and FD is also omitted (see Figure 7 (C)). Since the two N-regions are omitted, the manufacturing cost is further reduced.

[0092] exist Figure 7 In the example shown in (E), the protrusion of VTG is further omitted (see Figure 7 (D)). Since the protrusion of the VTG cannot improve the charge transfer capability of the VTG, removing the protrusion can secure space and give circuit layout flexibility while maintaining the performance of the VTG.

[0093] exist Figure 7In the example shown in (F), the P well around the DTI is omitted (see Figure 7 (C)). If the dark current is sufficiently suppressed in some way, such as by a background film (which is a thin film with a negative fixed charge), the manufacturing cost can be further reduced by omitting the P-well. For example, the background film can include SiO2, SiN, SiON, HfO2, Al2O3, AlN, ZrO2, Ta2O5, TiO2, La2O3, Pr2O3, CeO2, Nd2O3, Pm2O3, Sm2O3, Eu2O3, Gd2O3, Tb2O3, Dy2O3, Ho2O3, Er2O3, Tm2O3, Yb2O3, Lu2O3, Y2O3, or a combination thereof.

[0094] Figure 8 sectional views of various shapes of VTG according to the sixth embodiment of the present invention are shown. Figure 8 In (A), the cross section of the embedded portion of the VTG is a trapezoid or a cone, wherein the cross section narrows toward the bottom. Figure 8 In (B), the cross section of the embedded portion of the VTG is a trapezoid or an inverted cone, wherein the cross section widens toward the bottom. Figure 8 In (C), the cross section of the embedded portion of the VTG is a parallelogram. Figure 8 In (D), the cross section of the embedded portion of the VTG is rectangular with rounded corners on the N-PD side. Figure 8 In (E), the cross-section of the embedded portion of the VTG is rectangular with rounded corners on the FD side. Depending on the requirements of the manufacturing process or circuit layout, these or other shapes can be selected to improve the charge transfer capability of the VTG.

[0095] Fig. 9 2 is a cross-sectional view showing various shapes of PD according to the seventh embodiment of the present invention. Fig. 9 In the examples shown in (A) to (D) of FIG. 1 , each N-PD has structures 901 to 904 on the side thereof facing the color filter (CF). Structures 901 to 904 may include one or more square pyramids or one or more cones, and one triangle on the cross section may correspond to one square pyramid or cone. Structures 901 to 904 reduce the reflectivity of electromagnetic radiation incident from a microlens (ML) and increase the absorption. Structures 901 to 904 may be any other structures that achieve similar purposes.

[0096] Fig.10Various circuits of a shared pixel device according to an eighth embodiment of the present invention are shown. The pixel device includes a transfer gate (TX) device, a floating diffusion node (FD), a reset device (RST), a dual conversion gain (DCG) device, an amplifier (AMP) device, and a selector (SEL). TX corresponds to the vertical transfer gate (VTG) device described above. The photodiode (PD) corresponds to any one of PD1 to PD4 described above. AVSS1 and AVSS2 are ground or negative voltages, for example, in the range of -5.0V to 0V. For a description of the pixel device, see Figure 1 Description.

[0097] like Fig.10 As shown, a pixel device may be provided for one PD (1001), shared by two PDs (1002), shared by four PDs (1004), shared by eight PDs (1008), or shared by any other number of PDs.

[0098] The present invention is applicable to image sensors that read data frame by frame. A frame consists of all pixels in an array, and frame-by-frame data reading is accomplished by sequentially reading the pixel charges stored in all pixels in the array using row selection transistors. Alternatively, the present invention can be applied to image sensors that operate in a so-called event-driven manner. In an event-driven image sensor, data can be output asynchronously at any time in response to changes in the intensity of electromagnetic radiation incident on the pixel. Specifically, when the pixel charge generated by the electromagnetic radiation incident on the pixel and stored in the pixel exceeds a predetermined threshold, data is output to indicate that the intensity of the electromagnetic radiation has exceeded the threshold, or the pixel coordinates and time information are combined to indicate the intensity of the electromagnetic radiation.

[0099] In some embodiments, the pixels are controlled in a global shutter manner. That is, the solid-state imaging device has a synchronized shutter function for all pixels in the voltage domain or the charge domain.

[0100] Fig.11 Various circuits of a pixel device according to a ninth embodiment of the present invention are shown. Fig.11 (A) to (D) show the addition to Fig.10The capacitors C1 to C4 in the circuit. The capacitors C1 to C4 have large capacitance, and may include, for example, PN junction capacitors, MOS capacitors, metal-oxide-metal (MOM) capacitors, metal-insulator-metal (MIM) capacitors, capacitive DTI or polysilicon-insulator-polysilicon (PIP) capacitors, or memories such as dynamic random access memory (DRAM) and magnetoresistive random access memory (MRAM), or a combination thereof.

[0101] Taking (A) as an example, one end of C1 is connected between RST and DCG, and the other end of C1 is grounded. Taking (B) as an example, one end of C2 is connected between RST and DCG, and the other end of C2 is connected to AMP and AVDD2. Taking (C) as an example, one end of C3 is connected between RST and DCG, and the other end of C3 is connected to the constant voltage Vconst. Taking (D) as an example, one end of C4 is connected between RST and DCG, and the other end of C4 is connected to the pulse voltage Vpulse.

[0102] FD is electrically connected to any one of C1 to C4, and C1 to C4 can store excess charge, thereby increasing the full well capacity of FD. By turning on DCG, excess charge from the photodiode (PD) generated in a high illumination environment can be retained in C1 to C4 instead of being discharged. When the solid-state imaging device is operating in a high illumination environment, DCG can always be turned on. The increased full well capacity of C1 to C4 reduces the potential change of FD, even in the presence of excess charge. Therefore, in a high illumination environment, the conversion gain is reduced.

[0103] Fig.12 An exemplary pixel array to which an embodiment of the present invention is applied is shown. The solid-state imaging device 1200 includes a pixel array 1201, a control circuit 1202, a readout circuit 1203, and a signal processing circuit 1204. The pixel array 1201 is a two-dimensional (2D) array of pixels, in which pixels are arranged in rows ( Fig.12 R1 to Ry) and columns ( Fig.12C1 to Cx in the image processing circuit 1201, each pixel can detect electromagnetic radiation. Each pixel may include any one of the above-mentioned PD1 to PD4. The control circuit 1202 generates a shutter signal, a row selection signal, and other control signals to control the pixel array 1201, so that each pixel in the pixel array 1201 outputs a digital signal corresponding to the detected electromagnetic radiation to the readout circuit 1203 through a bit line. The readout circuit 1203 transmits the digital signal to the signal processing circuit 1204 for further processing. The pixel array 1201 can be front-illuminated or back-illuminated.

[0104] Fig.13 A cross-sectional view showing a portion of an exemplary pixel array to which an embodiment of the present invention is applied. Fig.13 A backside deep trench isolation (DTI) is shown. In other embodiments, a front DTI may be used. A color filter (CF) is placed under the microlens (ML), PD1 to PD4 are mounted under the CF, and a TX corresponding to the above-mentioned VTG is placed near the PD. Other pixel devices may be implemented on the same layer as the TX or on any other layer. The control circuit 1202, the readout circuit 1203, and the signal processing circuit 1204 may also be implemented on the same layer as the TX. Any other layout is possible, depending on the implementation. Fig.13 Just one example is shown. Fig.13 The structure shown can be partially Figure 2A , Figure 3 and Figures 7 to 9 substituted with any one of the structures shown.

[0105] Fig.14 A schematic structural diagram showing an exemplary solid-state imaging device to which an embodiment of the present invention is applied. Fig.14 The pixel array can correspond to Fig.12 The pixel array 1201 may include the pixel unit 100 according to the present invention.

[0106] Fig.14 A in FIG. 1 shows a standard solid-state imaging device including a pixel array, control circuitry, and signal processing circuitry mounted on a single semiconductor chip. The semiconductor substrate may be composed of a semiconductor material such as silicon or gallium. In some embodiments, the semiconductor substrate may be composed of one or more other materials sensitive to electromagnetic radiation, such as silicon germanium, silicon carbide, potassium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium, antimony, semiconductors on insulators, or combinations thereof.

[0107] Fig.14B in FIG. 1 shows a solid-state imaging device having a first semiconductor chip portion and a second semiconductor chip portion. The first semiconductor chip portion includes a pixel array and a control circuit, and the second semiconductor chip portion includes a signal processing circuit. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other to form a single semiconductor chip of the solid-state imaging device.

[0108] Fig.14 C in FIG. 1 shows a solid-state imaging device having a first semiconductor chip portion and a second semiconductor chip portion. The first semiconductor chip portion includes a pixel array, and the second semiconductor chip portion includes a control circuit and a signal processing circuit. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other to form a single semiconductor chip of the solid-state imaging device.

[0109] Fig.14 D in FIG. 1 shows a solid-state imaging device having a first semiconductor chip portion, a second semiconductor chip portion, and a third semiconductor chip portion. The first semiconductor chip portion includes a pixel array, the second semiconductor chip portion includes a memory circuit, and the third semiconductor chip portion includes a control circuit and a signal processing circuit. The first semiconductor chip portion, the second semiconductor chip portion, and the third semiconductor chip portion are electrically connected to each other to form a single semiconductor chip or two semiconductor chips of a solid-state imaging device.

[0110] Fig.14 E in FIG. 1 shows a solid-state imaging device having a first semiconductor chip portion, a second semiconductor chip portion, and a third semiconductor chip portion. The first semiconductor chip portion includes a pixel array, the second semiconductor chip portion includes a pixel circuit, and the third semiconductor chip portion includes a control circuit and a signal processing circuit. The first semiconductor chip portion, the second semiconductor chip portion, and the third semiconductor chip portion are electrically connected to each other to form a single semiconductor chip or two semiconductor chips of a solid-state imaging device.

[0111] Fig.15 A schematic block diagram of an exemplary electronic device to which an embodiment of the present invention is applied is shown. The electronic device 1500 includes a lens 1501, an imaging element 1502, a digital signal processing (DSP) circuit 1503, a frame memory 1504, a display unit 1505, a recording unit 1506, an operation unit 1507, a power supply unit 1508, and a bus 1509 connecting these devices together.

[0112] For example, imaging element 1502 may be Fig.12The solid-state imaging device 1200 of the present invention is shown. The DSP circuit 1503 is a camera signal processing circuit that processes the signal provided from the imaging element 1502. The DSP circuit 1503 outputs image data obtained by processing the signal from the imaging element 1502. The frame memory 1504 temporarily stores the image data processed by the DSP circuit 1503 in units of frames. The display unit 1505 includes a flat panel display device such as a liquid crystal panel or an organic electroluminescence (EL) panel to display a moving image or a still image imaged by the imaging element 1502. The recording unit 1506 records the image data of the moving image or the still image captured by the imaging element 1502 on a recording medium such as a semiconductor memory or a hard disk.

[0113] The operation unit 1507 outputs arithmetic instructions associated with various functions of the electronic device 1500 according to the user's operation. The power supply unit 1508 supplies power to the DSP circuit 1503, the frame memory 1504, the display unit 1505, the recording unit 1506, and the operation unit 1507.

[0114] Fig.16 An exemplary technical field to which an embodiment of the present invention is applied is shown. For example, a solid-state imaging device according to the present invention may be included in an electronic device, an image sensor, or any other device. The solid-state imaging device according to the present invention may be applied to various fields, such as sports equipment such as wearable cameras; medical equipment such as endoscopes; beauty salons; trucks or transportation equipment that support automatic / autonomous driving, etc.; entertainment equipment such as mobile phones, game terminals, digital cameras, and video cameras; agricultural fields such as farm surveillance cameras; household appliances such as televisions and refrigerators; disaster notification systems such as surveillance cameras, network cameras, machine vision cameras, broadcast cameras, and surveillance cameras for rivers / dams / oceans / roads / construction sites; and any other fields.

[0115] Fig.17An example of applying an embodiment of the present invention to a vehicle is shown. Vehicle 1700 includes image sensors 1701, 1702, 1703, 1704, and 1705, which include solid-state image sensors according to the present invention. Image sensor 1701 is located in front of vehicle 1700 and is used to monitor a front area 1711 of vehicle 1700. Image sensor 1702 is located in the left rearview mirror of vehicle 1700 and is used to monitor a left area 1712 of vehicle 1700. Image sensor 1703 is located in the right rearview mirror of vehicle 1700 and is used to monitor a right area 1713 of vehicle 1700. Image sensor 1704 is located in the rear camera of vehicle 1700 and is used to monitor a rear area 1714 of vehicle 1700. Image sensor 1705 is located on the roof of vehicle 1700 and is used to monitor an area farther than areas 1711 to 1714 , or to monitor the surrounding environment of vehicle 1700 from a higher position than image sensors 1701 to 1704 . Fig.17 The image sensors shown are only one example. In other embodiments, the image sensors may be located at other locations on the vehicle 1700 to monitor other areas, and the number of image sensors may be more or less than 1. Fig.17 The number of image sensors shown in .

[0116] Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the scope of the present application. Therefore, as long as these modifications and changes are within the scope of protection defined by the attached claims and their equivalents, the present application is also intended to cover these modifications and changes of the present application.

Claims

1. A solid-state imaging device, characterized in that comprising a pixel array, wherein each pixel of the pixel array comprises: photodiodes, which convert electromagnetic radiation into an electrical charge; a transfer gate device for transferring the charge from the photodiode to a floating diffusion node, The transmission gate device includes an embedded portion embedded in the pixel array, and a first wall of the embedded portion facing the floating diffusion node and a second wall of the embedded portion not facing the floating diffusion node have different shapes.

2. The solid-state imaging device according to claim 1, wherein The embedded portion includes a bottom surface between a surface of the pixel array and the photodiode; Each pixel includes a P-type doping region between the bottom surface and the photodiode, and also includes an N-type doping region between the P-type doping region and the photodiode.

3. The solid-state imaging device according to claim 2, wherein The P-type doping region further extends to one side of the transmission gate device.

4. The solid-state imaging device according to claim 1, wherein The embedded portion includes a bottom surface between a surface of the pixel array and the photodiode; Each pixel includes a P-type doped region between the bottom surface and the photodiode.

5. The solid-state imaging device according to claim 4, wherein The P-type doping region further extends to one side of the transmission gate device.

6. The solid-state imaging device according to claim 2, wherein: The P-type doped region and the N-type doped region are self-aligned with the transmission gate device.

7. The solid-state imaging device according to claim 6, wherein A P-type well between the embedded portion and the pixel device is deeper than a P-type well between the embedded portion and the floating diffusion node.

8. The solid-state imaging device according to claim 7, wherein A cross section of the embedding portion parallel to the surface of the pixel array is a combination of a polygon or curves.

9. The solid-state imaging device according to claim 8, wherein The transmission gate device further includes a protrusion formed on a surface of the pixel array; In the cross section of the embedded portion parallel to the surface of the pixel array, part or all of the polygonal sides or the plurality of curved lines are located outside the region of the protruding portion.

10. The solid-state imaging device according to claim 8, wherein The pixel array includes a pixel unit including four pixels coupled to the same floating diffusion node, and the embedded portion included in the pixel unit is arranged in a ring shape.

11. The solid-state imaging device according to claim 10, wherein The embedded portion included in the pixel unit is arranged to be 90 degrees rotationally symmetric or 180 degrees rotationally symmetric with respect to the same floating diffusion node.

12. The solid-state imaging device according to claim 11, wherein In the cross-section of the embedded portion parallel to the surface of the pixel array, the first wall has a first arc including a first center and a first radius, the second wall has a second arc including a second center and a second radius, and wherein the first center and the second center are both between the floating diffusion node and the transmission gate device, and the first radius is smaller than the second radius.

13. The solid-state imaging device according to claim 12, wherein The transmission gate device further includes a protrusion formed on a surface of the pixel array; The first wall and the second wall are arranged opposite to each other, and the embedded portion further comprises a third wall and a fourth wall, wherein the third wall and the fourth wall are connected to the first wall and the second wall respectively; In the cross section of the embedded portion parallel to the surface of the pixel array, part or all of one or more of the first wall, the second wall, the third wall, and the fourth wall are located outside the region of the protruding portion.

14. The solid-state imaging device according to claim 13, wherein The cross section of the embedded portion perpendicular to the surface of the pixel array is any one of the following shapes: square; a trapezoidal shape narrowing toward the bottom surface; a trapezoidal shape that widens toward the bottom surface; Parallelogram; is generally rectangular in shape, with rounded corners on one side of said bottom surface; It is generally rectangular and has rounded corners on one side of the surface of the pixel array.

15. The solid-state imaging device according to claim 14, characterized in that A portion of the overflow path is formed between the bottom surface of the embedding portion and the photodiode, or is formed below the bottom surface of the embedding portion inside the photodiode.

16. The solid-state imaging device according to claim 15, characterized in that The overflow path is a path for transferring photoelectric charges exceeding a full well capacity of the photodiode to the floating diffusion node.

17. An electronic device, characterized in that: A solid-state imaging device according to any one of claims 1 to 16 is included.

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