Chip fault positioning method
The chip fault location method using an insulating polymer film and organic solvent isolates high-voltage chips from air, preventing breakdown and enhancing fault detection accuracy while maintaining chip integrity and efficiency.
Patent Information
- Application Number
- CN202411351365.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2024-12-31
AI Technical Summary
High-voltage chip testing often results in air breakdown and irreversible damage due to sparking, necessitating costly vacuum environments and prolonged setup times, which reduce test efficiency.
A chip fault location method using an insulating polymer film with pre-drilled holes to cover the chip surface, combined with an organic solvent to isolate the chip from air, allowing for high-voltage testing without air breakdown, and utilizing thermal radiation positioning for accurate fault detection.
Enhances test withstand voltage, prevents air breakdown, maintains chip structure integrity, and improves fault location accuracy without requiring heating or chemical treatments.
Smart Images
Figure CN119224535A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip fault locating method. Background Art
[0002] In order to find the fault point without destroying the device structure of the chip, the thermal radiation positioning method is often used. The principle is to use a high-resolution infrared camera to receive the thermal radiation generated by the fault point in the chip after power is turned on, thereby locating the fault point. When the chip is a high-voltage chip, since a very high voltage is applied to the chip during positioning, air breakdown often occurs during testing, causing sparks, causing irreversible damage to the chip, and forcing the positioning to be interrupted. For example, when testing a high-voltage chip, the back of the chip is used as the positive electrode and the front of the chip is used as the negative electrode. When the electric field strength of the positive and negative electrodes reaches the air breakdown voltage, discharge will occur between the positive and negative electrodes, also known as sparking.
[0003] Figure 1 This is a diagram showing the relationship between voltage and current when a chip breaks down in the prior art. Please refer to Figure 1 Taking a 1200V SiCMOS chip as an example, when the IDSS test voltage rises to 620V, the current suddenly increases, and the chip has already broken down ( Figure 1 shown in the middle circle).
[0004] Figure 2 It is a heat radiation positioning map after the chip is broken down in the prior art. Figure 3 This is an optical inspection image of a chip after breakdown in the prior art. Please refer to Figure 2 and Figure 3 , Figure 2 and Figure 3 for Figure 1 Take the chip as an example to generate an example of a breakdown. By locating the thermal radiation of the chip after the breakdown, a hot spot is found in the ring area of the chip ( Figure 2 As shown in the red box in the figure, this hot spot is the breakdown point of the chip; after optical inspection of the hot spot, it was found that there was a burn at the hot spot ( Figure 3 shown in the red box).
[0005] At present, when air breakdown occurs in the chip and sparks occur, a medium with high electrical strength can be used to replace the air to reduce the occurrence of sparks. For example, without affecting the detection of thermal signals, air breakdown can be avoided as much as possible. Tests can be performed in a vacuum environment or a protective gas atmosphere. Taking vacuum environment testing as an example, the chip is placed in a closed cavity, and the cavity is evacuated during the test to improve the breakdown problem during high-voltage testing. However, in order to meet the needs of high-voltage testing, a vacuum cavity and a vacuum pump are added to the equipment, which increases the cost of the equipment; and the cavity needs to be evacuated before each test, which takes a lot of testing time and reduces test efficiency. Summary of the invention
[0006] The object of the present invention is to provide a chip fault location method to avoid air breakdown of the chip during fault location and to improve the accuracy of location.
[0007] In order to achieve the above object, the present invention provides a chip fault location method, comprising:
[0008] Providing a chip, wherein a surface of the chip has a plurality of pads;
[0009] Providing an insulating polymer film, and opening a plurality of holes corresponding to the positions of the plurality of pads on the insulating polymer film;
[0010] placing the chip on the conductive substrate and covering the surface of the chip with an organic solvent;
[0011] Covering the surface of the chip with the insulating polymer film, with the hole corresponding to the position of the pad to expose the pad;
[0012] Laminating the insulating polymer film to the chip;
[0013] The pads are led out, and the fault location of the chip is performed to obtain the fault point of the chip.
[0014] Optionally, the insulating polymer film is made of cellulose acetate.
[0015] Optionally, the organic solvent includes acetone.
[0016] Optionally, the back side of the chip contacts the conductive substrate to lead out the back side electrode of the chip.
[0017] Optionally, the organic solvent covers the front and side surfaces of the chip.
[0018] Optionally, when providing the chip, the front side of the chip has a plurality of the pads; when covering the surface of the chip with the insulating polymer film, the insulating polymer film covers the front side and side surfaces of the chip, and the pads are exposed through the holes opened in the insulating polymer film.
[0019] Optionally, a compressed air gun is used to blow air from the top of the chip toward the periphery of the chip, so that the organic solvent evaporates and the insulating polymer film is bonded to the chip.
[0020] Optionally, a thermal radiation positioning method is used to locate the fault of the chip.
[0021] Optionally, after locating the fault of the chip, tweezers are used to peel off and remove the insulating polymer film.
[0022] Optionally, the surface of the chip has a metal layer, and when the insulating polymer film covers the surface of the chip, the insulating polymer film contacts the metal layer.
[0023] In the chip fault location method provided by the present invention, a chip is provided, and the surface of the chip has a plurality of pads; an insulating polymer film is provided, and a plurality of holes corresponding to the positions of the plurality of pads are opened on the insulating polymer film; the chip is placed on a conductive substrate, and an organic solvent is covered on the surface of the chip; the surface of the chip is covered with the insulating polymer film, and the holes correspond to the positions of the pads to expose the pads; the insulating polymer film is attached to the chip; the pads are led out, and the chip is fault located to obtain the fault point of the chip. The present invention isolates the chip from the air by covering the surface of the chip with an insulating polymer film, thereby improving the test withstand voltage and avoiding air breakdown of the chip during fault location; and the method does not require heating treatment and does not use strong acid and alkali reagents, and will not damage the chip structure. At the same time, the insulating polymer film can enhance the thermal signal and improve the accuracy of positioning. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 This is a diagram showing the relationship between voltage and current when a chip breaks down in the prior art.
[0025] Figure 2 The present invention is a heat radiation positioning diagram of a chip after breakdown in the prior art.
[0026] Figure 3 Produce optical inspection images after breakdown for chips in the prior art.
[0027] Figure 4 The present invention provides a flowchart of a chip fault location method according to an embodiment of the present invention.
[0028] Figure 5A schematic diagram of a chip is provided in a chip fault location method provided in an embodiment of the present invention.
[0029] Figure 6 A schematic diagram of an insulating polymer film is provided in a chip fault location method provided in an embodiment of the present invention.
[0030] Figure 7 A schematic diagram of a chip covered with an organic solvent in a chip fault locating method provided by an embodiment of the present invention.
[0031] Figure 8 A schematic diagram of an insulating polymer film covering a chip in a chip fault location method provided by an embodiment of the present invention.
[0032] Fig. 9 A schematic diagram of the contact between an insulating polymer film and an organic solvent in a chip fault locating method provided by an embodiment of the present invention.
[0033] Fig.10 A schematic diagram of bonding an insulating polymer film to a chip in a chip fault location method provided by an embodiment of the present invention.
[0034] Fig.11 This is an optical inspection diagram of the bonding between the insulating polymer film and the chip in the chip fault locating method provided by one embodiment of the present invention.
[0035] Fig.12 A diagram showing the relationship between voltage and current when performing fault location in a chip fault location method provided by an embodiment of the present invention.
[0036] Fig.13 A chip fault location method provided in an embodiment of the present invention obtains a thermal radiation location map of a chip fault point.
[0037] Wherein, the accompanying drawings are marked as follows:
[0038] 10-chip; 12-pad; 20-insulating polymer film; 22-hole; 30-conductive substrate; 40-organic solvent. DETAILED DESCRIPTION
[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. The drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often part of the actual structure; in particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0040] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0041] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0042] In addition, relational terms such as the terms "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such articles or equipment. In the absence of further restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the articles or equipment including the elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.
[0043] Figure 4 This is a flowchart of the chip fault location method provided in this embodiment. Please refer to Figure 4 This embodiment provides a chip fault location method, including:
[0044] Step S1: providing a chip, wherein the surface of the chip has a plurality of pads;
[0045] Step S2: providing an insulating polymer film, and opening a plurality of holes corresponding to the positions of the plurality of pads on the insulating polymer film;
[0046] Step S3: placing the chip on a conductive substrate and covering the surface of the chip with an organic solvent;
[0047] Step S4: Covering the surface of the chip with an insulating polymer film, with the holes corresponding to the positions of the pads to expose the pads;
[0048] Step S5: Laminating the insulating polymer film to the chip;
[0049] Step S6: Lead out the pads and locate the chip fault to obtain the chip fault point.
[0050] Figure 5 A schematic diagram of a chip is provided in the chip fault locating method provided in this embodiment. Figure 6 A schematic diagram of an insulating polymer film is provided in the chip fault location method provided in this embodiment. Figure 7 This is a schematic diagram of a chip covered with an organic solvent in the chip fault locating method provided in this embodiment. Figure 8 This is a schematic diagram of the chip being covered by an insulating polymer film in the chip fault location method provided in this embodiment. Fig. 9 This is a schematic diagram of the contact between the insulating polymer film and the organic solvent in the chip fault location method provided in this embodiment. Fig.10 This is a schematic diagram of the bonding of the insulating polymer film to the chip in the chip fault locating method provided in this embodiment.
[0051] Fig.11 This is an optical inspection diagram of the bonding between the insulating polymer film and the chip in the chip fault locating method provided in this embodiment. Fig.12 This is a diagram showing the relationship between voltage and current when performing fault location in the chip fault location method provided in this embodiment. Fig.13 The chip fault location method provided in this embodiment obtains the thermal radiation location map of the chip fault point. Figure 5 to Figure 13 The chip fault locating method provided in this embodiment is described in detail.
[0052] Please refer to Figure 5 , executing step S1: providing a chip 10, the periphery of the chip 10 is exemplified as a ring area, and the surface of the chip 10 has a plurality of pads 12, specifically the front side of the chip 10 ( Figure 5 The front side of the chip 10 is shown in FIG. 1 . The chip 10 has a plurality of pads 12. The pads 12 are brought out to test the chip 10. Figure 5 The distribution, shape and number of pads 12 on the chip 10 are only exemplified. Figure 5 Two pads 12 are shown in the example. The two pads 12 are isolated from each other. The range of the first pad 12 is Figure 5 The light-colored filled area in the left square box is the range of the second pad 12. Figure 5 The other light-colored filled areas outside the left square frame are actually not limited to the number of the above-mentioned pads 12, the shape of the pads 12, and the distribution position of the pads 12 on the front of the chip 10. The back of the chip 10 has a back electrode. In this embodiment, the chip 10 is a high-voltage chip, such as a high-voltage MOS chip.
[0053] Please refer to Figure 6 , execute step S2: provide an insulating polymer film 20, and open a plurality of holes 22 on the insulating polymer film 20 corresponding to the positions of the plurality of pads on the chip, and open the holes in advance to reserve positions for subsequent pad piercing. In this embodiment, the material of the insulating polymer film 20 is preferably cellulose acetate, which has strong toughness after subsequent hardening and shaping, and is difficult for the probe to penetrate, but is not limited to this material; and the insulating polymer film 20 needs to be cut to a size corresponding to the size of the chip, so that the subsequent insulating polymer film 20 can completely cover the front and side of the chip. The size of the hole 22 on the insulating polymer film 20 is preferably smaller than the size of the pad on the chip, so that only the pad is exposed later and the area outside the pad is not exposed, and the probe can also be accommodated for piercing test.
[0054] Please refer to Figure 7 , executing step S3: placing the chip 10 on the conductive substrate 30, specifically, the back side of the chip 10 is in contact with the conductive substrate 30 to lead out the back electrode of the chip 10; then, dropping the organic solvent 40 on the surface of the chip 10 so that the organic solvent 40 covers the surface of the chip 10, specifically, the organic solvent 40 covers the front and side surfaces of the chip 10, and can also extend to the conductive substrate 30, Figure 7 The organic solvent 40 is provided with transparency to facilitate the viewing of the chip 10. In this embodiment, the organic solvent 40 is preferably acetone, which can soften the cellulose acetate (insulating polymer film 20) and improve the adhesion between the film and the chip 10, facilitating the subsequent bonding.
[0055] Please refer to Figure 8 , perform step S4: cover the surface of the chip 10 with the insulating polymer film 20. Specifically, the insulating polymer film 20 covers the front and side surfaces of the chip 10, and the holes 22 correspond to the positions of the pads 12 to expose part of the surface of the pads 12. The pads 12 are exposed through the holes 22 opened in the insulating polymer film 20; specifically, each hole 22 corresponds to the position of the corresponding pad 12 to expose each pad 12, so as to facilitate the subsequent pinning of the pads 12 to lead out the pad signals. In this embodiment, the surface of the provided chip 10 has a metal layer (not shown in the figure). When the insulating polymer film 20 covers the surface of the chip 10, the insulating polymer film 20 contacts the metal layer. Without destroying the chip structure, the metal layer on the surface of the chip 10 will block part of the thermal radiation signal. The thermal radiation emissivity of cellulose acetate (insulating polymer film 20) is much higher than that of metal at room temperature. Therefore, the provision of the insulating polymer film 20 can enhance the thermal radiation signal.
[0056] Please refer to Fig. 9 and Fig.10 , executing step S5: the step of attaching the insulating polymer film 20 to the chip 10 includes: using a compressed air gun to press the top of the chip 10 ( Fig. 9 The insulating polymer film 20 is bonded to the chip 10 by blowing air toward the edges of the chip 10 so that the organic solvent 40 evaporates. Fig.10 4 is a schematic diagram of the insulating polymer film 20 and the chip 10 after being bonded together, at which time the organic solvent 40 has evaporated. In this embodiment, the cellulose acetate (insulating polymer film 20) has been softened by acetone, so that the insulating polymer film 20 has a certain plasticity. The pressure of the airflow generated by the compressed air gun can tightly bond the insulating polymer film 20 to the surface of the chip 10, and at the same time, the acetone can evaporate quickly. After the acetone evaporates, the insulating polymer film 20 is fixed.
[0057] Execute step S6: use a probe to poke the exposed pad to lead out the pad to obtain the pad signal, and the back electrode of the chip is led out through the conductive substrate, and the chip is fault located by the thermal radiation positioning method to obtain the fault point of the chip. The thermal radiation positioning method applies a high voltage when locating the chip fault until the fault point of the chip is obtained.
[0058] Furthermore, after locating the fault of the chip, tweezers are used to peel off and remove the insulating polymer film, and then PFA analysis (Physical Failure Analysis) is performed; since the adhesion of the insulating polymer film is low, no heating treatment or chemical reagents (strong acid and alkali reagents) are required, and the chip structure will not be damaged. The insulating polymer film can be peeled off and completely removed with tweezers.
[0059] Please refer to Fig.11 , Fig.11 The optical inspection diagram after the insulating polymer film and the chip are bonded is shown in FIG. 1 , where the chip may be a 1200V SiC MOS chip. Please refer to Fig.12 ,right Fig.11 The 1200V SiC MOS chip was tested with an IDSS voltage of 1200V, but the chip did not break down. This shows that by covering the surface of the chip with an insulating polymer film to isolate the chip from the air, the test withstand voltage can be improved, thus preventing the chip from breaking down in the air during fault location. Fig.13 , in the right Fig.11 After the thermal radiation positioning of the 1200V SiC MOS chip, bright spots were found in the cell area (or cell area) of the chip. Fig.13 This bright spot is the fault point.
[0060] In summary, in the chip fault location method provided by the present invention, a chip is provided, and the surface of the chip has a plurality of pads; an insulating polymer film is provided, and a plurality of holes corresponding to the positions of the plurality of pads are opened on the insulating polymer film; the chip is placed on a conductive substrate, and an organic solvent is covered on the surface of the chip; the surface of the chip is covered with the insulating polymer film, and the holes correspond to the positions of the pads to expose the pads; the insulating polymer film is attached to the chip; the pads are led out, and the chip is fault located to obtain the fault point of the chip. The present invention isolates the chip from the air by covering the surface of the chip with an insulating polymer film, thereby improving the test withstand voltage and avoiding air breakdown of the chip during fault location; and the method does not require heating treatment and does not use strong acid and alkali reagents, and will not damage the chip structure. At the same time, the insulating polymer film can enhance the thermal signal and improve the accuracy of positioning.
[0061] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.
Claims
1. A chip fault location method, characterized in that: include: Providing a chip, wherein a surface of the chip has a plurality of pads; Providing an insulating polymer film, and opening a plurality of holes corresponding to the positions of the plurality of pads on the insulating polymer film; placing the chip on the conductive substrate and covering the surface of the chip with an organic solvent; Covering the surface of the chip with the insulating polymer film, with the hole corresponding to the position of the pad to expose the pad; Laminating the insulating polymer film to the chip; The pads are led out, and the fault location of the chip is performed to obtain the fault point of the chip.
2. The chip fault location method according to claim 1, characterized in that: The insulating polymer film is made of cellulose acetate.
3. The chip fault location method according to claim 2, characterized in that: The organic solvent includes acetone.
4. The chip fault location method according to claim 1, characterized in that: The back surface of the chip contacts the conductive substrate to lead out the back surface electrode of the chip.
5. The chip fault location method according to claim 4, characterized in that: The organic solvent covers the front and side surfaces of the chip.
6. The chip fault location method according to claim 1, characterized in that: When the chip is provided, the front side of the chip has a plurality of pads; when the insulating polymer film covers the surface of the chip, the insulating polymer film covers the front side and side of the chip, and the pads are exposed through the holes opened in the insulating polymer film.
7. The chip fault location method according to claim 1, characterized in that: A compressed air gun is used to blow air from the top of the chip to the periphery of the chip, so that the organic solvent is volatilized and the insulating polymer film is bonded to the chip.
8. The chip fault location method according to claim 1, characterized in that: A thermal radiation positioning method is used to locate the fault of the chip.
9. The chip fault location method according to claim 1, characterized in that: After locating the fault of the chip, the insulating polymer film is peeled off and removed using tweezers.
10. The chip fault location method according to claim 1, characterized in that: The surface of the chip has a metal layer, and when the insulating polymer film covers the surface of the chip, the insulating polymer film is in contact with the metal layer.