Hardware equipment identification method, control system and storage medium

Abstract

The invention discloses a hardware equipment identification method, a control system and a storage medium. The method is applied to a control system, hardware equipment comprises a resistor and a capacitor, a first port of the control system is grounded through the resistor and the capacitor, and a second port of the control system is connected between the capacitor and the resistor. The identification method comprises the following steps: in response to connection between hardware equipment and a control system, sampling the hardware equipment through the control system to obtain a first voltage signal; and identifying the model of the hardware equipment based on the first voltage signal. The signal of the hardware equipment is identified through the first voltage signal, the upper limit of the identification number of the hardware equipment does not need to be increased through a GPIO expansion mode, and the cost is greatly reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method for identifying a hardware device, a control system, and a storage medium. Background Art

[0002] At present, in the actual project use process, the solution of identifying hardware devices by obtaining the GPIO (General-purpose input / output) status can be used. The more hardware devices that need to be identified, the more system GPIO resources need to be occupied. Increasing the number of GPIOs through GPIO expansion to increase the upper limit of the number of hardware devices to be identified will greatly increase the hardware cost. Summary of the invention

[0003] In view of this, the present application provides a hardware device identification method, a control system and a storage medium to solve the above technical problems.

[0004] The first aspect of the present application provides a method for identifying a hardware device, which is applied to a control system, wherein the hardware device includes a resistor and a capacitor, a first port of the control system is grounded through the resistor and the capacitor, and a second port of the control system is connected between the capacitor and the resistor; the identification method includes: in response to the hardware device being connected to the control system, sampling the hardware device through the control system to obtain a first voltage signal; and identifying the model of the hardware device based on the first voltage signal.

[0005] In some embodiments, the identification method also includes: in response to the hardware device being connected to the control system, outputting a second voltage signal through a first port of the control system, wherein the second voltage signal is used to charge the capacitor; and when the first port outputs the second voltage signal, counting the charging time of the capacitor through the control system.

[0006] In some embodiments, the step of identifying the model of the hardware device based on the first voltage signal includes: acquiring the first voltage signal through the second port of the control system; and identifying the type of the hardware device based on the charging time.

[0007] In some embodiments, after the step of acquiring the first voltage signal through the second port of the control system, the identification method further includes: in response to the first voltage signal being at a high level, stopping counting the charging time of the capacitor to obtain the charging time.

[0008] In some embodiments, the step of identifying the type of the hardware device based on the charging time of the capacitor includes: calculating the theoretical charging time of the capacitor in the hardware device; and comparing the charging time with the theoretical charging time to identify the type of the hardware device.

[0009] In some embodiments, the step of comparing the charging time with the theoretical charging time to identify the type of the hardware device includes: calculating a first error based on the charging time and the theoretical charging time; determining whether the first error is less than a preset error; in response to the first error being less than a preset error, identifying the hardware device as a hardware device corresponding to the capacitor charging time.

[0010] In some embodiments, the identification method further includes: determining whether the control system is connected to the hardware device; in response to the control system not being connected to the hardware device, returning to the step of determining whether the control system is connected to the hardware device.

[0011] A second aspect of the present application provides a control system, which is connected to a hardware device, and is used to sample the hardware device to obtain a first voltage signal, and identify the model of the hardware device based on the first voltage signal.

[0012] In some embodiments, the hardware device includes a resistor and a capacitor, the first port of the control system is grounded through the resistor and the capacitor, and the second port of the control system is connected between the capacitor and the resistor.

[0013] In some embodiments, the control system includes an analog-to-digital converter, the hardware device includes a first resistor and a second resistor, the control system is connected between the first resistor and the second resistor through the analog-to-digital converter, one end of the first resistor receives a reference voltage, and one end of the second resistor is grounded.

[0014] A third aspect of the present application provides a non-volatile computer-readable storage medium having program instructions stored thereon, and when the program instructions are executed by a processor, the method for identifying a hardware device in the first aspect described above is implemented.

[0015] The hardware device identification method, control system and storage medium provided in the present application can sample the hardware device through the control system to obtain a first voltage signal, and identify the model of the hardware device based on the first voltage signal. There is no need to increase the upper limit of the number of hardware devices to be identified through GPIO expansion, which greatly reduces costs.

[0016] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a flowchart of an embodiment of a method for identifying a hardware device of the present application;

[0019] Figure 2 yes Figure 1 A schematic flow chart of an embodiment of step S12;

[0020] Figure 3 yes Figure 1 A schematic flow chart of an embodiment of step S13;

[0021] Figure 4 yes Figure 3 A schematic flow chart of an embodiment of step S33;

[0022] Figure 5 yes Figure 1 A schematic flow chart of another embodiment of step S12;

[0023] Figure 6 It is a structural schematic diagram of an embodiment of the control system of the present application;

[0024] Figure 7 It is a structural schematic diagram of another embodiment of the control system of the present application;

[0025] Figure 8 It is a schematic diagram of a framework of an embodiment of the non-volatile computer-readable storage medium of the present application. DETAILED DESCRIPTION

[0026] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification. It is particularly pointed out that the following embodiments are only used to illustrate the present application, but do not limit the scope of the present application. Similarly, the following embodiments are only some embodiments of the present application rather than all embodiments. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "set", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or connected through an intermediate medium. For ordinary technicians in this field, the above-mentioned specific meanings belonging to this application can be connected according to specific circumstances.

[0029] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other.

[0030] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship. In addition, "many" in this article means two or more than two. In addition, the term "at least one" in this article means any combination of at least two of any one or more of a plurality of, for example, including at least one of A, B, and C, can mean including any one or more elements selected from the set consisting of A, B, and C.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0032] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0033] At present, in the actual project use process, the solution of identifying hardware devices by obtaining GPIO status can be used. The more hardware devices that need to be identified, the more system GPIO resources need to be occupied. Increasing the number of GPIOs through GPIO expansion to increase the upper limit of the number of hardware devices to be identified will greatly increase the hardware cost.

[0034] In order to solve the above problems, this application proposes a method for identifying hardware devices. Figure 1 , Figure 1 1 is a flow chart of an embodiment of a method for identifying a hardware device of the present application. The method can be applied to a control system. In some possible implementations, the method can be implemented by a processor calling a computer-readable instruction stored in a memory. Specifically, the following steps can be included:

[0035] Step S11: Determine whether the control system is connected to the hardware device.

[0036] When the control system is running, it will determine whether the hardware device is connected to the control system. If the control system is not connected to the hardware device, it returns to step S11; if the hardware device is connected to the control system, it goes to step S12.

[0037] Step S12: sampling the hardware device through the control system to obtain a first voltage signal.

[0038] Optionally, see Figure 6 , Figure 6 6 is a schematic diagram of the structure of an embodiment of the control system of the present application. The hardware device 60 may include a resistor 601 and a capacitor 602 connected in series, a first port 611 of the control system 61 is grounded through the resistor 601 and the capacitor 602, a second port 612 of the control system 61 is connected between the capacitor 602 and the resistor 601, and the hardware device 60 is sampled through the second port 612 of the control system 61 to obtain a first voltage signal.

[0039] Optionally, see Figure 7The hardware device 60 may include a first resistor 603 and a second resistor 604. The control system 61 is connected between the first resistor 603 and the second resistor 604 through an analog to digital converter 613 (ADC). One end of the first resistor 603 receives a reference voltage, and one end of the second resistor 604 is grounded. One end of the analog to digital converter 613 samples the voltage signal between the two resistors to obtain a first voltage signal.

[0040] Therefore, the hardware device 60 is sampled by the control system 61 to obtain a first voltage signal. In some embodiments, the first voltage signal may be a sampling value of a voltage signal between resistors in the hardware device 60. In other embodiments, the capacitor 602 in the hardware device 60 may be charged by the control system 61, and the first voltage signal is a change value of a voltage signal on one side of the capacitor 602.

[0041] Step S13: Identify the model of the hardware device based on the first voltage signal.

[0042] In some embodiments, the model of the hardware device may be identified based on the voltage signal sampling value; in other embodiments, the model of the hardware device may be identified based on the charging time of the capacitor in the hardware device.

[0043] In the present application, the control system samples the hardware device through the control system to obtain a first voltage signal, and identifies the model of the hardware device based on the first voltage signal. There is no need to increase the upper limit of the number of hardware devices recognized through GPIO expansion, which greatly reduces costs.

[0044] See also Figure 2 and Figure 6 As shown, Figure 2 yes Figure 1 Schematic diagram of a flow chart of an embodiment of step S12 in FIG. Step S12 includes the following steps:

[0045] Step S21: outputting a second voltage signal through the first port of the control system, where the second voltage signal is used to charge the capacitor.

[0046] The first port 611 of the control system 61 is grounded through the resistor 601 and the capacitor 602, and the second port 612 of the control system 61 is connected between the capacitor 602 and the resistor 601. The second voltage signal is output through the first port 611 of the control system 61, that is, the first port 611 of the control system 61 provides the second voltage signal to the resistor 601.

[0047] The second voltage signal may be a power supply voltage, and the control system 61 may include a microcontroller unit (MCU). As described above, the second voltage signal is output through the first port 611 of the control system 61. In this embodiment, the power supply voltage may be output through a GPIO (General-purpose input / output) interface of the microcontroller unit to charge the capacitor 602.

[0048] Among them, the microcontroller unit integrates the central processing unit, memory, microsecond timer, etc. on a single chip to form a chip-level computer, which can be used as the central control unit of the control system 61. GPIO is some pins of the MCU. When the GPIO is used as an output port, it can output voltage; when the GPIO is used as an input port, it can read high and low levels.

[0049] When the control system 61 is running, it will determine whether the hardware device 60 is connected to the control system 61. In response to the hardware device 60 not being connected to the control system 61, the control system 61 continues to run and repeatedly determines whether the hardware device 60 is connected to the control system 61; in response to the hardware device 60 being connected to the control system 61, a second voltage signal is output through the first port 611 of the control system 61, and the second voltage signal is used to charge the capacitor 602.

[0050] Step S22: when the first port outputs the second voltage signal, counting the charging time of the capacitor through the control system.

[0051] In response to the connection between the hardware device 60 and the control system 61, the first port 611 of the control system 61 outputs a second voltage signal for charging the capacitor 602; the second port 612 of the control system 61 receives the first voltage signal, and counts the charging time of the capacitor 602 through the control system 61. The first voltage signal is the change value of the voltage signal on one side of the capacitor 602 during the charging process.

[0052] Optionally, the charging time may be recorded based on a microsecond timer of a microcontroller unit (MCU) in the control system 61, or a dedicated timer may be provided for timing.

[0053] See also Figure 3 , Figure 3 yes Figure 1 Schematic diagram of a flow chart of an embodiment of step S13 in FIG. Step S13 includes the following steps:

[0054] Step S31: acquiring a first voltage signal through a second port of the control system.

[0055] The initial voltage value of the capacitor 602 may be 0V or any voltage value, which is not limited in the present application.

[0056] Step S32: in response to the first voltage signal being at a high level, stopping counting the charging time of the capacitor to obtain the charging time.

[0057] The high level is the voltage signal on one side of the capacitor 602 after the capacitor 602 is fully charged. In some embodiments, the control system 61 obtains the first voltage signal of the second port 612, and determines whether the voltage signal of the second port 612 meets the high level based on the first voltage signal of the second port 612. In response to the voltage signal of the second port 612 meeting the high level, the control system 61 controls the timer to stop timing, and calculates the timer recording time.

[0058] Specifically, when the second port 612 of the control system 61 receives the initial value of the first voltage signal, it starts the microsecond timer to start timing and continuously judges the state of the first voltage signal. When the first voltage signal is at a high level, it stops timing. The start timing time can be set to T0, and the stop timing time can be set to T1. Then the charging time T can be calculated by the following formula:

[0059] T=T1–T0.

[0060] Step S33: Identify the type of the hardware device based on the charging time.

[0061] In some embodiments, the theoretical charging time of different types of hardware devices 60 may be recorded. The control system 61 compares the charging time with the theoretical charging time of different types of hardware devices 60 to identify the type of the hardware device 60 .

[0062] Specifically, the theoretical charging time of multiple hardware devices 60 can be obtained; based on the theoretical charging time and the microsecond timer recording time, a first error is calculated; it is determined whether the first error is less than a preset error; in response to the first error being less than the preset error, the hardware device 60 is identified as the hardware device 60 corresponding to the theoretical charging time.

[0063] See also Figure 4 , Figure 4 yes Figure 3 Schematic diagram of a flow chart of an embodiment of step S33 in FIG. Step S33 includes the following steps:

[0064] Step S41: Calculate the theoretical charging time of the capacitor in the hardware device.

[0065] When calculating the theoretical charging time, it is necessary to obtain the resistance value of the resistor 601, the capacity value of the capacitor 602, the power supply voltage value, the initial voltage value of the capacitor 602, and the final voltage value of the capacitor 602 in the fully charged state in the hardware device 60.

[0066] The resistance of the resistor 601 in the hardware device 60 is R, the capacitance of the capacitor 602 is C, the power supply voltage is V1, the initial voltage value of the capacitor 602 is V0, and the final voltage value of the capacitor 602 is Vt. The theoretical time Tc can be calculated by the theoretical charging time formula:

[0067] Tc=R*C*Ln[(V1-V0) / (V1-Vt)].

[0068] Step S42: Compare the charging time with the theoretical charging time to identify the type of the hardware device.

[0069] In some embodiments, the control system 61 can calculate the corresponding theoretical charging time based on relevant parameters of the hardware device 60. For example, the hardware device 60 includes a first hardware device and a second hardware device, wherein the resistance value of the resistor 601 in the first hardware device 60, the capacitance of the capacitor 602, the initial voltage of the capacitor 602 and the voltage signal after the capacitor 602 is fully charged are obtained, and the theoretical charging time corresponding to the first hardware device 60 is calculated by the above-mentioned theoretical charging time formula.

[0070] Similarly, the resistance value of the resistor 601 in the second hardware device 60, the capacitance of the capacitor 602, the initial voltage of the capacitor 602, and the voltage of the capacitor 602 after being fully charged are obtained, and the theoretical charging time corresponding to the second hardware device 60 is calculated by the above-mentioned theoretical charging time formula. It should be noted that the specifications of the resistor 601 and the capacitor 602 in different hardware devices 60 are different, and the corresponding actual parameter accuracy is also different. In actual applications, it is necessary to debug the theoretical charging time according to the accuracy values ​​of the resistor 601 and the capacitor 602 in the hardware device 60, combined with the actual measured resistance value and capacitance.

[0071] It should be noted that, in the present application, the number of hardware devices 60 is not limited, and “first” and “second” are merely exemplary.

[0072] After obtaining the theoretical charging time of multiple hardware devices 60, a first error is calculated based on the theoretical charging time and the microsecond timer recording time, and it is determined whether the first error is less than a preset error. In response to the first error being less than the preset error, the hardware device 60 is identified as the hardware device 60 corresponding to the theoretical charging time.

[0073] See also Figure 5 and Figure 7 As shown, Figure 5 yes Figure 1 Schematic diagram of another embodiment of step S12 in FIG. 1 . Step S12 also includes the following steps:

[0074] Step S51: collecting the voltage between the first resistor and the second resistor through the control system to obtain a first voltage signal.

[0075] The control system 61 is connected between the first resistor 603 and the second resistor 604 via an analog to digital converter (ADC) 613 , and one end of the analog to digital converter 613 samples the voltage signal between the two resistors to obtain a first voltage signal.

[0076] The analog-to-digital converter 613 is an electronic component that converts a voltage signal into a digital signal.

[0077] Step S52: converting the first voltage signal into a digital signal through an analog-to-digital converter.

[0078] In some embodiments, the control system 61 may sample the hardware device 60 through the analog-to-digital converter 613. The first voltage signal is converted into a digital signal through the analog-to-digital converter 613. The control system 61 identifies the model of the hardware device 60 based on the digital signal.

[0079] See also Figure 6 , Figure 6 The hardware device 60 includes a resistor 601 and a capacitor 602 , a first port 611 of the control system 61 is grounded through the resistor 601 and the capacitor 602 , and a second port 612 of the control system 61 is connected between the capacitor 602 and the resistor 601 .

[0080] See also Figure 7 , Figure 7 6 is a schematic diagram of the structure of another embodiment of the control system of the present application. The hardware device 60 includes a first resistor 603 and a second resistor 604, and the control system 61 includes an analog-to-digital converter 613. The control system 61 is connected between the first resistor 603 and the second resistor 604 through the analog-to-digital converter 613. One end of the first resistor 603 receives a reference voltage, and one end of the second resistor 604 is grounded.

[0081] See also Figure 8 , Figure 8 The non-volatile computer-readable storage medium 80 stores program instructions 801 that can be executed by the control system, and the program instructions 801 are used to implement the steps of any of the above-mentioned hardware device identification method embodiments.

[0082] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0083] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0084] In the several embodiments provided in the present application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0086] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of each implementation method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

Claims

1. A method for identifying a hardware device, characterized in that: Applied to a control system, the hardware device includes a resistor and a capacitor, a first port of the control system is grounded through the resistor and the capacitor, and a second port of the control system is connected between the capacitor and the resistor; The identification method comprises: In response to the hardware device being connected to the control system, sampling the hardware device through the control system to obtain a first voltage signal; The model of the hardware device is identified based on the first voltage signal.

2. The identification method according to claim 1, characterized in that: The identification method further comprises: In response to the hardware device being connected to the control system, outputting a second voltage signal through the first port of the control system, wherein the second voltage signal is used to charge the capacitor; When the first port outputs the second voltage signal, the charging time of the capacitor is counted by the control system.

3. The identification method according to claim 2, characterized in that: The step of identifying the model of the hardware device based on the first voltage signal comprises: Acquiring the first voltage signal through a second port of the control system; A type of the hardware device is identified based on the charging time.

4. The identification method according to claim 3, characterized in that: After the step of acquiring the first voltage signal through the second port of the control system, the identification method further includes: In response to the first voltage signal being at a high level, counting the charging time of the capacitor is stopped to obtain the charging time.

5. The identification method according to claim 3 or 4, characterized in that: The step of identifying the type of the hardware device based on the charging time of the capacitor includes: Calculating the theoretical charging time of the capacitor in the hardware device; The charging time is compared with the theoretical charging time to identify the type of the hardware device.

6. The identification method according to claim 5, characterized in that: The step of comparing the charging time with the theoretical charging time to identify the type of the hardware device includes: Based on the charging time and the theoretical charging time, a first error is calculated; Determining whether the first error is less than a preset error; In response to the first error being smaller than a preset error, the hardware device is identified as a hardware device corresponding to the capacitor charging time.

7. The identification method according to claim 1, characterized in that: The identification method further comprises: Determining whether the control system is connected to the hardware device; In response to the control system not being connected to the hardware device, the process returns to the step of determining whether the control system is connected to the hardware device.

8. A control system, characterized in that: The control system is connected to the hardware device, and the control system is used to sample the hardware device to obtain a first voltage signal, and identify the model of the hardware device based on the first voltage signal.

9. The control system according to claim 8, characterized in that: The hardware device comprises a resistor and a capacitor, a first port of the control system is grounded through the resistor and the capacitor, and a second port of the control system is connected between the capacitor and the resistor.

10. A non-volatile computer-readable storage medium having program instructions stored thereon, characterized in that: When the program instructions are executed by the control system, the method for identifying the hardware device according to any one of claims 1 to 7 is implemented.

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