Digital LDO circuit suitable for large voltage difference and voltage stabilizing method thereof

Abstract

The invention discloses a digital LDO circuit suitable for large voltage difference and a voltage stabilizing method of the digital LDO circuit, and aims to solve the problems that the large voltage difference cannot be achieved through the switching characteristic of a power tube of an existing digital LDO, and the application scene that a large SoC needs low power supply voltage cannot be met, the digital LDO circuit comprises a mode control circuit, a coarse adjustment loop and a fine adjustment loop, each of the coarse adjustment loop and the fine adjustment loop comprises an advance and retreat method controller, a decoder, a grid voltage control module and a PMOS (P-channel Metal Oxide Semiconductor) array, the advance and retreat method controller outputs a signal for indicating the closing number of the PMOS array according to the state of the output voltage, and the signal outputs a PMOS bit control signal to the grid voltage control module through the decoder; the grid voltage control module reduces reference voltage by means of resistance voltage division to serve as a digital ground end of the buffer array, so that logic 0 voltage of a PMOS bit control signal from the decoder is increased, the PMOS array is connected according to bits, grid voltage of the opened PMOS is increased, and grid source voltage is reduced to compensate for increase of voltage difference.

Description

Technical Field

[0001] The invention belongs to the technical field of digital LDO, and in particular relates to a digital LDO circuit suitable for large voltage difference and a voltage stabilization method thereof. Background Art

[0002] The voltage difference of common digital LDOs is relatively small, usually between 50mV and 200mV. When the voltage difference increases to around 400mV, the ripple of the digital LDO is too large and the output accuracy will be reduced.

[0003] Due to the low operating voltage, low static power consumption, and fast response characteristics of digital LDO, it is widely used in wearable devices and other on-chip systems, effectively improving battery life. Traditional digital LDO uses the switching characteristics of the power tube array to greatly improve the response speed and current efficiency of the LDO. However, its switching characteristics also limit the gate-source voltage Vgs of the turned-on power tube to the power supply voltage. As a result, under large voltage differences (Dropout Voltage, VDO), the current provided by the unit power tube increases, the output accuracy decreases, and the limit cycle oscillation (Limit Cycle Oscillation, LCO) ripple is too large in steady state, which cannot meet the application scenarios where large SoCs require stable low power supply voltages.

[0004] The existing technology usually further increases the control loop of the digital LDO to achieve low-medium-high multi-precision control and further reduce the steady-state ripple under large voltage difference. However, increasing the control loop will make the control loop of the digital LDO more complicated, and the power consumption and settling time will be longer. At the same time, to achieve high precision under large voltage difference, the required power tube has a very small width-to-length ratio, resulting in a relatively large length and a corresponding increase in area.

[0005] Alternatively, in a hybrid LDO architecture, an analog LDO is added as a small current analog auxiliary circuit. The negative feedback loop of the analog LDO can adaptively adjust the Vgs of the power tube to adapt to the increase in VDO, so that the power tube works in the saturation region, thereby achieving low ripple under a large voltage difference. However, this analog LDO requires customized stability adjustment for different indicator requirements and process nodes, and cannot quickly generate design and process migration. In addition, adding an analog loop will increase the area and power consumption, reducing the efficiency of the LDO. Summary of the invention

[0006] The purpose of the present invention is to provide a digital LDO circuit suitable for large voltage difference, which can compensate for the increase of voltage difference by reducing the gate-source voltage, so as to solve the problem of large LCO ripple of digital LDO under large voltage difference.

[0007] To solve the above problems, the technical solution of the present invention is:

[0008] A digital LDO circuit suitable for large voltage difference, comprising: a mode control circuit, a coarse adjustment loop and a fine adjustment loop;

[0009] The mode control circuit is used to control the digital LDO to enter a coarse adjustment loop or a fine adjustment loop;

[0010] At least one of the coarse adjustment loop and / or the fine adjustment loop includes a coarse adjustment / fine adjustment advance / retreat controller, a first / second decoder, a first / second gate voltage control module and a PMOS switch array;

[0011] The coarse / fine adjustment advance / retreat controller is used to detect the state of the output voltage of the digital LDO, and output a signal indicating the number of closed states of the corresponding PMOS switch array, and the signal outputs a PMOS bit control signal to the first / second gate voltage control module of the adaptation through the first / second decoder of the adaptation;

[0012] The first / second gate voltage control module is configured to use resistor voltage division to step down the reference voltage as the digital ground of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the adapted decoder, and to access the adapted PMOS switch array bit by bit to raise the gate voltage that turns on the adapted PMOS switch and reduce the gate-source voltage to compensate for the increase in the voltage difference.

[0013] According to an embodiment of the present invention, the mode control circuit includes a dynamic comparator, an undershoot detection circuit and a mode detector;

[0014] The negative phase terminal of the dynamic comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO through a resistor, and the output terminal is connected to the first input terminal of the mode detector;

[0015] The input end of the undershoot detection circuit is connected to the output voltage of the digital LDO, and the output end thereof is connected to the second input end of the mode detector;

[0016] The output end of the mode detector is connected to the coarse adjustment loop and the fine adjustment loop, and is used to control the digital LDO to enter the coarse adjustment loop or the fine adjustment loop.

[0017] According to one embodiment of the present invention, the output end of the dynamic comparator is also connected to the input end of the coarse-adjustment advance and retreat method controller, and the coarse-adjustment advance and retreat method controller is further configured to determine whether to change the step size of controlling the number of large-size PMOS arrays based on the output signal of the dynamic comparator in multiple consecutive clock cycles.

[0018] According to an embodiment of the present invention, the mode detector is configured to: detect the output voltage of the digital LDO in real time and adjust it; when the load current changes, the output voltage changes accordingly, causing the output voltage to leave the fine loop stable state, and at this time the mode detector controls the digital LDO to maintain the fine adjustment loop, that is, the fine adjustment advance and retreat method adjustment;

[0019] When the output voltage change is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the fine loop bits are exhausted, indicating that the fine loop has entered a stable oscillation state, and the fine loop is kept adjusted slowly without enabling the coarse loop.

[0020] When the output voltage change is greater than the maximum adjustment range of the fine loop, the output voltage cannot be adjusted to a stable oscillation state of the fine loop even if the fine loop adjustment bits are exhausted, so the digital LDO is controlled to enter the coarse adjustment loop, that is, the coarse adjustment advance and retreat method adjustment;

[0021] In the coarse-tuning loop, when the output voltage oscillates above and below the reference voltage for m clock cycles continuously, it indicates that the coarse-tuning loop has entered a stable oscillation state, and the digital LDO is controlled to enter a fine-tuning loop.

[0022] According to one embodiment of the present invention, the mode control circuit is configured as follows: when the mode detector detects that the load current jumps upward by more than 10 times, the undershoot detection circuit outputs 1, directly turns on half of the thick-ring large-size PMOS, and provides current to prevent the undershoot voltage from being too large.

[0023] According to an embodiment of the present invention, the first gate voltage control module includes a buffer array, a first resistor, and a second resistor;

[0024] The input end of the buffer array is connected to the output end of the first decoder, and the output end of the buffer array is connected to the gate of the large-size PMOS array;

[0025] The source end of the buffer array is connected to the input voltage of the digital LDO, and the ground end of the buffer array is connected to the feedback voltage obtained by dividing the reference voltage through the first resistor and the second resistor.

[0026] According to an embodiment of the present invention, the coarse-adjustment advance-retreat controller is configured to: detect the output signal of the dynamic comparator in the mode control circuit in real time, and when the dynamic comparator outputs 0, the coarse-adjustment advance-retreat controller outputs a coarse-loop PMOS shutdown quantity that decreases by a step length x;

[0027] When the output state of the dynamic comparator does not change for n consecutive clock cycles, the coarse-loop PMOS shutdown quantity is increased to a decreasing step size of y, and the adjustment is continued until the output of the dynamic comparator is flipped, and the coarse-loop PMOS shutdown quantity is changed to an increasing step size, and the increasing step size is updated to the minimum step size x.

[0028] According to an embodiment of the present invention, the fine adjustment loop includes a fine adjustment advance and retreat method controller, a second decoder, a second gate voltage control module and a small-size PMOS array connected in sequence;

[0029] The fine-tuning advance and retreat controller outputs a signal indicating the number of small-size PMOS arrays that are turned off according to the state of the output voltage of the digital LDO, and the signal outputs a PMOS bit control signal to the second gate voltage control module through the second decoder; the second gate voltage control module uses resistor voltage division to reduce the reference voltage as the digital ground terminal of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the decoder, and accesses the small-size PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increase in the voltage difference.

[0030] A voltage stabilization method suitable for a digital LDO circuit with a large voltage difference, comprising:

[0031] Before each load change, the digital LDO is initially in a thin-loop stable state;

[0032] When the output voltage of the digital LDO deviates from the stable state of the fine loop due to load changes, the mode detector controls the digital LDO to maintain the fine adjustment loop; if the current output voltage VOUT < the reference voltage VREF, the dynamic comparator outputs a signal Comp_out = 0, and controls the output fine loop PMOS closure number of the fine adjustment advance and retreat controller to decrease by a step length x; through the second decoder and the corresponding second gate voltage control module, the corresponding PMOS array is controlled to open one more, and the fine loop slow adjustment is performed;

[0033] If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction does not change, the fine loop fast adjustment mode is entered, and the decreasing step length of the number of fine loop PMOS shutdowns is increased to y, and the adjustment is continued until Comp_out is flipped. The control direction of the fine adjustment advance and retreat controller is correspondingly changed to add, and the adding step length is updated to the minimum step length x. Until Comp_out does not change for n consecutive clock cycles, the adding step length is increased to y, and the fine loop fast adjustment is performed;

[0034] If the output voltage change of the digital LDO is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the number of bits of the fine adjustment loop is exhausted, indicating that the fine loop has entered a stable oscillation state and the fine loop is maintained at a slow adjustment speed without enabling the coarse adjustment loop.

[0035] According to an embodiment of the present invention, the output voltage of the digital LDO deviates from the fine loop stable state due to load change, and the mode detector initially controls the digital LDO to enter the fine adjustment loop; when the change amount is greater than the maximum adjustment range of the fine loop, the output voltage cannot be adjusted to the fine loop stable oscillation state even if the fine loop adjustment bits are exhausted, so the fine loop PMOS shutdown number is reset to a, and the mode detector controls the digital LDO to enter the coarse adjustment loop;

[0036] In the coarse adjustment loop, if the current output voltage VOUT < the reference voltage VREF, the dynamic comparator output signal Comp_out = 0, and the output coarse loop PMOS closing quantity of the coarse adjustment advance and retreat controller is controlled to decrease by the step length x; through the first decoder and the corresponding first gate voltage control module, the corresponding PMOS array is controlled to open one more, and the coarse loop slow adjustment is performed;

[0037] If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction does not change, the decreasing step length of the coarse loop PMOS shutdown quantity is increased to y, and the adjustment is continued until Comp_out is reversed. The control direction of the coarse adjustment advance and retreat controller is correspondingly changed to add, and the add step length is updated to the minimum step length x. Until Comp_out does not change for n consecutive clock cycles, the add step length is increased to y, and the coarse loop fast adjustment is entered;

[0038] When the mode detector detects that the output voltage oscillates above and below the reference voltage for m clock cycles continuously, it indicates that it has entered the coarse loop stable oscillation state, and the digital LDO is controlled to enter the fine loop;

[0039] When entering the fine-tuning loop, the number of PMOS closures in the coarse loop is taken as the larger value of the number of PMOS closures that jump during the stable oscillation of the coarse loop, to ensure that when entering the fine-loop adjustment circuit again, the number of PMOS tube closures is reduced; since the number of PMOS closures in the fine loop is initialized to a, there is enough space to ensure that the fine loop adjustment enters a steady state to ensure low ripple.

[0040] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0041] A digital LDO circuit suitable for large voltage difference in one embodiment of the present invention aims at the problem that the switching characteristics of the power tube of the existing digital LDO cannot achieve a large voltage difference and cannot meet the application scenario where a large SoC requires a low power supply voltage. The gate-source voltage is reduced to compensate for the increase in the voltage difference, so as to solve the problem that the digital LDO has a large LCO ripple under a large voltage difference. The digital LDO circuit includes a mode control circuit, a coarse adjustment loop and a fine adjustment loop, wherein the coarse adjustment loop and the fine adjustment loop both include an advance-retreat method controller, a decoder, a gate voltage control module and a PMOS array. The advance-retreat method controller outputs a signal indicating the number of PMOS array closures according to the state of the output voltage, and the signal outputs a PMOS bit control signal to the gate voltage control module through the decoder; the gate voltage control module uses a resistor voltage divider to reduce the reference voltage as the digital ground terminal of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the decoder, and accesses the PMOS array bit by bit to raise the gate voltage of the turned-on PMOS, and reduce the gate-source voltage to compensate for the increase in the voltage difference.

[0042] In addition, since the number of closed thin-ring tubes is initialized to a large value, there is enough space to ensure that the thin-ring regulation enters a steady state to ensure low ripple. At the same time, since the gate voltage control module raises the gate voltage of the turned-on large-size PMOS array, the corresponding drain-source current is reduced, the regulation accuracy of the unit power tube is increased, and the coarse and thin ring ripples under large VOD pressure difference are effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A digital LDO circuit diagram suitable for large voltage difference in one embodiment of the present invention;

[0044] Figure 2 The figure is a voltage regulation control flow chart of a digital LDO circuit suitable for a large voltage difference in one embodiment of the present invention. DETAILED DESCRIPTION

[0045] The following is a further detailed description of a digital LDO circuit suitable for large voltage difference and a voltage stabilization method thereof proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0046] This embodiment provides a digital LDO circuit suitable for large voltage difference, where the large voltage difference is a voltage between 200mV and VIN / 2, where VIN is the source voltage of the PMOS array. The increase in voltage difference is compensated by reducing the gate-source voltage, so as to solve the problem of large LCO ripple under large voltage difference of digital LDO.

[0047] The digital LDO circuit suitable for large voltage difference includes: a mode control circuit, a coarse adjustment loop and a fine adjustment loop; wherein the mode control circuit is used to control the digital LDO to enter the coarse adjustment loop or the fine adjustment loop; at least one loop of the coarse adjustment loop and / or the fine adjustment loop includes a coarse adjustment / fine adjustment advance and retreat controller, a first / second decoder, a first / second gate voltage control module and a PMOS switch array. The coarse adjustment / fine adjustment advance and retreat controller is used to detect the state of the output voltage of the digital LDO, output a signal indicating the number of closures of the corresponding PMOS switch array, and the signal outputs a PMOS bit control signal to the adapted first / second gate voltage control module through the adapted first / second decoder. The coarse adjustment loop and / or the fine adjustment loop here means that sometimes the adjustment of the output voltage of the digital LDO needs to be completed by the coarse adjustment loop and the fine adjustment loop together, and sometimes only one of the coarse adjustment loop or the fine adjustment loop is needed, depending on the actual situation.

[0048] The first / second gate voltage control module is configured to use resistor voltage division to step down the reference voltage as the digital ground of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the adapted decoder, and to access the adapted PMOS switch array bit by bit to raise the gate voltage that turns on the adapted PMOS switch and reduce the gate-source voltage to compensate for the increase in the voltage difference.

[0049] For details, please see Figure 1 The mode control circuit of the digital LDO circuit includes a dynamic comparator, a mode detector, and an undershoot detection circuit. The dynamic comparator is controlled by a clock signal CLK. The negative phase terminal of the dynamic comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO through a resistor, and the output terminal of the dynamic comparator is connected to the first input terminal of the mode detector. The input terminal of the undershoot detection circuit is connected to the output voltage of the digital LDO, and the output terminal of the undershoot detection circuit is connected to the second input terminal of the mode detector; the output terminal of the mode detector is connected to a coarse adjustment loop and a fine adjustment loop to control the digital LDO to enter the coarse adjustment loop or the fine adjustment loop.

[0050] The output of the dynamic comparator is also connected to the input of the coarse-adjustment advance-retreat controller, which is further configured to determine whether to change the step size for controlling the number of large-size PMOS arrays based on the output signal of the dynamic comparator in multiple consecutive clock cycles.

[0051] The mode detector detects the output voltage of the digital LDO in real time and adjusts it; when the load current changes, the output voltage changes accordingly, causing the output voltage to leave the fine loop stable state. At this time, the mode detector controls the digital LDO to maintain the fine adjustment loop, that is, the fine adjustment advance and retreat method adjustment. When the change in the output voltage is less than the maximum adjustment range of the fine loop, before the number of bits in the fine adjustment loop is exhausted, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles, indicating that it has entered the fine loop stable oscillation state, and the fine loop slow adjustment is maintained without enabling the coarse adjustment loop. When the change in the output voltage is greater than the maximum adjustment range of the fine loop, even if the number of bits in the fine loop adjustment is exhausted, the output voltage cannot be adjusted to the fine loop stable oscillation state, so the digital LDO is controlled to enter the coarse adjustment loop, that is, the coarse adjustment advance and retreat method adjustment. In the coarse adjustment loop, when the output voltage oscillates continuously above and below the reference voltage for m clock cycles, it indicates that it has entered the coarse loop stable oscillation state, and the digital LDO is controlled to enter the fine adjustment loop.

[0052] Furthermore, when the mode detector detects that the load current jumps upward by more than 10 times, the undershoot detection circuit outputs 1, directly turning on half of the thick-ring large-size PMOS to provide current to prevent the undershoot voltage from being too large.

[0053] The coarse adjustment loop is used to quickly adjust the output voltage of the digital LDO so that the output voltage is in a stable state. The coarse adjustment loop includes a coarse adjustment advance and retreat method controller, a first decoder, a first gate voltage control module and a large-size PMOS array connected in sequence, wherein the coarse adjustment advance and retreat method controller outputs a signal indicating the number of PMOS array shutdowns according to the state of the output voltage, and the signal outputs a PMOS bit control signal to the first gate voltage control module through the first decoder; the first gate voltage control module uses a resistor voltage divider to reduce the reference voltage as the digital ground of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the decoder, and is connected to the large-size PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increase in the voltage difference.

[0054] Among them, the coarse-adjustment advance and retreat method controller detects the output signal of the dynamic comparator in the mode control circuit in real time. When the dynamic comparator outputs 0, the coarse-adjustment advance and retreat method controller outputs the coarse-loop PMOS shutdown quantity decreasing by step x; when the output state of the dynamic comparator has not changed for n consecutive clock cycles, the coarse-loop PMOS shutdown quantity decreasing step is increased to y, and the adjustment is continued until the output of the dynamic comparator is flipped, and the coarse-loop PMOS shutdown quantity is changed to increasing, and the increasing step is updated to the minimum step x.

[0055] The first gate voltage control module comprises a buffer array, a first resistor (R3), and a second resistor (R4); the input end of the buffer array is connected to the output end of the first decoder, and the output end of the buffer array is connected to the gate of the large-size PMOS array; the source end of the buffer array is connected to the input voltage of the digital LDO, and the ground end of the buffer array is connected to the feedback voltage obtained by dividing the reference voltage by the first resistor and the second resistor.

[0056] The fine-tuning loop is used to reduce the LCO ripple of the digital LDO under a large voltage difference. The fine-tuning loop includes a fine-tuning advance and retreat method controller, a second decoder, a second gate voltage control module and a small-size PMOS array connected in sequence, wherein the fine-tuning advance and retreat method controller outputs a signal indicating the number of PMOS array shutdowns according to the state of the output voltage, and the signal outputs a PMOS bit control signal to the second gate voltage control module through the second decoder; the second gate voltage control module uses a resistor voltage divider to reduce the reference voltage as the digital ground of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the decoder, and accesses the small-size PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increase in the voltage difference.

[0057] As mentioned above, both the coarse adjustment loop and the fine adjustment loop include an advance-retract controller, a decoder, a gate voltage control module and a PMOS array. The difference is that the coarse adjustment loop corresponds to a 2^M bit large-sized proportional PMOS array; the fine adjustment loop corresponds to a 2^N bit small-sized proportional PMOS array.

[0058] When the output voltage of the above digital LDO changes due to load changes, the following methods can be used to stabilize the output voltage:

[0059] Specifically, when the mode detector detects a change in the output voltage state, it outputs a steady-state Mode signal to control the DLDO to enter the coarse-tuning or fine-tuning loop. In the coarse-tuning or fine-tuning loop, the coarse-tuning / fine-tuning stepwise controller detects the output voltage state and outputs M or N bit signals to indicate the number of PMOS arrays to be turned off. After passing through the adapted first / second decoder, 2^M or 2^N bit PMOS bit control signals are output. The first / second gate voltage control module uses resistor voltage division to step down the reference voltage as the digital ground terminal of the buffer array, so as to raise the logic 0 voltage of the bit control signal from the decoder, and access the PMOS array bit by bit to raise the gate voltage of the turned-on PMOS, reducing Vgs to compensate for the increase in the voltage difference VDO. When the mode detector detects that the output voltage oscillates continuously around the reference voltage for m clock cycles, the fine-tuning loop is enabled for precise adjustment. Only when the fine-tuning stepwise controller detects that the output of the comparator has not changed for n consecutive clock cycles, will the step size for controlling the number of PMOS arrays be increased from x to y, so as to avoid misjudgment caused by logic delay.

[0060] For the voltage regulation control process of the above digital LDO circuit, please refer to Figure 2 . Before each load change occurs, the DLDO is initially in the fine-loop stable state.

[0061] When the load current changes, the output voltage changes accordingly, causing the output voltage to deviate from the fine-loop stable state. At this time, the mode detector controls the digital LDO to maintain the fine-tuning loop, that is, the fine-tuning stepwise adjustment.

[0062] In the fine-tuning loop, if VOUT < VREF at this time, the dynamic comparator outputs '0', and the Comp_out signal controls the output signal (the number of PMOS arrays turned off) Ctrl_F of the fine-tuning stepwise controller to decrease by one step at a time. Through the second decoder and the corresponding second gate voltage control module, one more small-size PMOS array is turned on for slow fine-loop adjustment. If VOUT is still less than VREF, this process is repeated in the next clock cycle. If the output state of the dynamic comparator does not change for 8 consecutive clock cycles, indicating that the adjustment direction has not changed, then the fine-loop fast adjustment mode is entered, and the decreasing step size of Ctrl_F is increased to 4. Continue to adjust until Comp_out flips, and the control direction of the stepwise method changes to addition, and the addition step size also returns to the minimum step size 1 until Comp_out has no change for 8 consecutive clock cycles and the addition step size is increased to 4. When the mode detector detects that the output voltage oscillates continuously around the reference voltage for 3 clock cycles, it indicates that the fine-loop stable oscillation state has been entered, and Mode outputs '1' to maintain the slow fine-loop adjustment.

[0063] If the output voltage change of the digital LDO is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for 3 clock cycles before the number of bits of the fine adjustment loop is exhausted, indicating that the fine loop has entered a stable oscillation state and the fine loop is maintained at a slow adjustment speed without enabling the coarse adjustment loop.

[0064] The maximum adjustment range of the thin ring here can be obtained according to the following formula:

[0065]

[0066] Among them, V DS Refers to the maximum adjustment range of the fine ring output voltage, I DM Refers to the load current carried by all PMOS in the thin ring array when they are fully turned on. 2^M refers to the number of PMOS in the thin ring array, and W / L refers to the size of the thin ring array. Other values ​​are constants. This formula is derived from PMOS working in the linear region.

[0067] In addition, the maximum adjustment range of the thin loop will change due to many variables. When the thin loop is not enough to pull the output voltage back to the stable state of the thin loop, the coarse loop will be turned on.

[0068] When the VOUT variation exceeds the maximum adjustment range of the fine loop, even if the fine loop adjustment bits are exhausted, the output voltage cannot be adjusted to enter the stable oscillation state of the fine loop, so the number of fine loop PMOS shutdowns is reset to 24, and the mode detector controls DLDO to enter the coarse adjustment loop. In the coarse adjustment loop, the same advance and retreat method as the fine adjustment loop is used for adjustment. When the mode detector detects that the output voltage is stable and oscillating, it re-enters the above-mentioned fine adjustment loop. At this time, the coarse loop PMOS array shutdown number Ctrl_C is determined to be a larger value to ensure that the fine loop adjustment is entered again in the form of reducing the number of tube shutdowns. The larger value means that when the coarse loop is in stable oscillation, there will be several values ​​jumping back and forth, and the larger value is taken. For example, if the jump back and forth is 23->24->23->24, then 24 is taken. In addition, since the number of fine loop tube shutdowns is initialized to 24, there is enough space to ensure that the fine loop adjustment enters a steady state to ensure low ripple.

[0069] When the mode detector detects that the load current jumps upward by more than 10 times, such as jumping from 10uA to 100uA, the undershoot detection circuit outputs '1', directly turning on half of the thick ring large-size PMOS, providing current to prevent large undershoot voltage. At the same time, because the gate voltage control module raises the gate voltage of the turned-on large-size PMOS array, the corresponding drain-source current is reduced, the regulation accuracy of the unit power tube is increased, and the ripple of the thick ring and thin ring under large voltage difference is reduced.

[0070] The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the protection scope of the present invention.

Claims

1. A digital LDO circuit suitable for large voltage difference, characterized in that: include: Mode control circuit, coarse adjustment loop and fine adjustment loop; The mode control circuit is used to control the digital LDO to enter a coarse adjustment loop or a fine adjustment loop; At least one of the coarse adjustment loop and / or the fine adjustment loop comprises a coarse adjustment / fine adjustment advance / retreat controller, a first / second decoder, a first / second gate voltage control module and a PMOS switch array; The coarse / fine adjustment advance / retreat controller is used to detect the state of the output voltage of the digital LDO, and output a signal indicating the number of closed states of the corresponding PMOS switch array, and the signal outputs a PMOS bit control signal to the first / second gate voltage control module of the adaptation through the first / second decoder of the adaptation; The first / second gate voltage control module is configured to use resistor voltage division to step down the reference voltage as the digital ground of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the adapted decoder, and to access the adapted PMOS switch array bit by bit to raise the gate voltage that turns on the adapted PMOS switch and reduce the gate-source voltage to compensate for the increase in the voltage difference.

2. The digital LDO circuit suitable for large voltage difference according to claim 1, characterized in that: The mode control circuit includes a dynamic comparator, an undershoot detection circuit and a mode detector; The negative phase terminal of the dynamic comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO through a resistor, and the output terminal is connected to the first input terminal of the mode detector; The input end of the undershoot detection circuit is connected to the output voltage of the digital LDO, and the output end thereof is connected to the second input end of the mode detector; The output end of the mode detector is connected to the coarse adjustment loop and the fine adjustment loop, and is used to control the digital LDO to enter the coarse adjustment loop or the fine adjustment loop.

3. The digital LDO circuit suitable for large voltage difference as claimed in claim 2, characterized in that: The output end of the dynamic comparator is also connected to the input end of the coarse-adjustment advance and retreat controller, and the coarse-adjustment advance and retreat controller is further configured to determine whether to change the step size of controlling the number of large-size PMOS arrays based on the output signal of the dynamic comparator in multiple consecutive clock cycles.

4. The digital LDO circuit suitable for large voltage difference as claimed in claim 2, characterized in that: The mode detector is configured to: detect the output voltage of the digital LDO in real time and adjust it; when the load current changes, the output voltage changes accordingly, causing the output voltage to leave the fine loop stable state, and at this time the mode detector controls the digital LDO to maintain the fine adjustment loop; When the output voltage change is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the fine loop bits are exhausted, indicating that the fine loop has entered a stable oscillation state, and the fine loop is kept adjusted slowly without enabling the coarse loop. When the output voltage change is greater than the maximum adjustment range of the fine loop, the output voltage cannot be adjusted to a stable oscillation state of the fine loop even if the fine loop adjustment bits are exhausted, so the digital LDO is controlled to enter the coarse adjustment loop; In the coarse-tuning loop, when the output voltage oscillates above and below the reference voltage for m clock cycles continuously, it indicates that the coarse-tuning loop has entered a stable oscillation state, and the digital LDO is controlled to enter a fine-tuning loop.

5. The digital LDO circuit suitable for large voltage difference as claimed in claim 2, characterized in that: The mode control circuit is configured as follows: when the mode detector detects that the load current jumps upward by more than 10 times, the undershoot detection circuit outputs 1, directly turns on half of the thick-ring large-size PMOS, and provides current to prevent the undershoot voltage from being too large.

6. The digital LDO circuit suitable for large voltage difference according to claim 1, characterized in that: The first gate voltage control module includes a buffer array, a first resistor, and a second resistor; The input end of the buffer array is connected to the output end of the first decoder, and the output end of the buffer array is connected to the gate of the large-size PMOS array; The source end of the buffer array is connected to the input voltage of the digital LDO, and the ground end of the buffer array is connected to the feedback voltage obtained by dividing the reference voltage through the first resistor and the second resistor.

7. The digital LDO circuit suitable for large voltage difference according to claim 1, characterized in that: The coarse-adjustment advance and retreat controller is configured to: detect the output signal of the dynamic comparator in the mode control circuit in real time, and when the dynamic comparator outputs 0, the coarse-adjustment advance and retreat controller outputs a coarse-loop PMOS shutdown quantity that decreases by a step length x; When the output state of the dynamic comparator does not change for n consecutive clock cycles, the coarse-loop PMOS shutdown quantity is increased to a decreasing step size of y, and the adjustment is continued until the output of the dynamic comparator is flipped, and the coarse-loop PMOS shutdown quantity is changed to an increasing step size, and the increasing step size is updated to the minimum step size x.

8. The digital LDO circuit suitable for large voltage difference according to claim 1, characterized in that: The fine adjustment loop includes a fine adjustment advance and retreat method controller, a second decoder, a second gate voltage control module and a small-size PMOS array connected in sequence; The fine-tuning advance and retreat controller outputs a signal indicating the number of small-size PMOS arrays that are turned off according to the state of the output voltage of the digital LDO, and the signal outputs a PMOS bit control signal to the second gate voltage control module through the second decoder; the second gate voltage control module uses resistor voltage division to reduce the reference voltage as the digital ground terminal of the buffer array to raise the logic 0 voltage of the PMOS bit control signal from the decoder, and accesses the small-size PMOS array bit by bit to raise the gate voltage of the turned-on PMOS and reduce the gate-source voltage to compensate for the increase in the voltage difference.

9. The voltage stabilization method for a digital LDO circuit with a large voltage difference as claimed in claims 1 to 8, characterized in that: include: Before each load change, the digital LDO is initially in a thin-loop stable state; When the output voltage of the digital LDO deviates from the stable state of the fine loop due to load changes, the mode detector controls the digital LDO to maintain the fine adjustment loop; if the current output voltage VOUT < the reference voltage VREF, the dynamic comparator outputs a signal Comp_out = 0, and controls the output fine loop PMOS closure number of the fine adjustment advance and retreat controller to decrease by a step length x; through the second decoder and the corresponding second gate voltage control module, the corresponding PMOS array is controlled to open one more, and the fine loop slow adjustment is performed; If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction does not change, the fine loop fast adjustment mode is entered, and the decreasing step length of the number of fine loop PMOS shutdowns is increased to y, and the adjustment is continued until Comp_out is flipped. The control direction of the fine adjustment advance and retreat controller is correspondingly changed to add, and the adding step length is updated to the minimum step length x. Until Comp_out does not change for n consecutive clock cycles, the adding step length is increased to y, and the fine loop fast adjustment is performed; If the output voltage change of the digital LDO is less than the maximum adjustment range of the fine loop, the output voltage can be adjusted to oscillate continuously above and below the reference voltage for m clock cycles before the number of bits of the fine adjustment loop is exhausted, indicating that the fine loop has entered a stable oscillation state and the fine loop is maintained at a slow adjustment speed without enabling the coarse adjustment loop.

10. The voltage stabilization method for a digital LDO circuit with a large voltage difference as claimed in claim 9, characterized in that: When the output voltage of the digital LDO changes due to load changes and is greater than the maximum adjustment range of the fine loop, the mode detector initially controls the digital LDO to enter the fine adjustment loop; when the fine loop adjustment bits are exhausted and the output voltage cannot be adjusted to the fine loop stable oscillation state, the fine loop PMOS shutdown number is reset to a, and the mode detector controls the digital LDO to enter the coarse adjustment loop; In the coarse adjustment loop, if the current output voltage VOUT < the reference voltage VREF, the dynamic comparator output signal Comp_out = 0, and the output coarse loop PMOS closing quantity of the coarse adjustment advance and retreat controller is controlled to decrease by the step length x; through the first decoder and the corresponding first gate voltage control module, the corresponding PMOS array is controlled to open one more, and the coarse loop slow adjustment is performed; If the output state of the dynamic comparator does not change for n consecutive clock cycles, indicating that the adjustment direction does not change, the decreasing step length of the coarse loop PMOS shutdown quantity is increased to y, and the adjustment is continued until Comp_out is reversed. The control direction of the coarse adjustment advance and retreat controller is correspondingly changed to add, and the add step length is updated to the minimum step length x. Until Comp_out does not change for n consecutive clock cycles, the add step length is increased to y, and the coarse loop fast adjustment is entered; When the mode detector detects that the output voltage oscillates above and below the reference voltage for m clock cycles continuously, it indicates that it has entered the coarse loop stable oscillation state, and the digital LDO is controlled to enter the fine loop; When entering the fine-tuning loop, the number of PMOS shutdowns in the coarse loop is taken as the larger value of the number of PMOS shutdowns that jump during the stable oscillation of the coarse loop, to ensure that when entering the fine-loop adjustment circuit again, the number of PMOS tube shutdowns is reduced; since the number of PMOS shutdowns in the fine loop is initialized to a, there is enough space to ensure that the fine loop adjustment enters a steady state to ensure low ripple.

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