Test data accelerated processing device, method and test machine

Abstract

The present application relates to a test data acceleration processing device, method and test machine, wherein a configuration information parsing module parses the received configuration parameters into configuration information, a data processing module receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the upper computer bottom software, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information to obtain the reorganized error cycle number, and stores the reorganized error cycle number in a storage module. The data analysis module performs data analysis according to the reorganized error cycle number stored in the storage module, and sends the target result data of the device under test obtained by the analysis to the upper computer. By completing the parsing, reorganization and target extraction of the original error cycle number in the test data acceleration processing device, that is, the process of processing the error cycle data originally in the upper computer is moved to the acceleration processing device, the upper computer can directly receive the processing result, release the transfer time of uploading the error cycle data, and improve the data processing efficiency.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a test data acceleration processing device, method and test machine. Background Art

[0002] Automated test equipment (ATE) is a device for testing devices under test (DUT). Due to its complex functions, high precision and high degree of automation, it is widely used in wafer (CP) and finished product inspection. A large amount of error cycle data will be generated during the test process, and it is necessary to quickly locate the number of cycles at each site to analyze the device under test. The traditional data analysis method is to aggregate the error cycle data collected by the front-end business card to the host computer through data frames for centralized calculation and statistics through software, which takes a long time for the host computer software to process. When the amount of error cycle data of the front-end business card reaches a certain scale (Gbytes), moving the error cycle data to the host computer will occupy the uplink channel for a long time, resulting in a long time for data processing. There is a disadvantage of low data processing efficiency. If the front-end business board has other uplink business data reported, the host computer cannot process it in time. Summary of the invention

[0003] Based on this, it is necessary to provide a test data acceleration processing device, method and test machine that can improve data processing efficiency in order to address the above problems.

[0004] The first aspect of the present application provides a test data accelerated processing device, comprising: a configuration information parsing module, a data processing module, a storage module and a data analysis module;

[0005] The configuration information parsing module parses the received configuration parameters into configuration information;

[0006] The data processing module is connected to the configuration information parsing module and the storage module, receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the upper computer, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module; the original error cycle number is the test cycle corresponding to the test result data when the test result data returned by the device under test of each site after inputting the stimulus is inconsistent with the expected data;

[0007] The data analysis module is connected to the storage module and the host computer, performs data analysis according to the number of reorganization error cycles stored in the storage module, and sends the target result data of the device under test obtained by the analysis to the host computer.

[0008] In one of the embodiments, the storage module includes a DDR memory and a FIFO storage module; the DDR memory is connected to the data processing module and the FIFO storage module, and the FIFO storage module is connected to the data analysis module.

[0009] In one of the embodiments, the data processing module includes a data parsing module, a DDR write controller and a DDR read controller;

[0010] The data analysis module is connected to the service board, the configuration information analysis module and the DDR write controller, the DDR write controller is connected to the configuration information analysis module, the DDR read controller and the DDR memory, and the DDR read controller is connected to the DDR memory.

[0011] In one of the embodiments, the configuration information parsing module sends a startup enable instruction, a parsing mode instruction and a data length to the data parsing module according to the received configuration parameters, and sends a startup enable instruction, a data length, a storage start address and a daughter card number to the DDR write controller;

[0012] After receiving the start-up enable instruction, the data parsing module performs parsing and reorganization based on the parsing mode determined by the parsing mode instruction, in combination with the channel mask information, the data length and the original error cycle number transmitted by the service board, and obtains the reorganized error cycle number and sends it to the DDR write controller;

[0013] After receiving the start enable instruction, the DDR write controller writes the number of reorganization error cycles of each daughter board card into the corresponding storage space in the DDR memory according to the data length, the storage start address and the daughter board card number; after the number of reorganization error cycles of each daughter board card is written into the DDR memory, the DDR write controller sends a write enable end instruction, the daughter board card number, and the storage address of the number of reorganization error cycles of each daughter board card in the DDR memory to the DDR read controller;

[0014] After receiving the write enable end instruction, the DDR read controller writes the reorganization error cycle number of each daughter card into the corresponding FIFO unit in the FIFO storage module for parallel storage according to the daughter card number and the storage address of the reorganization error cycle number of each daughter card in the DDR memory;

[0015] The data analysis module performs comparative analysis based on the number of reorganization error cycles stored in parallel in the FIFO storage module, obtains target result data of the device under test and sends it to the host computer.

[0016] In one of the embodiments, the data parsing module determines the parsing mode based on the parsing mode instruction, selects the corresponding site flag and error cycle from the original error cycle number, calculates the corresponding error site information by combining the selected site flag with the channel mask information, combines the error site information with the selected error cycle, obtains the reconstructed error cycle number and sends it to the DDR write controller.

[0017] In one of the embodiments, the data analysis module extracts multiple sub-masks from the channel mask information, performs bitwise AND operation on each bit of the sub-mask and each bit of the selected site flag to obtain the calculation result of each bit, and then performs bitwise OR operation on the calculation result of each bit to obtain the site bit information corresponding to each sub-mask; the data analysis module summarizes the site bit information corresponding to each sub-mask to obtain the error site information.

[0018] In one of the embodiments, the DDR write controller determines whether the current data has been received based on the data length. When the data length and the number of reassembly error cycles of each daughter board card are equal, it is determined that the data reception is completed and the data parsing is completed. Otherwise, the number of reassembly error cycles of each daughter board card is waited for to be sent to the DDR write controller until the data length and the number of reassembly error cycles of each daughter board card are equal.

[0019] In one embodiment, the target result data includes the first error cycle and all error cycles of the device under test at each site.

[0020] In one embodiment, the data analysis module includes a data comparison module and a result processing module, the data comparison module is connected to the storage module and the result processing module, and the result processing module is connected to a host computer;

[0021] The data comparison module compares the error cycles in the reorganized error cycle number, obtains the error site information corresponding to the minimum error cycle, and performs a bitwise OR operation on the error site information corresponding to the minimum error cycle to obtain the error site information of all sub-boards corresponding to the minimum error cycle and combine them, generates minimum value data and sends them to the result processing module, and cyclically obtains the minimum value data until all error cycles of the reorganized error cycle number in the storage module are processed;

[0022] The result processing module performs analysis according to the minimum value data, counts the first error cycle and all error cycles of the device under test at each site, and sends them to the host computer.

[0023] A second aspect of the present application provides a test data accelerated processing method, comprising:

[0024] The configuration information parsing module parses the received configuration parameters into configuration information;

[0025] The data processing module receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the upper computer bottom software, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module; the original error cycle number is the test cycle corresponding to the test result data when the test result data returned by the device under test of each site after inputting the stimulus is inconsistent with the expected data;

[0026] The data analysis module performs data analysis according to the number of reorganization error cycles stored in the storage module, and sends target result data of the device under test obtained through the analysis to the host computer.

[0027] A third aspect of the present application provides a test machine, comprising a service board, a host computer and the above-mentioned test data acceleration processing device, wherein the test data acceleration processing device is connected to the service board and the host computer.

[0028] In the test data acceleration processing device, method and test machine, the configuration information parsing module parses the received configuration parameters into configuration information, the data processing module receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the host computer bottom software, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module. The data analysis module performs data analysis according to the reorganized error cycle number stored in the storage module, and sends the target result data of the device under test obtained by the analysis to the host computer. By completing the parsing and reorganization of the original error cycle number and target extraction in the test data acceleration processing device, the extracted target result data is sent to the host computer, that is, the process of processing the error cycle data originally in the host computer is moved to the acceleration processing device, the host computer can directly receive the processing result, release the transfer time of uploading the error cycle data, release the software resources of the host computer, release the occupancy of the uplink channel PCIE, improve the data processing efficiency, and effectively improve the response of the host computer to other uplink services. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A structural block diagram of a test data acceleration processing device in one embodiment;

[0030] Figure 2 A structural schematic diagram of a test data acceleration processing device in one embodiment;

[0031] Figure 3 A schematic diagram of a data analysis principle in an embodiment;

[0032] Figure 4A schematic diagram of a data comparison principle in an embodiment;

[0033] Figure 5 A schematic diagram of the result processing principle in an embodiment;

[0034] Figure 6 The figure is a flow chart of a method for accelerating processing of test data in one embodiment. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, methods, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, methods, operations, components, parts or combinations thereof.

[0039] In ATE equipment, there are often test scenarios where the same service board is tested across sites or the same site is tested across service boards. Multiple sites can refer to multiple chips to be tested, and each site is a test station for one chip; multiple sites can also refer to multiple pins of a chip, and all pins of multiple chips can be distributed on one service board or on multiple service boards; service boards can be digital boards, and the test result data can be pattern data. When performing periodic statistics on error data on the service board side, the error cycle data statistics of the site will be incomplete, resulting in misjudgment of the test results of the chip to be tested or inaccurate positioning of the error data. The current data analysis method is to transmit the error cycle data of the front-end service board to the adapter card through optical transmission and then hand it over to the host computer for processing, which will lead to a series of problems such as long uplink channel occupation time, long host computer software processing time, and long error cycle data transfer time, which ultimately leads to inefficient chip test results.

[0040] Based on this, the test data acceleration processing device provided by the present application, the configuration information parsing module parses the received configuration parameters into configuration information, the data processing module receives the original error cycle number transmitted by the business board and the channel mask information transmitted by the upper computer bottom software, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module. The data analysis module performs data analysis based on the reorganized error cycle number stored in the storage module, and sends the target result data of the device under test obtained by the analysis to the upper computer. By completing the parsing, reorganization and target extraction of the original error cycle number in the test data acceleration processing device, and sending the extracted target result data directly to the upper computer, the transfer time of data upload can be effectively reduced, and the upper computer software processing resources can be released, as well as the occupancy of the uplink channel (PCIE), reducing the impact on the reporting of other uplink business data.

[0041] In one embodiment, Figure 1 As shown, a test data acceleration processing device is provided, including a configuration information parsing module 110, a data processing module 120, a storage module 130 and a data analysis module 140. The configuration information parsing module 110 parses the received configuration parameters into configuration information, the data processing module 120 connects the configuration information parsing module 110 and the storage module 130, receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the upper computer bottom soft, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module 130; the data analysis module 140 connects the storage module 130 and the upper computer, performs data analysis according to the reorganized error cycle number stored in the storage module 130, and sends the target result data of the device under test obtained by the analysis to the upper computer.

[0042] Among them, the original error cycle number is the test cycle corresponding to the test result data when the test result data returned by the device under test of each site after the input stimulus is inconsistent with the expected data. The configuration information parsing module 110 receives the configuration parameters transmitted by the upper computer bottom software (bottom drive) for parsing, obtains the configuration information and sends it to the data processing module 120. The data processing module 120 receives the channel mask information transmitted by the upper computer bottom software and the original error cycle number of multiple sub-board cards (fe) transmitted by the business board card. The sub-board card may include sub-board card fe0, sub-board card fe1, etc., and the specific number is not unique. The configuration information may include information such as startup enable instruction, parsing mode instruction, data length, storage start address, sub-board card number, etc. The data length represents the data volume of the reorganized error cycle number of each sub-board card. The data processing module 120 combines the received configuration information and channel mask information to parse and reorganize the original error cycle number, obtain the required reorganized error cycle number and store it in the storage module 130. The storage module 130 can store the number of reorganization error cycles separately according to different daughter boards, so that the data analysis module 140 can analyze the number of reorganization error cycles corresponding to each daughter board, determine the target result data of the device under test and send it to the host computer. It can be understood that the specific type and quantity of the target result data are not unique and can be set according to actual test needs.

[0043] The specific structure of the storage module 130 is not unique. Figure 2 As shown, the storage module 130 may include a DDR memory 132 and a FIFO storage module 134; the DDR memory 132 is connected to the data processing module 120 and the FIFO storage module 134, and the FIFO storage module 134 is connected to the data analysis module 140. The configuration information parsing module 110, the data processing module 120, the FIFO storage module 134 and the data analysis module 140 may all be set on the FPGA, and the DDR memory 132 is a DDR memory outside the FPGA.

[0044] Further, the data processing module 120 may specifically include a data parsing module 122, a DDR write controller 124, and a DDR read controller 126. The data parsing module 122 is connected to the service board DIO, the configuration information parsing module 110, and the DDR write controller 124; the DDR write controller 124 is connected to the configuration information parsing module 110, the DDR read controller 126, and the DDR memory 132; and the DDR read controller 126 is connected to the DDR memory 132. The configuration information parsing module 110 sends the start enable instruction Fail_start, the parsing mode instruction Fail_data_pat, and the data length Ddr_row_length to the data parsing module 122 according to the received configuration parameter Cfg_message, and sends the start enable instruction Fail_start, the data length Ddr_row_length, the storage start address Ddr_start_addr, and the subboard card number Fe_num to the DDR write controller 124. Among them, the configuration parameter Cfg_message is sent by the upper computer bottom software, and the configuration information includes the start enable instruction Fail_start, the parsing mode instruction Fail_data_pat, the data length Ddr_row_length, the storage start address Ddr_start_addr and the daughter board card number Fe_num.

[0045] After receiving the start enable instruction Fail_start, the data parsing module 122 performs parsing and reorganization based on the parsing mode determined by the parsing mode instruction Fail_data_pat (supporting parsing of three modes: X1, X2, and X4), combined with the channel mask information Site_channel_mak, the data length Ddr_row_length, and the original error cycle number Fail_cycle_data transmitted by the business board DIO, to obtain the reorganized error cycle number Fail_data and send it to the DDR write controller 124; after receiving the start enable instruction Fail_start, the DDR write controller 124 writes the reorganized error cycle number Fail_data of each sub-board into the corresponding storage space in the DDR memory 132 according to the data length Ddr_row_length, the storage start address Ddr_start_addr, and the sub-board number Fe_num; after the reorganized error cycle number Fail_data of each sub-board is written into the DDR memory 132, the DDR write controller 124 sends a write enable end instruction All fe wr done, the daughter board number Fe_num, and the storage address (Fe_ddr_start_addr, Fe_ddr_end_addr) of the number of reassembled error cycles of each daughter board (fe0, fe1, etc.) in the DDR memory 132 to the DDR read controller 126. After receiving the number of reassembled error cycles Fail_data of each daughter board, the DDR write controller 124 follows the pipeline form and synchronously sends the number of reassembled error cycles Fail_data of each daughter board to the DDR memory 132. After receiving the write enable end instruction All fe wr done, the DDR read controller 126 writes the number of reassembled error cycles of each daughter board into the corresponding FIFO unit in the FIFO storage module 134 for parallel storage (Fe0_data_fifo, Fe1_data_fifo, etc.) according to the daughter board number Fe_num and the storage address of the number of reassembled error cycles of each daughter board in the DDR memory 132. The data analysis module 140 performs comparative analysis based on the number of reassembly error cycles stored in parallel in the FIFO storage module 134, obtains target result data of the device under test, and sends it to the host computer.

[0046] Among them, Figure 3As shown, the data parsing module 122 first determines whether to start the data acceleration (FAIL ACC) function by starting the enable instruction Fail_start. When the start enable instruction Fail_start is equal to 1, data acceleration is started, and then the parsing mode of this data acceleration is set by the configured parsing mode instruction Fail_data_pat. When Fail_data_pat=0, it is X1 mode (this mode is also the default mode after the device is powered on); when Fail_data_pat=1, it is X2 mode; when Fail_data_pat=2, it is X4 mode. The data parsing module 122 determines the parsing mode based on the parsing mode instruction Fail_data_pat. In the corresponding parsing mode, the corresponding site sign (site_sign) and error cycle (cycle num) are selected from the original error cycle number Fail_cycle_data, and the corresponding error site information (Fail site) is calculated by combining the selected site sign and the channel mask information Site_channel_mak. The error site information is combined with the selected error cycle to obtain the reorganized error cycle number Fail_data and send it to the DDR write controller 124. The DDR write controller 124 determines whether the current data has been received in combination with the data length Ddr_row_length. When the data length Ddr_row_length and the number of recombination error cycles of each daughter board are equal, the data parsing is completed after the data is determined to be received. Otherwise, the recombination error cycle number of each daughter board is sent to the DDR write controller until the data length Ddr_row_length and the number of recombination error cycles of each daughter board are equal. The counter in the DDR write controller 124 counts the number of recombination error cycles of each daughter board.

[0047] Furthermore, the data analysis module 122 extracts multiple sub-masks from the channel mask information Site_channel_mak, performs bitwise AND operations on each bit of the sub-mask and each bit of the selected site flag to obtain the calculation result of each bit, and then performs bitwise OR operations on the calculation result of each bit to obtain the site bit information corresponding to each sub-mask; the data analysis module 122 summarizes the site bit information corresponding to each sub-mask to obtain the error site information.

[0048] Specifically, the information format of the original error cycle number Fail_cycle_data uploaded by the front-end service board DIO is shown in Table 1.

[0049] Table 1

[0050]

[0051] When the parsing mode is X1 mode, the MSB [95:64] 32 bits are recorded as the site sign site_sign[31:0], and the LSB [47:0] 48 bits are recorded as the error cycle cycle num. The channel mask information Site_channel_mak has 64 groups of 32-bit data, with a total width of 2048 bits. The corresponding error site information can be calculated through the site sign site_sign and the channel mask information Site_channel_mak. Since the site sign site_sign has a width of 32 bits, the lower 1024 bits of the channel mask information Site_channel_mak are needed for calculation, and the 128 bits are divided into 32 32-bit sub-masks (remember channel_mask0=channel mask[31:0], channel_mask1=channel mask[63:32]…channel_mask31=channel mask[1023:992]). The 32 bits of a sub-mask are bitwise ANDed with the 32 bits of the site sign site_sign to obtain the 32-bit calculation result, which is then bitwise ORed to obtain the 1-bit information of the site. Then, the 32 sub-masks are calculated with the site sign site_sign respectively to obtain the 32 bits of the site. At this point, the corresponding error site information is obtained, and then combined with the error cycle cycle num to obtain the reorganized error cycle number Fail_data.

[0052] When the parsing mode is X2 mode, the main difference between this mode and X1 mode is the bit selection of site information. The high 64 bits of the original error cycle number Fail_cycle_data contain 2 sets of site information, that is, [127:96] and [95:64] represent site0 and site1 respectively. When corresponding to site0, the error cycle cycle num is the lower 48 bits of the original error cycle number Fail_cycle_data shifted right by one bit; when corresponding to site1, the error cycle cycle num is the lower 48 bits of the original error cycle number Fail_cycle_data shifted right by one bit plus 1. The subsequent calculation and processing are the same as those in X1 mode.

[0053] When the parsing mode is X4 mode, similarly, the upper 64 bits of the original error cycle number Fail_cycle_data in this mode contain 4 sets of site information, namely [127:112], [111:96], [95:80] and [79:64] respectively represent site0, site1, site2 and site3. When corresponding to site0, the error cycle cycle num is the lower 48 bits of the original error cycle number Fail_cycle_data shifted right by two bits; when corresponding to site1, the error cycle cycle num is the lower 48 bits of the original error cycle number Fail_cycle_data shifted right by two bits plus 1; when corresponding to site2, the error cycle cycle num is the lower 48 bits of the original error cycle number Fail_cycle_data shifted right by two bits plus 2; when corresponding to site3, the error cycle cycle num is the lower 48 bits of the original error cycle number Fail_cycle_data shifted right by two bits plus 3, and the subsequent calculation and processing are the same as in X1 mode.

[0054] After receiving the start enable instruction Fail_start and the number of reorganized error cycles Fail_data, the DDR write controller 124 sends the write data Ddr_wr_data to the DDR memory 132 according to the data length Ddr_row_length, the storage start address Ddr_start_addr and the sub-board card number Fe_num, writes the number of reorganized error cycles of each sub-board card (fe0, fe1, etc.) into the corresponding storage space in the DDR memory 132 for serial storage, and determines whether the writing is completed or not by the sub-board card number Fe_num. When the data of all sub-board cards are written into the DDR memory 132, the write enable end instruction All fe wr done is sent to the subsequent DDR read controller 126. Among them, the storage space of the DDR memory 132 can be flexibly configured according to the current test scenario configuration (DDR storage is up to 8G, and the current sub-board card fe supports a maximum number of 64. Then when Fe num=64 is configured, the maximum data of each sub-board card fe=128M, and the corresponding DDR storage is 512K of error data).

[0055] After receiving the write enable end instruction All fe wrdone sent by the previous DDR write controller 124, the DDR read controller 126 starts the read state, sends the read instruction Rd_ctrl to the DDR memory 132, sends the write data ddr_rd_data from the DDR memory 132 to the FIFO storage module 134, and writes the number of reorganization error cycles of each sub-board card into the corresponding FIFO unit for parallel storage (Fe0_data_fifo, Fe1_data_fifo, etc.). The first read operation of the DDR read controller 126 is to write the half-full number of reorganization error cycles, i.e., 512 error data, into the FIFO unit corresponding to the number of configured sub-board cards from the DDR memory 132 side. This operation is to process the DDR read polling state machine. After all the FIFO units of all the sub-board cards fe to be configured are written, the first read comparison operation is started, i.e., one error data is read in parallel for each FIFO unit, and then these error data are transmitted to the data analysis module 140 for processing to obtain the target result data of the device under test.

[0056] In one embodiment, the target result data includes the first error cycle Fail_site_first_cycle and all error cycles Fail_site_all_cycle of the DUT at each site. Figure 2 As shown, the data analysis module 140 may include a data comparison module 142 and a result processing module 144. The data comparison module 142 is connected to the storage module 130 and the result processing module 144, specifically connected to the FIFO storage module 134 in the storage module 130, and the result processing module 144 is connected to the host computer. The data comparison module 142 compares the error cycles in the reorganized error cycle number, obtains the error site information corresponding to the minimum error cycle, and performs a bitwise OR operation on the error site information corresponding to the minimum error cycle, obtains the error site information of all sub-boards corresponding to the minimum error cycle and combines them, generates minimum value data (min_data) and sends it to the result processing module 144, and cyclically obtains the minimum value data until all error cycles of the reorganized error cycle number in the storage module 130 are processed; the result processing module 144 performs analysis based on the minimum value data, and counts the first error cycle Fail_site_first_cycle and all error cycles Fail_site_all_cycle of the device under test at each site and sends them to the host computer.

[0057] Specifically, Figure 4The comparison diagram of the data comparison module 142 is shown in FIG. 142. For example, the data in the figure is the lower 48 bits of the corresponding FIFO data output, i.e., the error cycle cycle num. After the data comparison module 142 compares the error cycle cycle num to obtain the minimum error cycle after the current comparison, the high 32 bits of the site information corresponding to the minimum error cycle (there may be a situation where the error cycle cycle num corresponds to multiple site information) are bitwise ORed to obtain the error site information of all sub-board cards fe corresponding to the minimum error cycle (only one site repeat is required if the site is valid), and the new 80-bit minimum value data min_data is combined and transmitted to the result processing module 144 of the subsequent stage. After the comparison is completed, the FIFO read enable corresponding to the minimum error cycle is enabled, and other non-minimum value data remain unchanged, and the FIFO read enable is not enabled. The result processing module 144 parses the error site information of the high 32 bits of the minimum value data min_data. If the site in the 32 bits is 1, the corresponding site counter count is increased by 1, and the minimum error cycle of each site, i.e., the first error cycle Fail_site_first_cycle of the site, is latched at the same time.

[0058] After the above steps are completed, it is necessary to continue the next comparison. In the previous round of comparison, the data comparison module 142 enables the FIFO corresponding to the minimum data to read the next data, and other non-minimum data are retained, and then a new round of comparison is performed with the data read from the FIFO corresponding to the minimum data to find the minimum data of this round of comparison. As in the previous comparison process, the data comparison module 142 continues to output the minimum data min_data to the result processing module 144, and this cycle is repeated until all the data in the DDR and the data in the FIFO are empty (when the FIFO reads data, the half-full flag of the FIFO and the empty and full flags of the corresponding fe of the DDR will be judged in real time. When the data stored in the FIFO is less than half full, there is still data in the corresponding FE in the DDR, and the DDR read control will initiate a read operation. The DDR read operation will continue to poll until all the data corresponding to fe in the DDR are empty before the DDR empty flag is pulled high). After the comparison is completed, the count of each site is reported, that is, all error cycles Fail_site_all_cycle of each site. The processing flow of the result processing module 144 is as follows Figure 5 As shown, there are 32 synchronization processes in total. When there is no data in the corresponding DDR and FIFO, the result processing module 144 reports the first error cycle Fail_site_first_cycle and all error cycles Fail_site_all_cycle corresponding to the site. When the upper computer bottom drive obtains the acceleration completion flag fail acc done during polling, it will read the corresponding result and complete the data acceleration operation.

[0059] In one embodiment, Figure 6 As shown, a test data acceleration processing method is also provided, comprising:

[0060] Step S110: The configuration information parsing module parses the received configuration parameters into configuration information.

[0061] Step S120: The data processing module receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the upper computer, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module. The original error cycle number is the test cycle corresponding to the test result data when the test result data returned by the device under test at each site after inputting the stimulus is inconsistent with the expected data.

[0062] Step S130: the data analysis module performs data analysis according to the number of reorganization error cycles stored in the storage module, and sends the target result data of the device under test obtained through the analysis to the host computer.

[0063] It can be understood that the specific embodiment of the above-mentioned test data accelerated processing method has been explained in detail in the above-mentioned test data accelerated processing device, and will not be repeated here.

[0064] In one embodiment, a test machine is also provided, including a business board, a host computer and the above-mentioned test data acceleration processing device, and the test data acceleration processing device is connected to the business board and the host computer. The test data acceleration processing device can be located on the communication board or can be independent of the communication board. If it is independent of the communication board, the test data acceleration processing device is connected to the business board via the communication board, and the test data acceleration processing device is connected to the host computer. The host computer can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and portable wearable devices, and the portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0065] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A test data acceleration processing device, characterized in that: include: Configuration information parsing module, data processing module, storage module and data analysis module; The configuration information parsing module parses the received configuration parameters into configuration information; The data processing module is connected to the configuration information parsing module and the storage module, receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the upper computer bottom software, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information, selects the corresponding site flag and error cycle from the original error cycle number, combines the selected site flag with the channel mask information to obtain the corresponding error site information, combines the error site information with the selected error cycle to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module; the original error cycle number is the test cycle corresponding to the test result data when the test result data returned by the device under test of each site after inputting stimulus is inconsistent with the expected data; The data analysis module is connected to the storage module and the host computer, performs data analysis according to the number of reorganization error cycles stored in the storage module, and sends the target result data of the device under test obtained by the analysis to the host computer.

2. The device according to claim 1, characterized in that The storage module includes a DDR memory and a FIFO storage module; the DDR memory is connected to the data processing module and the FIFO storage module, and the FIFO storage module is connected to the data analysis module.

3. The device according to claim 2, characterized in that The data processing module includes a data parsing module, a DDR write controller and a DDR read controller; The data analysis module is connected to the service board, the configuration information analysis module and the DDR write controller, the DDR write controller is connected to the configuration information analysis module, the DDR read controller and the DDR memory, and the DDR read controller is connected to the DDR memory.

4. The device according to claim 3, characterized in that The configuration information parsing module sends a startup enable instruction, a parsing mode instruction and a data length to the data parsing module according to the received configuration parameters, and sends a startup enable instruction, a data length, a storage start address and a daughter card number to the DDR write controller; After receiving the start-up enable instruction, the data parsing module performs parsing and reorganization based on the parsing mode determined by the parsing mode instruction, in combination with the channel mask information, the data length and the original error cycle number transmitted by the service board, and obtains the reorganized error cycle number and sends it to the DDR write controller; After receiving the start enable instruction, the DDR write controller writes the number of reorganization error cycles of each daughter board card into the corresponding storage space in the DDR memory according to the data length, the storage start address and the daughter board card number; after the number of reorganization error cycles of each daughter board card is written into the DDR memory, the DDR write controller sends a write enable end instruction, the daughter board card number, and the storage address of the number of reorganization error cycles of each daughter board card in the DDR memory to the DDR read controller; After receiving the write enable end instruction, the DDR read controller writes the reorganization error cycle number of each daughter card into the corresponding FIFO unit in the FIFO storage module for parallel storage according to the daughter card number and the storage address of the reorganization error cycle number of each daughter card in the DDR memory; The data analysis module performs comparative analysis based on the number of reorganization error cycles stored in parallel in the FIFO storage module, obtains target result data of the device under test and sends it to the host computer.

5. The device according to claim 4, characterized in that The data parsing module determines the parsing mode based on the parsing mode instruction, selects the corresponding site flag and error cycle from the original error cycle number, calculates the corresponding error site information by combining the selected site flag with the channel mask information, combines the error site information with the selected error cycle, obtains the reconstructed error cycle number and sends it to the DDR write controller.

6. The device according to claim 5, characterized in that The data analysis module extracts multiple sub-masks from the channel mask information, performs bitwise AND operation on each bit of the sub-mask and each bit of the selected site flag to obtain the calculation result of each bit, and then performs bitwise OR operation on the calculation result of each bit to obtain the site bit information corresponding to each sub-mask; the data analysis module summarizes the site bit information corresponding to each sub-mask to obtain the error site information.

7. The device according to claim 6, characterized in that The DDR write controller determines whether the current data has been received in combination with the data length. When the data length and the number of recombination error cycles of each daughter board card are equal, it is determined that the data reception is completed and the data parsing is completed. Otherwise, the number of recombination error cycles of each daughter board card is waited for to be sent to the DDR write controller until the data length and the number of recombination error cycles of each daughter board card are equal.

8. The device according to any one of claims 1 to 7, characterized in that: The target result data includes the first error cycle and all error cycles of the device under test at each site.

9. The device according to claim 8, characterized in that The data analysis module includes a data comparison module and a result processing module, the data comparison module is connected to the storage module and the result processing module, and the result processing module is connected to the host computer; The data comparison module compares the error cycles in the reorganized error cycle number, obtains the error site information corresponding to the minimum error cycle, and performs a bitwise OR operation on the error site information corresponding to the minimum error cycle to obtain the error site information of all sub-boards corresponding to the minimum error cycle and combine them, generates minimum value data and sends them to the result processing module, and cyclically obtains the minimum value data until all error cycles of the reorganized error cycle number in the storage module are processed; The result processing module performs analysis according to the minimum value data, counts the first error cycle and all error cycles of the device under test at each site, and sends them to the host computer.

10. A test data accelerated processing method, characterized in that: include: The configuration information parsing module parses the received configuration parameters into configuration information; The data processing module receives the original error cycle number transmitted by the service board and the channel mask information transmitted by the upper computer bottom soft, parses and reorganizes the original error cycle number according to the configuration information and the channel mask information, selects the corresponding site flag and error cycle from the original error cycle number, combines the selected site flag with the channel mask information to obtain the corresponding error site information, combines the error site information with the selected error cycle to obtain the reorganized error cycle number, and stores the reorganized error cycle number in the storage module; the original error cycle number is the test cycle corresponding to the test result data when the test result data returned by the device under test of each site after input stimulation is inconsistent with the expected data; The data analysis module performs data analysis according to the number of reorganization error cycles stored in the storage module, and sends target result data of the device under test obtained through the analysis to the host computer.

11. A testing machine, characterized in that: It comprises a service board, a host computer and the test data acceleration processing device according to any one of claims 1 to 9, wherein the test data acceleration processing device is connected to the service board and the host computer.

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