Inter-core communication method and device, multi-core processor and electronic equipment

Abstract

The invention provides an inter-core communication method and device, a multi-core processor, electronic equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: storing target data into a target shared memory through a data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core; triggering inter-core interruption in the target channel through the data sending core; wherein the target channel is any channel in an inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function; and calling a receiving response function configured by the target channel to receive the target data in the target shared memory through the data receiving core in response to the inter-core interruption triggered in the target channel. According to the invention, multiple communication types can be supported, and applicable inter-core communication scenes are enriched.

Description

Technical Field

[0001] The present application relates to computer technology, and in particular to an inter-core communication method, device, multi-core processor, electronic device, computer-readable storage medium and computer program product. Background Art

[0002] A multi-core processor is a processor that integrates multiple complete computing engines (cores) that can process tasks in parallel, thereby improving processing efficiency. At present, multi-core processors are widely used in a variety of application scenarios. For example, in the automotive electronic and electrical architecture, the system-on-chip (SoC) used for automotive domain controllers often has multi-core heterogeneity, so it can process multiple tasks simultaneously, such as perception, decision-making, control, etc., thereby improving the intelligence level of the car and driving safety.

[0003] In a multi-core processor, applications deployed on different cores often need to synchronize their key data, and inter-core communication technology is one of the key technologies to support such requirements. However, in the solutions provided by related technologies, inter-core communication usually only supports a single communication type, which makes it impossible to adapt to the complex and changing inter-core communication requirements. Summary of the invention

[0004] The present application provides an inter-core communication method, device, multi-core processor, electronic device, computer-readable storage medium and computer program product, which can support multiple communication types and enrich applicable inter-core communication scenarios.

[0005] The technical solution of this application is implemented as follows:

[0006] The present application provides an inter-core communication method, which is applied to a multi-core processor; the method comprises:

[0007] The target data is stored in the target shared memory through the data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core;

[0008] triggering an inter-core interrupt on a target channel through the data sending core; wherein the target channel is any channel in an inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function;

[0009] In response to the inter-core interrupt triggered by the target channel, the data receiving core calls a receiving response function configured by the target channel to receive the target data in the target shared memory.

[0010] The present application provides an inter-core communication device, which is applied to a multi-core processor; the device comprises:

[0011] A storage module, used for storing target data into a target shared memory through a data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core;

[0012] An inter-core interrupt module, used to trigger an inter-core interrupt on a target channel through the data sending core; wherein the target channel is any channel in the inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function;

[0013] The receiving module is used to respond to the inter-core interrupt triggered on the target channel through the data receiving core, and call the receiving response function configured on the target channel to receive the target data in the target shared memory.

[0014] The present application provides a multi-core processor, which includes executable instructions. The multi-core processor runs in an electronic device to implement the inter-core communication method provided in the present application.

[0015] The present application provides an electronic device, including:

[0016] A memory for storing executable instructions;

[0017] The processor is used to implement the inter-core communication method provided in the present application when executing the executable instructions stored in the memory.

[0018] The present application provides a computer-readable storage medium storing executable instructions for causing a processor to execute and implement the inter-core communication method provided by the present application.

[0019] The present application provides a computer program product, which includes executable instructions for causing a processor to execute and implement the inter-core communication method provided by the present application.

[0020] This application has the following beneficial effects:

[0021] The present application stores the target data to the target shared memory through the data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core; the inter-core interrupt is triggered in the target channel through the data sending core; wherein the target channel is any channel in the inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function; the data receiving core responds to the inter-core interrupt triggered in the target channel, and calls the receiving response function configured in the target channel to receive the target data in the target shared memory. The present application configures a receiving response function in each channel, so it can support multiple communication types; it can select the appropriate receiving response function for inter-core communication according to actual needs, thereby enriching the applicable inter-core communication scenarios and promoting the platformization of inter-core communication technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a first structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0024] Figure 2 is a second structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0025] Figure 3 It is a first flow chart of the inter-core communication method provided in an embodiment of the present application;

[0026] Figure 4 is a second flow chart of the inter-core communication method provided in an embodiment of the present application;

[0027] Figure 5 It is a flow chart of inter-core communication based on query response function provided in an embodiment of the present application;

[0028] Figure 6 It is a flowchart of inter-core communication based on interrupt response function implementation provided by an embodiment of the present application;

[0029] Figure 7 It is a flowchart of a single-core restart scenario provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0031] In the following description, reference is made to "some embodiments", which describes a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. In the following description, reference is made to the term "multiple" to mean at least two.

[0032] In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0034] The embodiments of the present application provide an inter-core communication method, device, multi-core processor, electronic device, computer-readable storage medium, and computer program product, which can support multiple communication types and enrich applicable inter-core communication scenarios. The following describes an exemplary application of the electronic device provided by the embodiments of the present application. The electronic device provided by the embodiments of the present application can be implemented as various types of terminal devices or as a server.

[0035] See also Figure 1 , Figure 1 is a schematic diagram of a structure of an electronic device provided in an embodiment of the present application, Figure 1 In the figure, the electronic device 100 includes a processor 110, which is a multi-core processor. For ease of understanding, inter-core communication between a data sending core 110-1 and a data receiving core 110-2 in the processor 110 is taken as an example for explanation.

[0036] In some embodiments, the data sending core 110-1 stores the target data to the target shared memory; wherein the target shared memory is shared by the data sending core 110-1 and the data receiving core 110-2; the data sending core 110-1 triggers an inter-core interrupt on a target channel; wherein the target channel is any channel in the inter-core communication link between the data sending core 110-1 and the data receiving core 110-2, and each channel is configured with a receive response function; the data receiving core 110-2 responds to the inter-core interrupt triggered on the target channel, and calls the receive response function configured on the target channel to receive the target data in the target shared memory.

[0037] In some embodiments, the electronic device 100 can implement the inter-core communication method provided in the embodiments of the present application by running a computer program.

[0038] See also Figure 2 , Figure 2 is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of the present application, Figure 2The electronic device 100 shown includes: at least one processor 110, a memory 150 and at least one network interface 120. The various components in the electronic device 100 are coupled together via a bus system 140. It is understood that the bus system 140 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 140 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, the bus system 140 is not described in detail. Figure 2 Various buses are labeled as bus system 140 .

[0039] The processor 110 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., where the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0040] The memory 150 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. The memory 150 may optionally include one or more storage devices that are physically remote from the processor 110.

[0041] The memory 150 includes a volatile memory or a non-volatile memory, and may also include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), and the volatile memory may be a random access memory (RAM). The memory 150 described in the embodiments of the present application is intended to include any suitable type of memory.

[0042] In some embodiments, the memory 150 can store data to support various operations, examples of which include programs, modules, and data structures, or a subset or superset thereof, as exemplarily described below.

[0043] Operating system 151, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;

[0044] A network communication module 152, used to reach other computing devices via one or more (wired or wireless) network interfaces 120, exemplary network interfaces 120 include: Bluetooth, Wireless Authentication (WiFi), and Universal Serial Bus (USB);

[0045] In some embodiments, the inter-core communication device provided in the embodiments of the present application can be implemented in software. Figure 2 The inter-core communication device 155 stored in the memory 150 is shown, which can be software in the form of a program and a plug-in, etc., including the following software modules: a storage module 1551, an inter-core interrupt module 1552, and a receiving module 1553. These modules are logical, so they can be arbitrarily combined or further split according to the functions implemented. The functions of each module will be explained below.

[0046] The inter-core communication method provided in the embodiment of the present application will be explained in combination with the exemplary application and implementation of the electronic device provided in the embodiment of the present application.

[0047] See also Figure 3 , Figure 3 is a flow chart of the inter-core communication method provided in the embodiment of the present application, which will be combined with Figure 3 The steps shown are explained.

[0048] In step 101, the data sending core stores target data in a target shared memory; wherein the target shared memory is shared by the data sending core and the data receiving core.

[0049] Here, the data sending core is any core in the multi-core processor, and the data receiving core is any core in the multi-core processor that is different from the data sending core. When the data sending core faces the need to send target data to the data receiving core, it first stores the target data in the target shared memory, where the target data refers to any data, and the target shared memory is shared by the data sending core and the data receiving core.

[0050] It is worth mentioning that shared memory allows different cores to access the same memory space, thereby achieving data sharing and fast exchange. This method is usually more efficient than exchanging data through files, pipes or message queues, because data does not need to be copied between multiple cores, which can reduce memory usage and data transmission overhead.

[0051] In step 102, the data sending core triggers an inter-core interrupt on a target channel; wherein the target channel is any channel in an inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function.

[0052] Here, the inter-core communication link between the data sending core and the data receiving core includes multiple channels, and the data sending core can select any one of the channels (named as the target channel) to trigger an inter-core interrupt. Each channel in the inter-core communication link is configured with a receiving response function, where each receiving response function corresponds to a communication type, so that multiple communication types can be supported.

[0053] It is worth noting that an inter-processor interrupt (IPI) is a mechanism for inter-core communication, which allows one core to send an inter-core interrupt signal to other cores so that the core receiving the inter-core interrupt signal performs a specific operation, thereby realizing a complex task scheduling and synchronization mechanism. The inter-core interrupt involved in the embodiments of the present application may refer to a hard interrupt (hardirq) or a soft interrupt (softirq), which is not limited to this.

[0054] In some embodiments, the data transmission core can select a corresponding receiving response function according to the data type of the target data, and trigger an inter-core interrupt on the channel configured with the receiving response function. The corresponding relationship between the data type and the receiving response function can be preset according to the actual application scenario.

[0055] In step 103, the data receiving core responds to the inter-core interrupt triggered on the target channel and calls the receiving response function configured on the target channel to receive the target data in the target shared memory.

[0056] Here, when the data receiving core receives the inter-core interrupt triggered on the target channel, the data receiving core calls the receiving response function configured by the target channel to receive the target data in the target shared memory, thereby ensuring the smooth delivery of the target data.

[0057] In some embodiments, each channel can be configured with a pointer to a receive response function instead of a function name. Based on this, the data receiving core calls the receive response function through the pointer to the receive response function configured by the target channel, which can greatly enhance flexibility and versatility.

[0058] In some embodiments, the above-mentioned data receiving core can be implemented in the following manner: the data receiving core responds to the inter-core interrupt triggered on the target channel, calls the receiving response function configured on the target channel to receive the target data in the target shared memory: the data receiving core responds to the inter-core interrupt triggered on the target channel, calls the interrupt receiving function, and calls the receiving response function configured on the target channel in the interrupt receiving function to receive the target data in the target shared memory.

[0059] Here, when the data receiving core receives the inter-core interrupt triggered on the target channel, the interrupt receiving function is triggered by default, and the receiving response function configured by the target channel is called in the interrupt receiving function to receive the target data in the target shared memory. In this way, the orderliness of the data receiving core responding to the inter-core interrupt can be improved, and the receiving response function can be effectively called during the execution of the interrupt receiving function.

[0060] In some embodiments, before the data sending core stores the target data to the target shared memory, the inter-core communication method also includes: the data sending core applies for the target shared memory; after calling the receiving response function configured by the target channel to receive the target data in the target shared memory, the inter-core communication method also includes: the data receiving core releases the target shared memory.

[0061] Here, when the data sending core determines the target data to be sent, it can apply for a part of the memory as the target shared memory, thereby ensuring that the memory resources required for inter-core communication are available and correctly configured. After successfully receiving the target data in the target shared memory, the data receiving core can release the target shared memory, thus ensuring that the memory resources can be recovered in time for subsequent communication or other tasks, thereby avoiding memory leaks and improving the utilization of memory resources.

[0062] In some embodiments, the above-mentioned calling of the receiving response function configured by the target channel to receive the target data in the target shared memory can be implemented in the following manner: when the receiving response function configured by the target channel is a query response function, the query response function is called to implement the following processing: storing the data address of the target data in the target shared memory to the memory buffer corresponding to the target channel; sending the data address in the memory buffer to the application running in the data receiving core, so that the application receives the target data from the target shared memory according to the data address.

[0063] Here, taking the receiving response function configured by the target channel as a query response function as an example, the implementation mechanism of the query response function is explained.

[0064] First, the data address of the target data in the target shared memory is stored in the memory buffer corresponding to the target channel, where the data address may include the data first address and the byte length. A memory buffer may be pre-established for each channel, and the data structure used by the memory buffer is not limited in the embodiment of the present application. By storing the data address of the target data in the memory buffer, it is possible to avoid directly accessing the target shared memory each time the data arrives, thereby reducing the frequency of accessing the target shared memory and reducing system overhead; at the same time, the memory buffer can support the storage of data addresses of a large amount of data, which is suitable for inter-core communication scenarios where a large amount of data needs to be sent.

[0065] Then, the data address in the memory buffer is sent to the application program running in the data receiving core, so that the application program receives the target data from the target shared memory according to the data address, so that the application program can further apply the target data.

[0066] In some embodiments, the memory buffer is a ring queue buffer; when the data address of the target data in the target shared memory is stored in the memory buffer corresponding to the target channel, the inter-core communication method also includes: updating the write pointer of the ring queue buffer; before sending the data address in the memory buffer to the application running by the data receiving core, the inter-core communication method also includes: determining whether there is an unreceived data address in the ring queue buffer based on the write pointer and read pointer of the ring queue buffer; after sending the data address in the memory buffer to the application running by the data receiving core, the inter-core communication method also includes: updating the read pointer of the ring queue buffer.

[0067] Here, the memory buffer may be a ring queue buffer which adopts a First Input First Output (FIFO) data structure, which allows efficient storage and removal of data in a fixed-size buffer and manages data reading and writing operations through two pointers (a read pointer and a write pointer).

[0068] Based on this, when the data address of the target data in the target shared memory is stored in the memory buffer corresponding to the target channel, the write pointer of the circular queue buffer is updated, for example, the write pointer is increased by one, wherein the increase of the write pointer indicates that new data is written to the circular queue buffer. Then, according to the write pointer and the read pointer of the circular queue buffer, it is determined whether there is an unreceived data address in the circular queue buffer (here, it means that it is not received by the application program running by the data receiving core), wherein if the write pointer and the read pointer point to different positions in the circular queue buffer respectively, it is determined that there is an unreceived data address in the circular queue buffer; if the write pointer and the read pointer point to the same position in the circular queue buffer, it is determined that there is no unreceived data address in the circular queue buffer. Since the write pointer is updated in the above process, the write pointer and the read pointer point to different positions in the circular queue buffer respectively, and it is determined that there is an unreceived data address in the circular queue buffer, thereby triggering the sending of the unreceived data address in the memory buffer to the application program running by the data receiving core. After the application successfully receives the data address, the read pointer of the circular queue buffer is updated, for example, the read pointer is increased by one, wherein the increase of the read pointer indicates that the corresponding data in the circular queue buffer has been read.

[0069] The characteristic of the circular queue buffer is its circular structure, that is, when data is written to the end of the buffer, it will wrap around to the beginning of the buffer and continue writing, forming a closed loop. Therefore, the circular queue buffer is used in the embodiment of the present application to efficiently utilize the limited memory space, avoiding the problem of the traditional linear buffer needing to move data or allocate new memory after the data is filled.

[0070] In some embodiments, the above-mentioned calling of the receiving response function configured by the target channel to receive the target data in the target shared memory can be implemented in the following way: when the receiving response function configured by the target channel is an interrupt response function, the interrupt response function is called to implement the following processing: the data address of the target data in the target shared memory is sent to the application running in the data receiving core through a callback method, so that the application receives the target data from the target shared memory according to the data address.

[0071] Here, taking the receiving response function configured as an interrupt response function of the target channel as an example, the implementation mechanism of the interrupt response function is explained.

[0072] The interrupt response function is a callback function. When the interrupt response function is called, the data address of the target data in the target shared memory is sent to the application running in the data receiving core through a callback method, so that the application can receive the target data from the target shared memory according to the data address. In this way, the delay in the data receiving process can be significantly reduced, and the real-time processing of data is realized. This immediacy is particularly important for inter-core communication scenarios with high timeliness requirements, such as inter-core communication scenarios where the target data is abnormal information or restart information.

[0073] like Figure 3 As shown, the embodiment of the present application stores the target data to the target shared memory through the data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core; the inter-core interrupt is triggered in the target channel through the data sending core; wherein the target channel is any channel in the inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function; the data receiving core responds to the inter-core interrupt triggered in the target channel, and calls the receiving response function configured in the target channel to receive the target data in the target shared memory. The embodiment of the present application configures a receiving response function in each channel, so it can support multiple communication types; it can select a suitable receiving response function for inter-core communication according to actual needs, thereby enriching the applicable inter-core communication scenarios and promoting the platformization of inter-core communication technology.

[0074] In some embodiments, see Figure 4 , Figure 4 is a flow chart of the inter-core communication method provided in the embodiment of the present application, which will be combined with Figure 4 The steps shown are explained.

[0075] In step 201 , the main core closes the inter-core communication link between the main core and the restart core, and clears the shared memory between the main core and the restart core.

[0076] Here, a scenario in which a core in a multi-core processor needs to be restarted is taken as an example. For ease of explanation, the core that needs to be restarted is named a restart core.

[0077] The restart work of the restart core is usually implemented by the main core in the multi-core processor. When the main core receives the restart instruction for the restart core, it first closes the inter-core communication link between the main core and the restart core, and clears the shared memory between the main core and the restart core. The purpose of closing the inter-core communication link is to prohibit the inter-core communication between the main core and the restart core at the bottom layer, so as to avoid the main core sending untrusted data to the restart core or the restart core sending untrusted data to the main core due to the false triggering of the inter-core interrupt during the clearing of the shared memory, so as to ensure that the functions of the upper-layer application will not be abnormal; the purpose of clearing the shared memory is to prevent the expired data in the shared memory from affecting the functions of the upper-layer application.

[0078] It is worth noting that the releasing of shared memory involved in the embodiments of the present application refers to returning the memory resources allocated to the shared memory to the operating system so that these memory resources can be reused; clearing shared memory refers to clearing the contents stored in the shared memory, which means logically "resetting" the shared memory so that it can be reused and no longer contains any old data that may no longer be relevant, that is, clearing shared memory does not return the memory resources allocated to the shared memory to the operating system, but only changes the data in the shared memory.

[0079] It is worth noting that if the main core is the restart core, it is equivalent to restarting all the cores in the multi-core processor.

[0080] In step 202, the main core stores the restart information of the restart core in the target shared memory; wherein the target shared memory is shared by the main core and other cores, and the other cores are different from the restart core and the main core.

[0081] Step 201 can prohibit the inter-core communication between the main core and the restart core, but the inter-core communication between other cores and the restart core is still in progress. Therefore, similar to step 101, the main core stores the restart information of the restart core (i.e., the notification that the restart core needs to be restarted) to the target shared memory, where the target shared memory is shared by the main core and other cores, and other cores refer to any core except the main core and the restart core.

[0082] It is worth noting that in the restart scenario, the main core acts as the data sending core and the other cores act as the data receiving cores.

[0083] In step 203, the main core triggers an inter-core interrupt on a target channel; wherein the target channel is any channel in an inter-core communication link between the main core and other cores, and each channel is configured with a receiving response function.

[0084] Similar to step 102, the master core triggers an inter-core interrupt on the target channel, wherein the target channel may be a dedicated control information transmission channel.

[0085] In some embodiments, the target channel is configured with an interrupt response function. Since the timeliness requirement of the restart information is high and it needs to reach the data receiving core as much as possible, the interrupt response function can be configured in the target channel in advance, so as to realize efficient transmission of the restart information based on the real-time characteristics of the interrupt response function.

[0086] In step 204, in response to the inter-core interrupt triggered on the target channel, other cores call the receiving response function configured on the target channel to receive the restart information in the target shared memory.

[0087] When other cores receive the inter-core interrupt triggered on the target channel, they call the receiving response function (such as the interrupt response function) configured on the target channel to receive the restart information in the target shared memory.

[0088] In step 205, the other cores close the inter-core communication link between the other cores and the restarted core according to the restart information, and clear the shared memory between the other cores and the restarted core.

[0089] When other cores receive the restart information of the restart core, they know that the restart core needs to be restarted. Therefore, other cores close the inter-core communication link between other cores and the restart core, and clear the shared memory between other cores and the restart core.

[0090] In step 206, the main core restarts the restart core.

[0091] Through the above steps 201 to 205, all inter-core communication links related to the restarted core have been closed, and all shared memories related to the restarted core have been cleared. Therefore, the main core restarts the restarted core, which can improve the security of the restart process and avoid the restart process from causing adverse effects on upper-level applications.

[0092] In some embodiments, after the restart core is restarted by the main core, the inter-core communication method also includes: for any core different from the restart core, performing the following processing: reading the shared memory between any core and the restart core through any core; when the shared memory between any core and the restart core includes initialization information, opening the inter-core communication link between any core and the restart core.

[0093] If the restart core is successfully restarted, the restart core will write initialization information in the related shared memory, wherein the location of the initialization information in the shared memory is not limited, for example, it can be located in the shared memory header information; the specific content of the initialization information is not limited, and can be determined according to the actual communication protocol. For each core different from the restart core, the shared memory between the core and the restart core can be read, and when the shared memory between the core and the restart core includes initialization information, the inter-core communication link between the core and the restart core is opened for inter-core communication, wherein, considering that the time for the restart core to successfully restart is uncertain, the shared memory between the core and the restart core can be periodically read. In the above manner, after the restart core is successfully restarted, the inter-core communication link related to the restart core can be reopened, thereby automatically and efficiently restoring inter-core communication.

[0094] like Figure 4 As shown, before the restart core is restarted, the embodiment of the present application closes the inter-core communication link related to the restart core, thereby preventing the main core from sending untrusted data to the restart core or the restart core from sending untrusted data to the main core due to the false triggering of the inter-core interrupt during the clearing of the shared memory, ensuring that the functions of the upper-layer application will not be abnormal; at the same time, the shared memory related to the restart core is cleared, thereby preventing expired data in the shared memory from affecting the functions of the upper-layer application. After the restart core is successfully restarted, the inter-core communication link related to the restart core is opened, thereby automatically and efficiently restoring the inter-core communication.

[0095] The following is an explanation of an exemplary application of the embodiments of the present application in a practical application scenario.

[0096] In an embodiment of the present application, for each channel in the inter-core communication link, a pointer to the receive response function that the channel needs to use is configured, thereby realizing the characteristic receive response requirements of each channel, laying the foundation for expanding the functional service type. For the data sending core, the target data can be stored in the target shared memory, and the inter-core interrupt can be triggered on the target channel. For the data receiving core, in response to the inter-core interrupt triggered on the target channel, the interrupt receive function is called, the configuration of the target channel is queried in the interrupt receive function, and the corresponding receive response function is called through the pointer in the configuration, thereby receiving the target data in the target shared memory, wherein the interrupt receive function is a function bound to the inter-core interrupt.

[0097] In the embodiment of the present application, the receiving response function can be divided into two categories. One category is for the scenario of application query-type reception, called query-type response function, which is suitable for the situation where the timeliness requirement is not high but the data volume is large; the other category is for the scenario of application interruption-type reception, called interruption-type response function, which is suitable for the situation where the timeliness requirement is high, such as the situation where the target data is control information such as abnormal information or restart information. The following will describe these two categories of receiving response functions in detail.

[0098] 1. Query response function.

[0099] Here, for each channel configured with a query response function, a circular queue buffer of a certain size is set. In the process of the interrupt receiving function calling the query response function, the data address of the target data in the target shared memory is stored in the circular queue buffer, and the write pointer is marked as plus one. In the process of the application of the data receiving core actively calling the query response function, the pointer of the circular queue buffer is first checked to determine whether there is any unreceived (need to be read) data. If so, the unreceived data (i.e., the data address of the target data) is read, and the read pointer is marked as plus one, and then the target data is read from the target shared memory according to the read data address; if not, the target shared memory is released.

[0100] As an example, the present application embodiment provides the following Figure 5 The flowchart of inter-core communication based on query response function is shown in Figure 5 , explained in step form.

[0101] 1) The application of the data sending core calls the inter-core communication sending function (IpcfSrv_Send) to send the target data to the inter-core communication interface (IpcfSrv) of the data sending core. The inter-core communication interface is an interface open to the upper-layer application. Through the inter-core communication interface, the upper-layer application can be decoupled from the underlying inter-core communication driver (IPC drv). The upper-layer application only needs to modify the configuration parameters of the inter-core communication interface to achieve various inter-core communication requirements without modifying the underlying inter-core communication driver. The inter-core communication driver is used to directly operate shared memory and is also used to trigger and respond to inter-core interrupts.

[0102] 2) The inter-core communication interface of the data sending core calls the shared memory application function (ipc_shm_acquire_buf) to apply for the target shared memory for the target data.

[0103] 3) The inter-core communication interface of the data sending core calls the data storage function (IPCF_MemCpy) to store the target data in the requested target shared memory.

[0104] 4) The inter-core communication interface of the data sending core calls the inter-core communication function (ipc_shm_tx) to enable the inter-core communication driver of the data sending core to call the inter-core interrupt function (ipc_hw_irq_notify) to trigger the inter-core interrupt, where the inter-core interrupt can be a hardware interrupt.

[0105] 5) The inter-core communication driver of the data receiving core responds to the inter-core interrupt, calls the interrupt receiving function (ipc_shm_hardirq), and calls the query response function in the interrupt receiving function. Figure 5 In the example, the query response function includes two functions, IpcfSrv_Rx_Cb_Queue_polling and IpcfSrv_Setpoll. The IpcfSrv_Rx_Cb_Queue_polling function is called by the inter-core communication driver of the data receiving core to send the data address of the target data in the target shared memory to the IpcfSrv_Setpoll function; the IpcfSrv_Setpoll function is called by the inter-core communication interface of the data receiving core to store the data address of the target data in the target shared memory in the circular queue buffer, waiting for the application of the data receiving core to actively poll and read and release.

[0106] 2. Interrupt response function.

[0107] Here, in the process of the interrupt receiving function calling the interrupt response function, the data address of the target data in the target shared memory is sent to the application of the data receiving core through a callback method. After the application of the data receiving core reads the target data from the target shared memory according to the data address, the target shared memory can be released, thereby improving the utilization of memory resources.

[0108] As an example, the present application embodiment provides the following Figure 6 The flowchart of the inter-core communication based on the interrupt response function is shown in Figure 6 , explained in step form.

[0109] 1) The application of the data sending core calls the inter-core communication sending function (IpcfSrv_Send) to send the target data to the inter-core communication interface (IpcfSrv) of the data sending core.

[0110] 2) The inter-core communication interface of the data sending core calls the shared memory application function (ipc_shm_acquire_buf) to apply for the target shared memory for the target data.

[0111] 3) The inter-core communication interface of the data sending core calls the data storage function (IPCF_MemCpy) to store the target data in the requested target shared memory.

[0112] 4) The inter-core communication interface of the data sending core calls the inter-core communication function (ipc_shm_tx) to enable the inter-core communication driver of the data sending core to call the inter-core interrupt function (ipc_hw_irq_notify) to trigger the inter-core interrupt, where the inter-core interrupt can be a hardware interrupt.

[0113] 5) The inter-core communication driver of the data receiving core responds to the inter-core interrupt, calls the interrupt receiving function (ipc_shm_hardirq), and calls the interrupt response function (IpcfSrv_Rx_Cb_Queue_Callback) in the interrupt receiving function, where the interrupt response function is used to send the data address of the target data in the target shared memory to the application of the data receiving core through a callback.

[0114] 6) After the application of the data receiving core reads the target data from the target shared memory according to the data address, the inter-core communication interface of the data receiving core calls the shared memory release function (ipc_shm_release_buf) to release the target shared memory storing the target data.

[0115] In addition, the embodiment of the present application also performs shared memory management in a single-core restart scenario.

[0116] For example, before restarting the restart core, the main core closes the inter-core communication link between the main core and the restart core, clears the shared memory between the main core and the restart core, and at the same time, the main core also notifies other cores through the inter-core communication technology, so that other cores also close the inter-core communication link with the restart core and clear the shared memory with the restart core. The purpose of closing the inter-core communication link is to prohibit inter-core communication at the bottom layer, so as to avoid the transmission of untrusted data due to false triggering of inter-core interrupts during the clearing of shared memory, and ensure that the functions of the upper-layer application will not be abnormal; the purpose of clearing shared memory is to prevent expired data in the shared memory from affecting the functions of the upper-layer application.

[0117] After the main core restarts the restart core, each core different from the restart core periodically accesses the shared memory header information between the restart core through the inter-core communication driver to determine whether the inter-core communication driver of the restart core has completed initialization (whether the restart core has been successfully restarted). If a core reads the shared memory header information between the restart core and the restart core, including initialization information, it is determined that the inter-core communication driver of the restart core has completed initialization, so the inter-core communication link with the restart core is reopened. Among them, writing the initialization information to the shared memory header information of the restart core is the key control condition for opening the inter-core communication link, which indicates that the inter-core communication driver of the restart core has successfully completed initialization and has the conditions for normal inter-core communication. When this condition is not met, the inter-core communication link cannot be opened at will to prevent system function abnormalities due to inter-core communication failures.

[0118] As an example, the present application embodiment provides the following Figure 7The flowchart of the single-core restart scenario shown in FIG. 1 shows the interaction process between the master core, the restart core, and the slave core, where the slave core refers to any core other than the master core and the restart core. Figure 7 , explained in step form.

[0119] 1) The application of the main core calls the restart function (PowerMgrIf_RestartA53Clusters) to notify the power driver (PwrMgrIf) of the main core that the restart core (here taking the A53 core as an example) needs to be restarted. Among them, the power driver or power management unit is used to handle related issues of the restart core restart scenario.

[0120] 2) The power driver of the main core calls the inter-core communication prohibition function (IpcfSrv_BreakLink), so that the inter-core communication interface of the main core calls the inter-core communication link closing function (ipc_shm_free_instance), thereby closing the inter-core communication link between the main core and the restart core.

[0121] 3) The inter-core communication interface of the main core calls the local clearing function (IpcfSrv_ClearMem_Local) to clear the local (referring to the main core) shared memory.

[0122] 4) The power driver of the main core calls the peer clearing function (IpcfSrv_ClearMem_Remote) to clear the shared memory of the peer (referring to the restart core).

[0123] 5) The power driver of the master core calls the control information storage function (IpcfSrv_GetMapData) to store the restart information of the restart core into the target shared memory, where the target shared memory is shared by the master core and the slave core.

[0124] 6) The power driver of the main core calls the control information notification function (IpcfSrv_NotifyMapData) to trigger an inter-core interrupt on the target channel, where the target channel refers to a dedicated control information transmission channel, which is configured with a pointer to an interrupt response function (IpcfSrv_Rx_Cb_Map_Callback), where the interrupt response function is specifically used to transmit control information. Among them, the control information involved in the embodiment of the present application includes restart information, abnormal information, etc.

[0125] 7) The inter-core communication driver of the slave core responds to the inter-core interrupt, calls the interrupt receiving function (ipc_shm_hardirq), and calls the interrupt response function in the interrupt receiving function.

[0126] 8) The inter-core communication interface of the slave core calls the control information upload function (PowerMgrIfApp_PentaDead) to send the restart information of the restart core to the power driver of the slave core.

[0127] 9) The power driver of the slave core calls the inter-core communication disable function (IpcfSrv_BreakLink), thereby closing the inter-core communication link between the slave core and the restart core.

[0128] 10) Call the peer clearing function (IpcfSrv_ClearMem_Remote) from the core power driver to clear the peer (referring to the restarted core) shared memory.

[0129] 11) The main core restarts the restart core ( Figure 7 not shown).

[0130] 12) The inter-core communication interface of the master core and the inter-core communication interface of the slave core periodically call the check function (IpcfSrv_Proc_RemoteReset) to determine whether the restarted core has completed the restart. If the restart is completed, the inter-core communication link between the restarted core and the restarted core is opened.

[0131] The embodiments of the present application can at least achieve the following technical effects:

[0132] 1) It improves the shortcoming of traditional solutions that only support a single type of communication, and enriches the inter-core communication scenarios that can be supported by the inter-core communication driver.

[0133] 2) Effectively manage the shared memory in the single-core restart scenario, avoiding functional abnormalities caused by expired shared memory storage data and improving the security of inter-core communication.

[0134] 3) There is no need to modify the underlying inter-core communication driver, which promotes the platformization of inter-core communication technology, facilitates rapid porting on different multi-core chip platforms, supports application scenarios of different controller projects, and avoids the time cost caused by repeated development.

[0135] The following is a description of an exemplary structure of the inter-core communication device 155 provided in the embodiment of the present application implemented as a software module. In some embodiments, Figure 2As shown, the software modules stored in the inter-core communication device 155 of the memory 150 may include: a storage module 1551, used to store the target data to the target shared memory through the data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core; an inter-core interrupt module 1552, used to trigger an inter-core interrupt on the target channel through the data sending core; wherein the target channel is any channel in the inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function; a receiving module 1553, used to respond to the inter-core interrupt triggered on the target channel through the data receiving core, and call the receiving response function configured on the target channel to receive the target data in the target shared memory.

[0136] In some embodiments, the receiving module 1553 is also used to call the query response function to implement the following processing when the receiving response function configured for the target channel is a query response function: storing the data address of the target data in the target shared memory to the memory buffer corresponding to the target channel; sending the data address in the memory buffer to the application running in the data receiving core, so that the application receives the target data from the target shared memory according to the data address.

[0137] In some embodiments, the memory buffer is a circular queue buffer; the receiving module 1553 is also used to: update the write pointer of the circular queue buffer; the receiving module 1553 is also used to: determine whether there are unreceived data addresses in the circular queue buffer based on the write pointer and read pointer of the circular queue buffer; the receiving module 1553 is also used to: update the read pointer of the circular queue buffer.

[0138] In some embodiments, the receiving module 1553 is also used to call the interrupt response function to implement the following processing when the receiving response function configured for the target channel is an interrupt response function: the data address of the target data in the target shared memory is sent to the application running in the data receiving core through a callback method, so that the application receives the target data from the target shared memory according to the data address.

[0139] In some embodiments, the inter-core communication device 155 also includes a shared memory application module, which is used to: apply for target shared memory through the data sending core; the inter-core communication device 155 also includes a shared memory release module, which is used to: release the target shared memory through the data receiving core.

[0140] In some embodiments, the data sending core is the main core, the data receiving core is other cores different from the restart core and the main core, and the target data is the restart information of the restart core;

[0141] In some embodiments, the inter-core communication device 155 also includes a restart preparation module, which is used to: close the inter-core communication link between the main core and the restart core through the main core, and clear the shared memory between the main core and the restart core; close the inter-core communication link between other cores and the restart core according to the restart information through other cores, and clear the shared memory between other cores and the restart core; the inter-core communication device 155 also includes a restart module, which is used to: restart the restart core through the main core.

[0142] In some embodiments, the inter-core communication device 155 also includes an inspection module, which is used to perform the following processing for any core different from the restarted core: reading the shared memory between any core and the restarted core through any core; when the shared memory between any core and the restarted core includes initialization information, opening the inter-core communication link between any core and the restarted core.

[0143] An embodiment of the present application provides a multi-core processor, which includes executable instructions. The multi-core processor runs in an electronic device to implement the inter-core communication method described above in the embodiment of the present application.

[0144] An embodiment of the present application provides an electronic device, which includes a memory and a processor. The memory is used to store executable instructions, and the processor is used to execute the executable instructions stored in the memory to implement the above-mentioned inter-core communication method of the embodiment of the present application.

[0145] The embodiment of the present application provides a computer program product or a computer program, which includes executable instructions stored in a computer-readable storage medium. The processor of the electronic device reads the executable instructions from the computer-readable storage medium, and the processor executes the executable instructions, so that the electronic device implements the inter-core communication method described in the embodiment of the present application.

[0146] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, wherein executable instructions are stored. When the executable instructions are executed by a processor, the processor will implement the inter-core communication method provided by the embodiment of the present application.

[0147] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface storage, optical disk, or CD-ROM; or it may be various devices including one or any combination of the above memories.

[0148] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0149] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0150] As an example, the executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed at multiple sites and interconnected by a communication network.

[0151] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A method for inter-core communication, characterized in that: Applied to a multi-core processor; the method comprises: The target data is stored in the target shared memory through the data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core; triggering an inter-core interrupt on a target channel through the data sending core; wherein the target channel is any channel in an inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function; In response to the inter-core interrupt triggered by the target channel, the data receiving core calls a receiving response function configured by the target channel to receive the target data in the target shared memory.

2. The method according to claim 1, characterized in that The calling of the receiving response function configured by the target channel to receive the target data in the target shared memory includes: When the receiving response function configured by the target channel is a query response function, the query response function is called to implement the following processing: Storing the data address of the target data in the target shared memory into the memory buffer corresponding to the target channel; The data address in the memory buffer is sent to an application program running on the data receiving core, so that the application program receives the target data from the target shared memory according to the data address.

3. The method according to claim 2, characterized in that The memory buffer is a ring queue buffer; when the data address of the target data in the target shared memory is stored in the memory buffer corresponding to the target channel, the method further includes: Updating the write pointer of the circular queue buffer; Before sending the data address in the memory buffer to the application program running in the data receiving core, the method further includes: Determine, according to the write pointer and the read pointer of the circular queue buffer, that there is an unreceived data address in the circular queue buffer; After sending the data address in the memory buffer to the application program running in the data receiving core, the method further includes: The read pointer of the circular queue buffer is updated.

4. The method according to claim 1, characterized in that: The calling of the receiving response function configured by the target channel to receive the target data in the target shared memory includes: When the receiving response function configured by the target channel is an interrupt response function, the interrupt response function is called to implement the following processing: The data address of the target data in the target shared memory is sent to the application program running on the data receiving core in a callback manner, so that the application program receives the target data from the target shared memory according to the data address.

5. The method according to claim 1, characterized in that Before storing the target data into the target shared memory through the data sending core, the method further includes: Applying for the target shared memory through the data sending core; After calling the receiving response function configured by the target channel to receive the target data in the target shared memory, the method further includes: The target shared memory is released by the data receiving core.

6. The method according to any one of claims 1 to 5, characterized in that: The data sending core is a main core, the data receiving core is another core different from the restart core and the main core, and the target data is the restart information of the restart core; Before storing the target data into the target shared memory through the data sending core, the method further includes: Closing the inter-core communication link between the main core and the restart core through the main core, and clearing the shared memory between the main core and the restart core; After calling the receiving response function configured by the target channel to receive the target data in the target shared memory, the method further includes: Closing the inter-core communication link between the other cores and the restart core according to the restart information through the other cores, and clearing the shared memory between the other cores and the restart core; The method further comprises: The restart core is restarted by the main core.

7. The method according to claim 6, characterized in that After restarting the restart core by the main core, the method further includes: For any core different from the restarted core, perform the following processing: Reading a shared memory between the any one core and the restarted core through the any one core; When the shared memory between the any one core and the restarted core includes initialization information, an inter-core communication link between the any one core and the restarted core is enabled.

8. An inter-core communication device, characterized in that: Applied to a multi-core processor; the device comprises: A storage module, used for storing target data into a target shared memory through a data sending core; wherein the target shared memory is shared by the data sending core and the data receiving core; An inter-core interrupt module, used to trigger an inter-core interrupt on a target channel through the data sending core; wherein the target channel is any channel in the inter-core communication link between the data sending core and the data receiving core, and each channel is configured with a receiving response function; The receiving module is used to respond to the inter-core interrupt triggered on the target channel through the data receiving core, and call the receiving response function configured on the target channel to receive the target data in the target shared memory.

9. A multi-core processor, characterized in that: The multi-core processor includes executable instructions, and the multi-core processor runs in an electronic device to implement the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: A memory for storing executable instructions; A processor, configured to implement the method according to any one of claims 1 to 7 when executing the executable instructions stored in the memory.

11. A computer-readable storage medium, characterized in that: Executable instructions are stored, and when executed by a processor, the method described in any one of claims 1 to 7 is implemented.

12. A computer program product, characterized in that The method comprises executable instructions for implementing the method according to any one of claims 1 to 7 when executed by a processor.

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