Cyclic redundancy check circuit, method and medium
By designing a cyclic redundant verification circuit, the problem of lack of error verification in low-speed serial port data transmission is solved, and the data checksum verification code generation in UART protocol communication is realized, avoiding unexpected interrupts in the data reception process.
Patent Information
- Application Number
- CN202411209922.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2024-12-31
AI Technical Summary
In the prior art, there is a lack of error verification in low-speed serial port data transmission, which makes it impossible to use multiple serial port frames for data transmission, and the same cyclic redundancy verification code may lead to unexpected interrupts.
A cyclic redundant verification circuit is designed, including a trigger control module, a verification code generation module and a verification module. Through the clock input unit, a data processing circuit, an exclusive-or logic circuit and a multi-level cache unit, the UART data is realized. Preprocessing, verification code generation and verification calculation to avoid interrupts caused by the same data and verification code.
Without the need for CPU participation, cyclic redundancy verification of UART protocol communication data with uncertain frames is completed, data reception, cyclic redundancy verification code generation, data source verification and verification result output is achieved, avoiding the Unexpected interruption during data reception.
Smart Images
Figure CN119226027A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of data communication technology, and in particular to a cyclic redundancy check circuit, method and medium. Background Art
[0002] Cyclic redundancy check is a commonly used error checking method in the field of data communication, which is used to detect whether data is damaged or bit errors occur during data transmission. In the data transmission of key interfaces, it is necessary to ensure the correct transmission of data or instructions. Taking the low-speed serial port as an example, there is no error checking design in the original protocol, which makes it impossible to use multiple serial port frames for data transmission. Summary of the invention
[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a cyclic redundancy check circuit, method and medium, which can avoid the cyclic redundancy check process from being accidentally interrupted due to the data and the cyclic redundancy check code being the same during the data receiving process.
[0004] In a first aspect, an embodiment of the present invention provides a cyclic redundancy check circuit, comprising:
[0005] A trigger control module is used to receive UART data and pre-process the UART data to obtain pre-processed data;
[0006] A check code generation module, electrically connected to the trigger control module, and configured to generate a check code corresponding to the preprocessed data;
[0007] A verification module is electrically connected to the trigger control module and the verification code generation module respectively, and is used to perform verification calculation on the verification code. The verification module is provided with a cache unit and a comparison logic unit. The input end of the cache unit is electrically connected to the verification code generation module, the first output end of the cache unit is electrically connected to the trigger control module, and the second output end of the cache unit is electrically connected to the comparison logic unit. The cache unit is used to output a register return value to the trigger control module according to the verification code generation module. The first input end of the comparison logic unit is connected to the second output end of the cache unit, and the second input end of the comparison logic unit is connected to the trigger control module.
[0008] In some embodiments of the present invention, the trigger control module includes:
[0009] A clock input unit, wherein the clock input unit receives clock frequency division and serial data according to a preset baud rate preset value;
[0010] A first data processing circuit, electrically connected to the clock input unit, for performing parallel processing on the serial data;
[0011] an inversion circuit, electrically connected to the data processing circuit, and used for performing big-endian and small-endian inversion on the serial data after parallel processing;
[0012] The first XOR logic circuit is electrically connected to the inversion circuit and is used to perform an XOR operation on the serial data according to the register value to obtain pre-processed data.
[0013] In some embodiments of the present invention, the check code generation module is provided with a plurality of check code generation units connected in sequence, the check code generation unit comprises a shift logic circuit, a second XOR logic circuit and a second data processing circuit, the input end of the shift logic circuit is electrically connected to the trigger control module, the first output end and the second output end of the shift logic circuit are both connected to the second data processing circuit, the third output end of the shift logic circuit is connected to the input end of the second XOR logic circuit, and the output end of the second XOR logic circuit is connected to the second data processing circuit, when the check code generation unit is the first one among the plurality of check code generation units, the shift logic circuit is used to receive the preprocessed data, the second data processing circuit is used to generate a valid flag, and the highest bit of the preprocessed data is determined according to the generated flag to form cyclic data, when the check code generation unit is the middle check code generation unit, the shift logic circuit is used to receive the cyclic data, and when the check code generation unit is the last check code generation unit, the second data processing circuit is used to generate a check code.
[0014] In some embodiments of the present invention, the verification module includes a multi-level cache unit, a comparison logic unit and an AND logic circuit, the input end of the multi-level cache unit is connected to the verification code generation module, the first output end of the multi-level cache unit outputs the registered return value to the trigger control module, the second output end of the multi-level cache unit is connected to the input end of the comparison logic unit, and the output end of the comparison logic unit is connected to the AND logic circuit.
[0015] In some embodiments of the present invention, the multi-level cache unit is provided with a first cache circuit, a second cache circuit and a third cache circuit, and the comparison logic unit is provided with a first comparison logic circuit and a second comparison logic circuit, the input end of the first cache circuit is connected to the verification code generation module, the first output end of the first cache circuit is connected to the trigger control module, the second output end of the first cache circuit is connected to the input end of the second cache circuit, the first output end of the second cache circuit is connected to the input end of the third cache circuit, the second output end of the second cache circuit is connected to the first input end of the first comparison logic circuit, the second input end of the first comparison logic circuit and the first input end of the second comparison logic circuit are both connected to the trigger control module, the output end of the third cache circuit is connected to the second input end of the second comparison logic circuit, and the output ends of the first comparison logic circuit and the second comparison logic circuit are both connected to the logic circuit.
[0016] In a second aspect, an embodiment of the present invention provides a cyclic redundancy check method, comprising:
[0017] The trigger control module receives the UART data and pre-processes the UART data to obtain pre-processed data;
[0018] The check code generation module obtains a valid flag of the preprocessed data, determines an extreme value of the preprocessed data according to the valid flag, and obtains a redundant check code calculation result;
[0019] The current redundant check code calculation result is stored, and a first clock cycle, a second clock cycle, and a third clock cycle are obtained, wherein the check module obtains a comparison result of valid data according to the first clock cycle, the second clock cycle, and the third clock cycle;
[0020] All cache registers are cleared according to the comparison result.
[0021] In some embodiments of the present invention, the preprocessing data determines the extreme value of the preprocessing data according to the valid flag to obtain the redundant check code calculation result, including:
[0022] When the extreme value is 1, the extreme value is shifted left by one bit and XORed with the check code generation module;
[0023] When the extreme value is 0, the extreme value is shifted left by one bit and saved as second-level data. The extreme value is cyclically calculated eight times to obtain eighth-level data, and the eighth-level data is the calculation result of the redundant check code.
[0024] In some embodiments of the present invention, the verification module obtains a comparison result of valid data according to the first clock cycle, the second clock cycle, and the third clock cycle, including:
[0025] The first cache register stores the current redundancy check code calculation result and the first clock cycle;
[0026] The second cache register stores a first comparison result between the content of the first cache register in the first clock cycle and the high bit of the current content of the second cache register and the first valid data currently received by the second cache register in the second clock cycle;
[0027] The third cache register stores the content of the first cache register in the second clock cycle, the comparison result of the high bit of the content of the second cache register in the second clock cycle with the first valid data received in the second clock cycle data receiving step and the current low bit of the third cache register content, and the second comparison result of the second valid data received in the third clock cycle is sent to the trigger control module.
[0028] In some embodiments of the present invention, after the comparison result of the second valid data received in the third clock cycle is sent to the trigger control module, the method further includes:
[0029] When the third buffer register receives the second valid data, the calculation result of the redundant check code in the first buffer is sent to the trigger control module to perform continuous calculation of the next frame;
[0030] The trigger control module outputs the second comparison result according to a preset end flag or an input timeout flag;
[0031] After outputting the second comparison result, the first cache register, the second cache register and the third cache register are cleared.
[0032] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the cyclic redundancy check method as described in the second aspect above.
[0033] The cyclic redundancy check circuit according to the embodiment of the present invention has at least the following beneficial effects:
[0034] The trigger control module is used to receive UART data, preprocess the UART data, and obtain preprocessed data; the check code generation module is electrically connected to the trigger control module, and is used to generate a check code corresponding to the preprocessed data; the check module is electrically connected to the trigger control module and the check code generation module, and is used to perform a check calculation on the check code. The check module is provided with a cache unit and a comparison logic unit, the input end of the cache unit is electrically connected to the check code generation module, the first output end of the cache unit is electrically connected to the trigger control module, the second output end of the cache unit is electrically connected to the comparison logic unit, the cache unit is used to output the register return value to the trigger control module according to the check code generation module, the first input end of the comparison logic unit is connected to the second output end of the cache unit, and the second input end of the comparison logic unit is connected to the trigger control module. According to the technical solution of this embodiment, the cyclic redundancy check of UART protocol communication data with an indefinite number of frames can be completed without the participation of the CPU, and the functions of data reception, cyclic redundancy check code generation, data source verification and verification result output can be realized. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 is an overall structural block diagram of a cyclic redundancy check circuit provided by an embodiment of the present invention;
[0036] Figure 2 is a structural block diagram of a trigger control module provided by an embodiment of the present invention;
[0037] Figure 3 is a structural block diagram of a verification code generation module provided by an embodiment of the present invention;
[0038] Figure 4 is a structural block diagram of a verification module provided by an embodiment of the present invention;
[0039] Figure 5 is a flow chart of a cyclic redundancy check method provided by an embodiment of the present invention;
[0040] Figure 6 is a flow chart of obtaining a redundant check code calculation result provided by an embodiment of the present invention;
[0041] Figure 7 is a flow chart of obtaining result information of valid data provided by an embodiment of the present invention;
[0042] Figure 8 This is a flow chart provided by an embodiment of the present invention after the comparison result of the second valid data received in the third clock cycle is sent to the trigger control module.
[0043] Reference numerals:
[0044] Trigger control module 100; clock input unit 110; first data processing circuit 120; inversion circuit 130; first XOR logic circuit 140; check code generation module 200; check code generation unit 210; shift logic circuit 211; second XOR logic circuit 212; second data processing circuit 213; check module 300; cache unit 310; first cache circuit 311; second cache circuit 312; third cache circuit 313; comparison logic unit 320; first comparison logic circuit 321; second comparison logic circuit 322. DETAILED DESCRIPTION
[0045] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0046] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.
[0047] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.
[0048] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.
[0049] Reference Figure 1The embodiment of the present invention provides a cyclic redundancy check circuit, including a trigger control module 100, which is used to receive UART data, pre-process the UART data, and obtain pre-processed data; a check code generation module 200, which is electrically connected to the trigger control module 100, and is used to generate a check code corresponding to the pre-processed data; a check module 300, which is electrically connected to the trigger control module 100 and the check code generation module 200, and is used to perform a check calculation on the check code. The check module 300 is provided with a cache unit 310 and a comparison logic unit 320, the input end of the cache unit 310 is electrically connected to the check code generation module 200, the first output end of the cache unit 310 is electrically connected to the trigger control module 100, the second output end of the cache unit 310 is electrically connected to the comparison logic unit 320, the cache unit 310 is used to output a register return value to the trigger control module 100 according to the check code generation module 200, the first input end of the comparison logic unit 320 is connected to the second output end of the cache unit 310, and the second input end of the comparison logic unit 320 is connected to the trigger control module 100.
[0050] It should be noted that the cyclic redundancy check circuit is integrated in the FPGA chip. The FPGA chip is connected to the host computer, and the host computer program inputs data through the serial port and generates the circuit required for the check code, and continuously outputs the check result.
[0051] The clock frequency division and serial data reception are completed by triggering the control module 100, and the serial data is processed in parallel and then the big and small ends are reversed. At the same time, an XOR operation is performed according to the register value of the check module 300, thereby obtaining preprocessed data. The check code generation module 200 receives the preprocessed data and the valid flag to determine the highest bit of the data and forms the next level of data. After multiple cycles, the redundant cyclic check code calculation result is finally obtained, and the calculation result is input to the check module 300. According to the circuit structure of this embodiment, through the multi-stage cyclic calculation of the check code generation module 200, the integrated control module in the PFGA chip is omitted, and the cyclic redundancy check of UART data with an indefinite number of frames can be completed and the result can be output without the CPU participating in the calculation. At the same time, the end valid flag and the input timeout flag are used to check the cache register to avoid the accidental interruption caused by the same data and cyclic redundancy check code during the data reception process.
[0052] Reference Figure 1 and Figure 2The trigger control module 100 includes a clock input unit 110, which receives clock division and serial data according to a preset baud rate preset value; a first data processing circuit 120, which is electrically connected to the clock input unit 110 and is used to perform parallel processing on the serial data; an inversion circuit 130, which is electrically connected to the data processing circuit and is used to invert the serial data after parallel processing; a first XOR logic circuit 140, which is electrically connected to the inversion circuit 130 and is used to perform an XOR operation on the serial data according to the register value to obtain preprocessed data.
[0053] It should be noted that the clock input unit 110 generates and distributes a clock signal according to a preset baud rate. The clock signal is used to synchronize the data stream and processing logic in the entire CRC circuit. The clock is divided so that the clock input unit 110 can ensure that the UART data is sampled and processed at a preset time, and simultaneously process the reception of the serial data stream; the first data processing circuit 120 is electrically connected to the clock input unit 110, and is used to convert the received serial data stream into parallel data, so that subsequent steps such as data flipping and XOR operations can be performed efficiently; by flipping the serial data, the UART is ensured to be The consistency of data during the CRC verification process can avoid verification errors caused by inconsistent byte order; the first XOR logic circuit 140 is electrically connected to the inversion circuit 130, and the flipped UART data is XORed through the preset register value in the cache unit 310. The XOR operation is the core step in the CRC verification. Based on the polynomial principle, the data verification code is generated. Through the XOR operation, the first XOR logic circuit 140 can detect errors that may occur during data transmission (such as bit flipping and data loss, etc.), and generate a unique verification code, which is transmitted together with the UART data.
[0054] Reference Figure 1 , Figure 2 and Figure 3The check code generation module 200 is provided with a plurality of check code generation units 210 connected in sequence, and the check code generation unit 210 includes a shift logic circuit 211, a second XOR logic circuit 212 and a second data processing circuit 213. The input end of the shift logic circuit 211 is electrically connected to the trigger control module 100, the first output end and the second output end of the shift logic circuit 211 are both connected to the second data processing circuit 213, the third output end of the shift logic circuit 211 is connected to the input end of the second XOR logic circuit 212, and the output end of the second XOR logic circuit 212 is connected to the second The data processing circuit 213 is connected. When the check code generation unit 210 is the first one among multiple check code generation units 210, the shift logic circuit 211 is used to receive preprocessed data, and the second data processing circuit 213 is used to generate a valid flag, and the highest bit of the preprocessed data is determined according to the generated flag to form cyclic data. When the check code generation unit 210 is an intermediate check code generation unit 210, the shift logic circuit 211 is used to receive cyclic data, and when the check code generation unit 210 is a terminal check code generation unit 210, the second data processing circuit 213 is used to generate a check code.
[0055] It should be noted that the check code generation module 200 completes the CRC16 algorithm calculation of the data pre-processed by the trigger control circuit through shift logic and XOR logic to generate the corresponding cyclic redundancy check code. The CRC16 algorithm specifically includes judging the highest bit after the first-level data processing. If the highest bit is 1, it is shifted left by one bit and XORed with the CRC polynomial. If the highest bit is 0, it is shifted left by one bit and maintained to form the second-level data. The calculation is repeated eight times. After the cyclic operation, the eighth-level data is obtained as the final calculation result and is passed to the check module 300.
[0056] Reference Figure 4 The verification module 300 includes a multi-level cache unit 310, a comparison logic unit 320 and an AND logic circuit. The input end of the multi-level cache unit 310 is connected to the verification code generation module 200, the first output end of the multi-level cache unit 310 outputs the registered return value to the trigger control module 100, the second output end of the multi-level cache unit 310 is connected to the input end of the comparison logic unit 320, and the output end of the comparison logic unit 320 is connected to the AND logic circuit.
[0057] It should be noted that the multi-level cache unit 310 is used to store multiple versions of the verification code and pre-processed data. By setting the multi-level cache unit 310, it can be ensured that the pre-processed data after multi-level operations can be effectively saved and accessed; the comparison logic unit 320 is used to compare the received pre-processed data and the verification code; and the logic circuit is used to receive the data results of the comparison logic unit 320 or the verification results of the remaining modules, and the multiple verification results are integrated by performing a logical AND operation on the input signal. Only when all input signals pass the verification, the final verification result is output. Furthermore, the multi-level cache unit 310 and the comparison logic unit 320 can be adjusted and optimized according to the actual verification requirements to adapt to different verification requirements and scenarios.
[0058] Reference Figure 4 The multi-level cache unit 310 is provided with a first cache circuit 311, a second cache circuit 312 and a third cache circuit 313, and the comparison logic unit 320 is provided with a first comparison logic circuit 321 and a second comparison logic circuit 322. The input end of the first cache circuit 311 is connected to the check code generation module 200, the first output end of the first cache circuit 311 is connected to the trigger control module 100, the second output end of the first cache circuit 311 is connected to the input end of the second cache circuit 312, the first output end of the second cache circuit 312 is connected to the input end of the third cache circuit 313, the second output end of the second cache circuit 312 is connected to the first input end of the first comparison logic circuit 321, the second input end of the first comparison logic circuit 321 and the first input end of the second comparison logic circuit 322 are both connected to the trigger control module 100, the output end of the third cache circuit 313 is connected to the second input end of the second comparison logic circuit 322, and the output ends of the first comparison logic circuit 321 and the second comparison logic circuit 322 are both connected to the logic circuit.
[0059] It should be noted that, through the setting of the first cache circuit 311, the second cache circuit 312 and the third cache circuit 313, the data is cached and transmitted step by step, thereby reducing the delay of the data in the transmission process. Since the first cache circuit 311 is directly connected to the check code generation module 200, it is ensured that the data is cached together with the check code in the initial stage, which provides a basis for the subsequent data integrity check and helps to immediately discover and correct errors that may occur in the data transmission or storage process; the first comparison logic circuit 321 and the second comparison logic circuit 322 receive data from different cache stages and the model of the trigger control module 100, respectively, to achieve multiple verification of the data, ensure the flexibility and accuracy of the verification, and reduce unnecessary hardware redundancy, thereby ensuring the performance of the cyclic redundancy circuit while reducing the overall complexity and cost. In addition, through the parallel processing of multiple multi-level circuits, the resource utilization is further improved.
[0060] The cyclic redundancy check method according to the embodiment of the present invention is further described below based on the accompanying drawings.
[0061] Reference Figure 5 , Figure 5 A flowchart of a cyclic redundancy check method provided by an embodiment of the present invention, the cyclic redundancy check method includes but is not limited to the following steps:
[0062] Step S11, triggering the control module to receive UART data, preprocessing the UART data to obtain preprocessed data;
[0063] It should be noted that clock division and serial data reception are completed through the preset clock input and baud rate, the serial data is processed in parallel to complete the big and small endian inversion, and the register value of the feedback check module is completed with the XOR operation to obtain the processed data.
[0064] Step S12, the check code generation module obtains the valid flag of the preprocessed data, determines the extreme value of the preprocessed data according to the valid flag, and obtains the redundant check code calculation result;
[0065] It should be noted that this embodiment uses a digital circuit to implement the CRC16 algorithm. The preprocessing data and the valid flag are obtained through data reception, i.e., the preprocessing step, and the highest bit of the processed data is determined. The next level of data is formed through calculation. The eighth level data obtained after eight cycles is the final cyclic redundancy check code calculation result.
[0066] Step S13, storing the current redundancy check code calculation result, obtaining the first clock cycle, the second clock cycle and the third clock cycle, and the check module obtains the comparison result of the valid data according to the first clock cycle, the second clock cycle and the third clock cycle;
[0067] It should be noted that in hardware implementation, CRC verification is usually completed by processing data bit by bit through a shift register. After each clock cycle, the register will move one bit of data and perform corresponding AND logic operations based on the current data bit and the generated polynomial. The first clock cycle, the second clock cycle, and the third clock cycle represent different stages in the CRC polynomial calculation process. In different clock cycles, the hardware performs different specific operations (such as checking the most significant bit, performing XOR operations, shifting, etc.) to advance the CRC calculation process. At the receiving end, when all data bits have been processed and the CRC calculation is completed, the hardware will compare the calculated check code with the received check code and perform data processing based on the comparison result. This improves the reliability of data transmission, reduces error detection costs, and improves traffic efficiency.
[0068] Step S14, obtaining an end flag and a timeout flag, and clearing all cache registers according to the comparison result, the end flag and the timeout flag.
[0069] It should be noted that when the end flag is valid or the input timeout is valid, the comparison result is output. The output result is the result of the third buffer performing a logic operation on the high and low bit comparison results. After the output is completed, all cache registers are cleared. By clearing the registers in a timely manner, the consistency and accuracy of the data are ensured. Avoid errors and failures caused by outdated or inconsistent data in the cache. Clearing the cache registers can reduce the internal resource usage and potential conflicts of the FPGA chip. When a timeout or error is detected, further error propagation and resource waste can be avoided by clearing the relevant cache, thereby improving the stability and reliability of the cyclic redundancy circuit.
[0070] It should be noted that this embodiment can complete the cyclic redundancy check and output the result of UART received data of an indefinite number of frames without the CPU participating in the calculation, and at the same time clear the cache register through the end valid flag and the input timeout flag to avoid accidental interruption caused by the same data and cyclic redundancy check code during the data reception process.
[0071] In addition, in one embodiment, referring to Figure 6 ,exist Figure 5 Step S12 of the illustrated embodiment also includes but is not limited to the following steps:
[0072] Step S21, when the extreme value is 1, the extreme value is shifted left by one bit and XORed with the check code generation module;
[0073] Step S22, when the extreme value is 0, the extreme value is shifted left by one bit and saved as the second-level data. The extreme value is cyclically calculated eight times to obtain the eighth-level data, which is the calculation result of the redundant check code.
[0074] It should be noted that the data and valid flag are obtained through data reception and preprocessing steps, and the highest bit of the data is judged. If it is 1, it is shifted left by one bit and XORed with the CRC polynomial. If it is 0, it is shifted left by one bit and maintained to form the next level of data. The calculation is repeated eight times, and the eighth level data obtained is the final cyclic redundancy check code calculation result.
[0075] In addition, in one embodiment, referring to Figure 7 ,exist Figure 5 Step S13 of the illustrated embodiment also includes but is not limited to the following steps:
[0076] Step S31, the first cache register stores the current redundancy check code calculation result and the first clock cycle;
[0077] Step S32, the second cache register stores a first comparison result between the first cache register content in the first clock cycle and the high bit of the current second cache register content and the first valid data currently received by the second cache register in the second clock cycle;
[0078] Step S33, the third cache register stores the first cache register content in the second clock cycle, the high bit of the second cache register content in the second clock cycle, the comparison result of the first valid data received in the second clock cycle data receiving step and the low bit of the current third cache register content, and the second comparison result of the second valid data received in the third clock cycle is sent to the trigger control module.
[0079] It should be noted that by storing data and verification results of different clock cycles in multiple cache registers, the integrity and correctness of the data can be monitored and verified in real time. The check code, comparison result and further processing result of the current clock cycle are stored in the first, second and third cache registers respectively, so that the check code generation module can immediately obtain the latest check and comparison information at the end of each clock cycle. The second cache register not only stores the comparison result of the first clock cycle, but also combines the high bit of the current second cache register content with the newly received valid data for comparison, which increases the depth and complexity of data processing and helps to detect potential data errors more comprehensively. At the end of the third clock cycle, the comparison result of the second valid data is sent to the trigger control module, which can simplify the design and implementation of the trigger control logic. The trigger control module can decide whether to trigger further data processing, error handling or system response operations based on these comparison results.
[0080] In addition, in one embodiment, referring to Figure 8 ,exist Figure 7 Step S33 of the illustrated embodiment also includes but is not limited to the following steps:
[0081] Step S41, when the third buffer register receives the second valid data, the redundant check code calculation result in the first buffer is sent to the trigger control module to perform continuous calculation of the next frame;
[0082] Step S42, triggering the control module to output a second comparison result according to a preset end flag or input timeout flag;
[0083] Step S43, after outputting the second comparison result, clearing the first cache register, the second cache register and the third cache register.
[0084] It should be noted that by sending the redundant check code calculation result in the first buffer to the trigger control module in a timely manner, the system can seamlessly transition to the processing of the next frame of data. This continuous operation capability reduces processing delays and improves the overall processing efficiency of the system. After outputting the second comparison result, the first, second and third cache registers are cleared, which helps to release system resources and avoid performance bottlenecks caused by excessive resource occupation. At the same time, clearing the cache register also provides a clean environment for subsequent data processing, avoiding interference from old data and potential errors. By clearing the cache register after each key step, the system reduces the risk of data conflicts and errors. For example, when processing multiple frames of data continuously, if the cache register is not cleared in time, confusion and errors between new and old data may occur. Clearing the cache register ensures the independence and accuracy of each frame of data.
[0085] An embodiment of the present application further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned cyclic redundancy check method is implemented.
[0086] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.
[0087] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media generally include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
[0088] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions under the shared conditions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.
Claims
1. A cyclic redundancy check circuit, characterized in that: include: A trigger control module is used to receive UART data and pre-process the UART data to obtain pre-processed data; A check code generation module, electrically connected to the trigger control module, and configured to generate a check code corresponding to the preprocessed data; A verification module is electrically connected to the trigger control module and the verification code generation module respectively, and is used to perform verification calculations on the verification code. The verification module is provided with a cache unit and a comparison logic unit. The input end of the cache unit is electrically connected to the verification code generation module, the first output end of the cache unit is electrically connected to the trigger control module, and the second output end of the cache unit is electrically connected to the comparison logic unit. The cache unit is used to output a register return value to the trigger control module according to the verification code generation module. The first input end of the comparison logic unit is connected to the second output end of the cache unit, and the second input end of the comparison logic unit is connected to the trigger control module.
2. The cyclic redundancy check circuit according to claim 1, characterized in that: The trigger control module comprises: A clock input unit, wherein the clock input unit receives clock frequency division and serial data according to a preset baud rate preset value; A first data processing circuit, electrically connected to the clock input unit, for performing parallel processing on the serial data; an inversion circuit, electrically connected to the data processing circuit, and used for performing big-endian and small-endian inversion on the serial data after parallel processing; The first XOR logic circuit is electrically connected to the inversion circuit and is used to perform an XOR operation on the serial data according to the register value to obtain pre-processed data.
3. The cyclic redundancy check circuit according to claim 1, characterized in that: The check code generation module is provided with a plurality of check code generation units connected in sequence, and the check code generation unit includes a shift logic circuit, a second XOR logic circuit and a second data processing circuit. The input end of the shift logic circuit is electrically connected to the trigger control module, the first output end and the second output end of the shift logic circuit are both connected to the second data processing circuit, the third output end of the shift logic circuit is connected to the input end of the second XOR logic circuit, and the output end of the second XOR logic circuit is connected to the second data processing circuit. When the check code generation unit is the first one among the plurality of check code generation units, the shift logic circuit is used to receive the preprocessed data, and the second data processing circuit is used to generate a valid flag, and the highest bit of the preprocessed data is determined according to the generated flag to form cyclic data. When the check code generation unit is the middle check code generation unit, the shift logic circuit is used to receive the cyclic data, and when the check code generation unit is the last check code generation unit, the second data processing circuit is used to generate a check code.
4. The cyclic redundancy check circuit according to claim 1, characterized in that: The verification module includes a multi-level cache unit, a comparison logic unit and an AND logic circuit. The input end of the multi-level cache unit is connected to the verification code generation module, the first output end of the multi-level cache unit outputs the registered return value to the trigger control module, the second output end of the multi-level cache unit is connected to the input end of the comparison logic unit, and the output end of the comparison logic unit is connected to the AND logic circuit.
5. The cyclic redundancy check circuit according to claim 4, characterized in that: The multi-level cache unit is provided with a first cache circuit, a second cache circuit and a third cache circuit, and the comparison logic unit is provided with a first comparison logic circuit and a second comparison logic circuit, the input end of the first cache circuit is connected to the verification code generation module, the first output end of the first cache circuit is connected to the trigger control module, the second output end of the first cache circuit is connected to the input end of the second cache circuit, the first output end of the second cache circuit is connected to the input end of the third cache circuit, the second output end of the second cache circuit is connected to the first input end of the first comparison logic circuit, the second input end of the first comparison logic circuit and the first input end of the second comparison logic circuit are both connected to the trigger control module, the output end of the third cache circuit is connected to the second input end of the second comparison logic circuit, and the output ends of the first comparison logic circuit and the second comparison logic circuit are both connected to the logic circuit.
6. A cyclic redundancy check method, characterized in that: include: The trigger control module receives the UART data and pre-processes the UART data to obtain pre-processed data; The check code generation module obtains a valid flag of the preprocessed data, determines an extreme value of the preprocessed data according to the valid flag, and obtains a redundant check code calculation result; The current redundant check code calculation result is stored, and a first clock cycle, a second clock cycle, and a third clock cycle are obtained, wherein the check module obtains a comparison result of valid data according to the first clock cycle, the second clock cycle, and the third clock cycle; All cache registers are cleared according to the comparison result.
7. The cyclic redundancy check method according to claim 6, characterized in that: The preprocessed data determines the extreme value of the preprocessed data according to the valid flag to obtain a redundant check code calculation result, including: When the extreme value is 1, the extreme value is shifted left by one bit and XORed with the check code generation module; When the extreme value is 0, the extreme value is shifted left by one bit and saved as second-level data. The extreme value is cyclically calculated eight times to obtain eighth-level data, and the eighth-level data is the calculation result of the redundant check code.
8. The cyclic redundancy check method according to claim 6, characterized in that: The verification module obtains a comparison result of valid data according to the first clock cycle, the second clock cycle and the third clock cycle, including: The first cache register stores the current redundancy check code calculation result and the first clock cycle; The second cache register stores a first comparison result between the content of the first cache register in the first clock cycle and the high bit of the current content of the second cache register and the first valid data currently received by the second cache register in the second clock cycle; The third cache register stores the content of the first cache register in the second clock cycle, the comparison result of the high bit of the content of the second cache register in the second clock cycle with the first valid data received in the second clock cycle data receiving step and the current low bit of the third cache register content, and the second comparison result of the second valid data received in the third clock cycle is sent to the trigger control module.
9. The cyclic redundancy check method according to claim 8, characterized in that: After the comparison result of the second valid data received in the third clock cycle is sent to the trigger control module, the method further includes: When the third buffer register receives the second valid data, the calculation result of the redundant check code in the first buffer is sent to the trigger control module to perform continuous calculation of the next frame; The trigger control module outputs the second comparison result according to a preset end flag or an input timeout flag; After outputting the second comparison result, the first cache register, the second cache register and the third cache register are cleared.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the UART-based cyclic redundancy check method according to any one of claims 6 to 9.