High-reliability computer system with redundancy dissimilar architecture

Abstract

The invention provides a high-reliability computer system of a redundancy dissimilar architecture. The high-reliability computer system comprises a bus; the CPU module comprises a high-reliability CPU unit and a high-performance CPU unit which are connected through the bus; the power supply module is used for providing redundant power supply for the CPU unit; and the peripheral interface module is connected to the CPU unit through the bus. According to the invention, continuous operation of the system and uninterrupted execution of tasks can be ensured, and the stability and safety of the system are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer system design, and more particularly, to a high-reliability computer system with a redundant non-similar architecture. Background Art

[0002] In many mission-critical fields, such as aerospace, military, and industrial control, there are extremely high requirements for the reliability and stability of computer systems. Existing computer systems usually use a single hardware architecture. Although it can meet basic needs in some application scenarios, the fragility and lack of redundancy of the single architecture often lead to overall instability of the system when facing extreme environments or unexpected failures. Especially in scenarios that require long-term continuous operation, the failure of any single hardware may cause the entire system to stop working, causing immeasurable losses. With the development of technology, although some systems improve reliability by adding redundant hardware, this usually increases the complexity and cost of the system. In addition, the response speed and switching efficiency of existing technologies when dealing with hardware failures are often unsatisfactory, making it difficult to achieve truly seamless switching and continuous operation.

[0003] In the process of implementing the embodiments of the present invention, the inventors discovered that there are at least the following problems or defects in the prior art: there is a lack of a computer system architecture that can achieve high reliability and fast response while maintaining high performance. Summary of the invention

[0004] The present invention provides a high-reliability computer system with a redundant non-similar architecture, comprising:

[0005] bus;

[0006] CPU modules, including a high-reliability CPU unit and a high-performance CPU unit, connected via the bus;

[0007] Power supply module, providing redundant power supply for CPU unit;

[0008] The peripheral interface module is connected to the CPU unit through the bus.

[0009] Furthermore, the high-reliability CPU unit includes:

[0010] High reliability CPU;

[0011] High reliability processing FPGA module.

[0012] Furthermore, the high performance CPU unit includes:

[0013] High-performance CPU;

[0014] High-performance processing FPGA module.

[0015] Furthermore, the high-reliability CPU unit and the high-performance CPU unit include:

[0016] Watchdog and reset circuit for monitoring and status recovery;

[0017] Clock module, providing timing signals.

[0018] Furthermore, the high-reliability CPU unit also includes:

[0019] Interfaces for connecting external storage devices, including SRAM, Flash, EEPROM, and MRAM;

[0020] Ethernet interface for connecting external network devices;

[0021] General purpose interface for connecting other external devices.

[0022] Furthermore, the high performance CPU unit also includes:

[0023] Interfaces for connecting external storage devices, including DDR2, Flash, EEPROM, and MRAM;

[0024] Ethernet interface for connecting external network devices;

[0025] General purpose interface for connecting other external devices.

[0026] Furthermore, the CPU module also includes a level conversion unit and an isolation drive unit; wherein,

[0027] The level conversion unit is used to ensure voltage compatibility with other system components;

[0028] The isolation drive unit is used to improve the electrical safety of connection with other system components.

[0029] Furthermore, the bus comprises:

[0030] Data bus for high-speed data transmission;

[0031] A control bus for synchronous signal transmission;

[0032] Address bus for inter-module communication.

[0033] Further, the high-reliability computer system of the redundant non-similar architecture is configured with a heartbeat synchronization mechanism and a task synchronization period interruption detection mechanism;

[0034] The heartbeat synchronization mechanism is used to periodically detect and confirm the operating status of each high-performance CPU unit and high-reliability CPU unit, and to ensure the high reliability of the system by receiving heartbeat signals in parallel and using OR logic;

[0035] The task synchronization period interrupt detection mechanism is used to automatically switch to error interrupt processing when it detects that the synchronization interrupt signal of the on-duty machine is abnormal, and to identify the state change of the on-duty machine through the interrupt flag in the register.

[0036] Furthermore, the high-reliability computer system with redundant non-similar architecture is configured with a heartbeat detection and voting mechanism and cold and hot standby switching logic;

[0037] Heartbeat detection and voting mechanism, used to automatically output heartbeat signals to other CPU units of the same type and receive heartbeat signals to achieve real-time monitoring and fault determination of the heartbeats of high-performance CPU units and high-reliability CPU units;

[0038] The cold and hot standby switching logic ensures that when the heartbeat of the current on-duty machine is abnormal, it can automatically switch to other normally working CPU units as the new on-duty machine based on the priority chain logic and heartbeat detection results, ensuring the continuous operation of the system and uninterrupted execution of tasks.

[0039] The above-mentioned embodiments of the present invention have at least the following beneficial effects: the redundant non-similar architecture high-reliability computer system of the present invention can achieve double protection in critical task processing by integrating high-reliability CPU units and high-performance CPU units. In the system design, the modular design of bus connection can not only improve the flexibility and scalability of the system, but also enhance the stability and reliability of the system through redundant power supply and diversified interface design. In particular, the heartbeat synchronization mechanism and task synchronization cycle interruption detection mechanism of the system configuration can monitor the operating status of each CPU unit in real time, ensuring that fault switching and status recovery can be quickly performed when an abnormality is detected, thereby improving the system's continuous operation capability and the stability of task execution.

[0040] In addition, the system of the present invention also particularly strengthens the design of the level conversion unit and the isolation drive unit, which can not only ensure the voltage compatibility with other system components, but also improve electrical safety. Through the introduction of cold and hot standby switching logic, the system can automatically switch to other normally working CPU units according to the priority chain logic and heartbeat detection results when the heartbeat of the current on-duty machine is abnormal, so as to achieve seamless system switching and task takeover, and ensure the uninterrupted execution of key tasks. The comprehensive application of these designs can provide users with an efficient and reliable computing platform, which is particularly suitable for application scenarios with extremely high reliability requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, in which:

[0042] Figure 1 A schematic diagram of a high-reliability computer system structure with a redundant non-similar architecture provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of the structure of a high-reliability CPU unit provided by an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of the structure of a high-performance CPU unit provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0045] The principles and spirit of the present invention will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0046] Those skilled in the art know that the embodiments of the present invention can be implemented as a system, device, apparatus, method or computer program product. Therefore, the present invention can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0047] It should be noted that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction and does not have any limiting meaning.

[0048] Reference below Figure 1 , Figure 1 A schematic diagram of a high-reliability computer system structure of a redundant non-similar architecture provided by an embodiment of the present invention. A high-reliability computer system of a redundant non-similar architecture includes a plug-in module, wherein the plug-in module includes:

[0049] Bus: As the core communication channel of the system, the bus is responsible for connecting various plug-in modules to achieve high-speed data transmission, synchronous signal transmission and communication between modules.

[0050] The CPU modules, including high-reliability CPU units and high-performance CPU units, are interconnected through bus modules. The CPU module is the core of system processing and control, responsible for executing system tasks and instructions.

[0051] The power supply module provides redundant power supply for the CPU unit, ensuring stable operation of the system even when part of the power supply fails.

[0052] The peripheral interface module is connected to the CPU unit through a bus and is used to connect and control various external devices such as sensors, actuators, etc.

[0053] Furthermore, the CPU module also includes a level conversion unit and an isolation drive unit; wherein the level conversion unit is used to ensure voltage compatibility with other system components; and the isolation drive unit is used to improve electrical safety of connection with other system components.

[0054] Level conversion units and isolation driver units are used to ensure voltage compatibility between the CPU module and other system components and to improve electrical safety.

[0055] Further, the bus includes:

[0056] Data bus for high-speed data transmission;

[0057] A control bus for synchronous signal transmission;

[0058] Address bus for inter-module communication.

[0059] Further, the high-reliability computer system of the redundant non-similar architecture is configured with a heartbeat synchronization mechanism and a task synchronization period interruption detection mechanism;

[0060] The heartbeat synchronization mechanism is used to periodically detect and confirm the operating status of each high-performance CPU unit and high-reliability CPU unit, and to ensure the high reliability of the system by receiving heartbeat signals in parallel and using OR logic;

[0061] The task synchronization period interrupt detection mechanism is used to automatically switch to error interrupt processing when it detects that the synchronization interrupt signal of the on-duty machine is abnormal, and to identify the state change of the on-duty machine through the interrupt flag in the register.

[0062] Furthermore, the high-reliability computer system with redundant non-similar architecture is configured with a heartbeat detection and voting mechanism and cold and hot standby switching logic;

[0063] Heartbeat detection and voting mechanism, used to automatically output heartbeat signals to other CPU units of the same type and receive heartbeat signals to achieve real-time monitoring and fault determination of the heartbeats of high-performance CPU units and high-reliability CPU units;

[0064] The cold and hot standby switching logic ensures that when the heartbeat of the current on-duty machine is abnormal, it can automatically switch to other normally working CPU units as the new on-duty machine based on the priority chain logic and heartbeat detection results, ensuring the continuous operation of the system and uninterrupted execution of tasks.

[0065] The working principle of a high-reliability computer system with redundant non-similar architecture involves multiple levels, including hardware design, communication mechanism, monitoring system, and fault handling strategy. The following is a detailed description of the working principle of the system:

[0066] More specifically, the high-reliability computer system with redundant non-similar architecture adopts a layered bus structure, including a data bus, a control bus and an address bus. The data bus is responsible for high-speed data transmission, the control bus is used for the transmission of synchronization signals, and the address bus is used for communication between modules.

[0067] The CPU module consists of a high-reliability CPU unit and a high-performance CPU unit, which are interconnected through a bus to achieve parallel processing of tasks and load balancing. The power module provides redundant power supply to ensure that the system can still operate stably when part of the power supply fails.

[0068] The peripheral interface module connects various external devices, such as sensors and actuators, and communicates with the CPU module through the bus.

[0069] The communication mechanism of the high-reliability computer system with redundant non-similar architecture is:

[0070] Through the data bus, data can be transmitted between system modules at high speed to ensure the rapid flow of information. The control bus ensures that all CPU units and other modules remain synchronized when performing tasks to avoid time deviations. The address bus allows modules to address and communicate with each other, realizing complex task allocation and coordination.

[0071] The high-reliability computer system with redundant non-similar architecture also integrates a monitoring system, specifically:

[0072] Heartbeat synchronization mechanism: Periodically detect the operating status of each CPU unit, receive heartbeat signals in parallel, and use OR logic to ensure that at least one CPU unit is working normally, thereby ensuring high reliability of the system.

[0073] Task synchronization periodic interrupt detection mechanism: monitors the synchronization of task execution. Once an abnormality is detected, the system automatically switches to the error interrupt processing flow and identifies the state change through the interrupt flag in the register.

[0074] The high-reliability computer system with redundant non-similar architecture also integrates fault handling strategies, specifically:

[0075] Heartbeat detection and voting mechanism: The system automatically outputs heartbeat signals to other CPU units of the same type and receives their heartbeat signals to achieve real-time monitoring of the CPU unit's heartbeat and fault determination.

[0076] Cold and hot standby switching logic: When the heartbeat of the current on-duty machine is abnormal, the system automatically switches to other normally working CPU units as the new on-duty machine based on the priority chain logic and heartbeat detection results, ensuring the continuous operation of the system and uninterrupted execution of tasks.

[0077] Exemplarily, the workflow of a high-reliability computer system with a redundant non-similar architecture is as follows:

[0078] 1. Startup phase: When the system starts, all CPU units receive the startup signal through the bus and begin to execute the initialization program.

[0079] 2. Operation phase:

[0080] Each CPU unit receives a task via the bus and starts executing it.

[0081] The heartbeat synchronization mechanism periodically detects the CPU unit status to ensure that at least one CPU unit is working properly.

[0082] The task synchronization period interruption detection mechanism monitors the synchronization of task execution to ensure the correct execution of tasks.

[0083] 3. Troubleshooting:

[0084] Once an abnormal heartbeat of the CPU unit is detected, the heartbeat detection and voting mechanism will be triggered, and the system will evaluate the fault and respond.

[0085] The cold and hot standby switching logic automatically switches to the standby CPU unit based on the priority and heartbeat detection results to ensure that the system does not interrupt service.

[0086] 4. Normal operation: After the fault is handled, the system continues to operate normally, and all modules work together to complete the task.

[0087] Through this design, a high-reliability computer system with redundant non-similar architecture can achieve efficient data processing and task execution while ensuring high reliability.

[0088] Further references Figure 2 . Figure 2 This is a schematic diagram of the structure of a high-reliability CPU unit.

[0089] High reliability CPU unit includes:

[0090] High-reliability CPU: It is the computing core of the unit and is responsible for performing critical computing tasks. It is designed to withstand extreme environmental conditions and high loads, ensuring stable operation in all situations.

[0091] High-Reliability Processing FPGA Module: Works closely with the high-reliability CPU to provide additional processing power, especially when fast response or specific algorithm optimization is required. The programmability of the FPGA module allows for flexible adaptation to different processing requirements.

[0092] Watchdog and reset circuit: monitors the operating status of the CPU unit to ensure its normal operation. If an abnormality is detected, the watchdog will trigger the reset circuit to restore the CPU unit to a safe state.

[0093] Clock module: Provides precise timing signals to ensure that the CPU unit and other system components can operate synchronously.

[0094] Interface module: includes SRAM, Flash, EEPROM and MRAM interfaces, which are used to connect external storage devices and provide data storage and fast access capabilities.

[0095] Ethernet interface: realizes connection with external network devices and supports remote transmission and communication of data.

[0096] Universal interface: provides the ability to connect with other external devices, increasing the scalability and flexibility of the system.

[0097] Level conversion unit: Ensures compatibility between the CPU unit and other system components at the voltage level to avoid problems caused by voltage mismatch.

[0098] Isolation drive unit: Improves electrical safety of connections between CPU units and other system components, and reduces electrical interference and fault propagation through isolation technology.

[0099] Specifically, the workflow of the high-reliability CPU unit is:

[0100] 1. Initialization: When the system starts, the high-reliability CPU unit receives the startup signal from the bus and begins to execute the initialization program to configure system resources and parameters.

[0101] 2. Task execution: Once initialization is completed, the CPU unit begins to receive task requests from the bus and executes the corresponding calculation and processing tasks.

[0102] 3. Monitoring and synchronization:

[0103] Watchdog and reset circuits continuously monitor the status of the CPU Unit to ensure stable operation.

[0104] The clock module provides synchronization signals to ensure the time consistency between the CPU unit and other system components.

[0105] 4. Data interaction:

[0106] Through the interface module, the CPU unit interacts with the external storage device to store and read data.

[0107] The Ethernet interface supports communication with remote network devices and realizes remote transmission of data.

[0108] 5. Fault detection and recovery:

[0109] If the watchdog detects that the CPU unit is operating abnormally, it will trigger the reset circuit to restore the CPU unit to a safe state.

[0110] The heartbeat synchronization mechanism periodically checks the operating status of the CPU units to ensure that at least one CPU unit is working properly.

[0111] 6. Redundant power supply: The power supply module provides redundant power supply, which can maintain stable operation of the CPU unit even in the event of partial power failure.

[0112] 7. Electrical safety: The level conversion unit and isolation drive unit ensure the electrical compatibility and safety of the CPU unit and other system components.

[0113] 8. Cold and hot standby switching: When the heartbeat is abnormal, the system will automatically switch to the backup CPU unit according to the cold and hot standby switching logic to ensure task continuity and system stability.

[0114] Further references Figure 3 . Figure 3 This is a schematic diagram of the structure of a high-performance CPU unit.

[0115] High-performance CPU unit includes:

[0116] High-performance CPU: It is the computing core of the unit, has high-speed processing capabilities, and is responsible for performing computationally intensive tasks and high-speed data processing.

[0117] High-performance processing FPGA module: Works in parallel with the high-performance CPU to provide dedicated hardware acceleration, especially in scenarios that require parallel processing or specific algorithm optimization.

[0118] Watchdog and reset circuit: monitors the operating status of the high-performance CPU to ensure its normal operation. When an abnormality is detected, a reset operation is triggered to restore the CPU to a stable state.

[0119] Clock module: Provides precise clock signals to ensure that the CPU unit and other system components run synchronously.

[0120] Interface module: includes DDR2, Flash, EEPROM and MRAM interfaces, used to connect high-speed external storage devices and provide fast data access capabilities.

[0121] Ethernet interface: realizes connection with external network devices and supports high-speed data transmission and remote communication.

[0122] Universal interface: provides the ability to connect to other external devices, increasing the flexibility and scalability of the system.

[0123] Level conversion unit: ensures compatibility between high-performance CPUs and other system components at the voltage level.

[0124] Isolation drive unit: Improves electrical safety when connecting high-performance CPUs to other system components.

[0125] Specifically, the workflow of the high-performance CPU unit is:

[0126] 1. Initialization: When the system starts, the high-performance CPU unit receives the startup signal from the bus, executes the initialization program, and configures system resources and parameters.

[0127] 2. Task execution: After initialization, the CPU unit receives task requests from the bus and performs high-speed computing and data processing tasks.

[0128] 3. Monitoring and synchronization:

[0129] Watchdog and reset circuits continuously monitor the status of the CPU Unit to ensure stable operation.

[0130] The clock module provides synchronization signals to ensure the time consistency between the CPU unit and other system components.

[0131] 4. Data interaction:

[0132] Through the interface module, the CPU unit interacts with external storage devices at high speed.

[0133] The Ethernet interface supports high-speed data transmission and communication with remote network devices.

[0134] 5. Fault detection and recovery:

[0135] If the watchdog detects that the CPU unit is operating abnormally, it will trigger the reset circuit to restore the CPU unit to a safe state.

[0136] The heartbeat synchronization mechanism periodically checks the operating status of the CPU units to ensure that at least one CPU unit is working properly.

[0137] 6. Redundant power supply: The power supply module provides redundant power supply to ensure that the CPU unit can still operate stably when part of the power supply fails.

[0138] 7. Electrical safety: The level conversion unit and isolation drive unit ensure the electrical compatibility and safety of the high-performance CPU and other system components.

[0139] 8. Cold and hot standby switching: When the heartbeat is abnormal, the system will automatically switch to the backup CPU unit according to the cold and hot standby switching logic to ensure task continuity and system stability.

[0140] 9. Performance optimization: The design of high-performance CPU unit focuses on computing efficiency and data processing speed, and achieves rapid response to complex computing tasks through hardware acceleration of FPGA module and high-speed access to DDR2 memory.

[0141] In some embodiments, the high-reliability CPU unit acts as the main control unit to perform key tasks; the high-performance CPU unit acts as an auxiliary unit to handle tasks with high real-time requirements. When the performance of the high-reliability CPU unit meets the task requirements, the system works in self-monitoring mode, and the two units perform the same task to enhance reliability. If the performance is not satisfied, the system switches to parallel working mode, and the two units perform different tasks to improve real-time performance.

[0142] In some embodiments, in order to achieve fast data communication between high-reliability CPU units and high-performance CPU units, the system adopts high-speed serial data communication technology. Each CPU unit includes a transmit data interface logic and a multi-channel receive data interface logic, and its transmit and receive buffer FIFO is implemented by an FPGA module.

[0143] The synchronization signal is generated by the master control unit and sent to other units to achieve synchronization of data communication. Each unit can detect whether the periodic signal of the master control unit is normal. Under normal working conditions, all units will generate interrupts in each task cycle and send them to their respective CPU processors. If the synchronization interrupt signal is detected to be abnormal, the task interrupt will be stopped and the error interrupt will be submitted instead. The interrupt flag register will be updated and the master control unit status will be marked as an error. When a new master control unit appears, the system will automatically switch to the synchronization interrupt of the new unit.

[0144] In some embodiments, each CPU unit writes a heartbeat signal to the FPGA through the interface module after entering the task synchronization cycle interrupt. The heartbeat detection and voting module in the FPGA automatically outputs a periodic heartbeat signal to other CPU units of the same type, and receives their heartbeat signals, and determines whether the heartbeat status is normal through OR logic.

[0145] This system is a multi-machine cold and hot standby system, with only one CPU unit as the master control unit. The FPGA implements the voting logic and identifies the CPU module by reading the bus board slot number. Each machine can output a signal that prohibits other machines from becoming the master control unit, and receive a signal output by other machines that prohibits the machine from becoming the master control unit. The judgment of the master control unit is based on the detection results of the heartbeat signal of the current master control unit by other units. If the heartbeat of this machine is normal and is not prohibited from becoming the master control unit, this machine will become the new master control unit according to the priority logic. If it is necessary to work under a heartbeat failure, the heartbeat detection mode must be turned off. Any machine can become the master control unit, and the determination and switching of its role are jointly controlled by hardware and onboard software.

[0146] The above-mentioned various embodiments of the present invention have the following beneficial effects: The high-reliability computer system of the present invention, with its innovative architecture, can significantly improve the system stability and reliability in critical applications. By adopting a plug-in modular design, the system is not only easy to expand and maintain, but also can enhance the ability to resist failures through redundant power supplies and multi-functional interfaces. The heartbeat synchronization and task synchronization cycle interrupt detection mechanism embedded in the system can timely monitor and respond to abnormal operating status of the CPU unit, and realize rapid fault switching and system status recovery. The design of the level conversion and isolation drive unit can ensure voltage matching and electrical safety with external components. The integration of cold and hot standby switching logic allows the system to automatically and seamlessly switch to the backup CPU unit when a heartbeat abnormality occurs on the current machine, ensuring the continuous execution of critical tasks. The integration of these technologies can bring users an efficient and stable computing solution, which is particularly suitable for critical mission environments with extremely high reliability requirements.

[0147] The above descriptions are only some preferred embodiments of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present invention is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention to form a technical solution.

Claims

1. A high-reliability computer system with redundant non-similar architecture, characterized in that: A plug-in module is included, wherein the plug-in module includes: bus; CPU modules, including a high-reliability CPU unit and a high-performance CPU unit, connected via the bus; Power supply module, providing redundant power supply for CPU unit; The peripheral interface module is connected to the CPU unit through the bus.

2. A high-reliability computer system with redundant non-similar architecture according to claim 1, characterized in that: High reliability CPU unit includes: High reliability CPU; High reliability processing FPGA module.

3. A high-reliability computer system with redundant non-similar architecture according to claim 1, characterized in that: High-performance CPU unit includes: High-performance CPU; High-performance processing FPGA module.

4. A high-reliability computer system with redundant non-similar architecture according to claim 2, characterized in that: The high-reliability CPU unit and the high-performance CPU unit include: Watchdog and reset circuit for monitoring and status recovery; Clock module, providing timing signals.

5. A high-reliability computer system with a redundant non-similar architecture according to claim 4, characterized in that: The high-reliability CPU unit also includes: Interfaces for connecting external storage devices, including SRAM, Flash, EEPROM, and MRAM; Ethernet interface for connecting external network devices; General purpose interface for connecting other external devices.

6. A high-reliability computer system with redundant non-similar architecture according to claim 3, characterized in that: The high performance CPU unit also includes: Interfaces for connecting external storage devices, including DDR2, Flash, EEPROM, and MRAM; Ethernet interface for connecting external network devices; General purpose interface for connecting other external devices.

7. The high-reliability computer system with redundant non-similar architecture according to claim 1, characterized in that: The CPU module also includes a level conversion unit and an isolation drive unit; wherein, The level conversion unit is used to ensure voltage compatibility with other system components; The isolation drive unit is used to improve the electrical safety of the connection with other system components.

8. The high-reliability computer system with redundant non-similar architecture according to claim 1, characterized in that: The bus comprises: Data bus for high-speed data transmission; A control bus for synchronous signal transmission; Address bus for inter-module communication.

9. The high-reliability computer system with redundant non-similar architecture according to claim 1, characterized in that: The high-reliability computer system with redundant non-similar architecture is configured with a heartbeat synchronization mechanism and a task synchronization cycle interrupt detection mechanism; The heartbeat synchronization mechanism is used to periodically detect and confirm the operating status of each high-performance CPU unit and high-reliability CPU unit, and to ensure the high reliability of the system by receiving heartbeat signals in parallel and using OR logic; The task synchronization period interrupt detection mechanism is used to automatically switch to error interrupt processing when it detects that the synchronization interrupt signal of the on-duty machine is abnormal, and to identify the state change of the on-duty machine through the interrupt flag in the register.

10. The high-reliability computer system with redundant non-similar architecture according to claim 1, characterized in that: The high-reliability computer system with redundant non-similar architecture is equipped with heartbeat detection and voting mechanism and cold and hot standby switching logic; Heartbeat detection and voting mechanism, used to automatically output heartbeat signals to other CPU units of the same type and receive heartbeat signals to achieve real-time monitoring and fault determination of the heartbeats of high-performance CPU units and high-reliability CPU units; The cold and hot standby switching logic ensures that when the heartbeat of the current on-duty machine is abnormal, it can automatically switch to other normally working CPU units as the new on-duty machine based on the priority chain logic and heartbeat detection results, ensuring the continuous operation of the system and uninterrupted execution of tasks.

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