FPGA test data acquisition method, FPGA and device

Abstract

The embodiment of the invention provides an FPGA (Field Programmable Gate Array) test data acquisition method, an FPGA and an FPGA test data acquisition device, relates to the technical field of testing, is applied to the FPGA and comprises the following steps: receiving configuration information sent by a debugging machine; wherein the configuration information represents a termination condition and a sampling depth of signal data acquisition; collecting signal data processed by the FPGA, and storing the collected signal data in an RAM (Random Access Memory) in the FPGA; delaying and stopping signal data acquisition when the acquired signal data meets a termination condition; reading test data from the signal data stored in the RAM; wherein the test data is continuously acquired signal data acquired in a sampling depth clock period, and the test data comprises signal data acquired in a clock period meeting a termination condition; and generating a test file according to the test data, and sending the test file to the debugging machine. By applying the scheme provided by the embodiment of the invention, the debugging cost of the FPGA can be reduced.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to an FPGA test data acquisition method, FPGA and device. Background Art

[0002] In the related art, FPGA (Field Programmable Gate Array) developers need to rely on the tools provided by the FPGA manufacturer to capture the signal waveform inside the FPGA as test data when debugging and locating the FPGA. However, when using the above tools, a JTAG (Join Test Action Group) loading box is required, and the JTAG loading box is connected to the FPGA. In addition, the debugging machine that receives the test data and processes the test data to generate the test results also needs to install EDA (Electronic Design Automation) software. The debugging machine and JTAG are connected through a wired or wireless network for data exchange.

[0003] See also Figure 1 , is a schematic diagram of an FPGA test scenario in the related art. The figure includes a debugger, a JTAG loading box and an FPGA. The figure shows the connection relationship between the three.

[0004] It can be seen that the collection of FPGA test data in the related technology requires a dedicated JTAG loading box and EDA software, resulting in high software and hardware costs for FPGA debugging. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide an FPGA test data collection method, FPGA and device to reduce the debugging cost of FPGA. The specific technical solution is as follows:

[0006] In a first aspect of an embodiment of the present application, a method for collecting FPGA test data is first provided, which is applied to an FPGA, wherein the FPGA is connected to a debugging machine, and the method comprises:

[0007] Receiving configuration information sent by the debugging machine; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0008] Collecting signal data processed by the FPGA, and storing the collected signal data in a random access memory RAM in the FPGA;

[0009] From the time when the collected signal data meets the termination condition, delaying and stopping the signal data collection;

[0010] Reading test data from the signal data stored in the RAM; wherein the test data is signal data collected continuously in the sampling depth clock cycles, and the test data includes signal data collected in the clock cycle that meets the termination condition;

[0011] A test file is generated according to the test data, and the test file is sent to the debugging machine.

[0012] In a possible embodiment, the configuration information further indicates a trigger position, and the trigger position is the order of the signal data collected in the clock cycle that meets the termination condition in the test data;

[0013] After the collected signal data meets the termination condition, delaying and stopping the signal data collection includes:

[0014] Starting from the time when the collected signal data meets the termination condition, continuing to collect valid signal data in a target clock cycle and then stopping the collection; wherein the number of the target clock cycles is the difference between the sampling depth and the trigger position;

[0015] The step of reading the test data from the signal data stored in the RAM comprises:

[0016] The test data including the valid signal data is read from the signal data stored in the RAM.

[0017] In a possible embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, storing the collected signal data in a random access memory RAM in the FPGA includes:

[0018] storing different parts of the signal data collected in the same clock cycle in rows of the same order in a plurality of RAMs in the FPGA;

[0019] The step of reading the test data from the signal data stored in the RAM comprises:

[0020] Reading data from the plurality of RAMs respectively;

[0021] The data read from the plurality of RAMs are combined into test data, wherein each test data is composed of data recorded in rows of the plurality of RAMs in the same order.

[0022] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0023] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0024] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0025] In a second aspect of an embodiment of the present application, a method for collecting FPGA test data is further provided, which is applied to a debugging machine, wherein the debugging machine is connected to a field programmable gate array FPGA, and the method comprises:

[0026] Acquire configuration information; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0027] Sending configuration information to the FPGA so that the FPGA collects signal data processed by the FPGA according to the configuration information, generates a test file containing test data in the collected signal data, and sends the test file to the debugging machine; wherein the test data is signal data collected continuously and collected in clock cycles of the sampling depth, and the test data contains signal data collected in clock cycles that meet the termination condition;

[0028] Receive a test file sent by the FPGA.

[0029] In a possible embodiment, the configuration information further indicates a trigger position, where the trigger position is the order of the signal data collected by the FPGA in a clock cycle that meets the termination condition in the test data.

[0030] In a possible embodiment, after receiving the test file sent by the FPGA, the method further includes:

[0031] The signal waveform represented by the test file is displayed in the signal waveform display interface.

[0032] In a possible embodiment, the acquiring configuration information includes:

[0033] Receiving a configuration information input signal; wherein the configuration information input signal is used to indicate the value of a parameter included in the configuration information to be generated;

[0034] Configuration information is generated according to the configuration information input signal.

[0035] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0036] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0037] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0038] In a third aspect of the embodiment of the present application, an FPGA is further provided, the FPGA being connected to a debugging machine, and the FPGA being used to perform the following operations:

[0039] Receiving configuration information sent by the debugging machine; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0040] Collecting signal data processed by the FPGA, and storing the collected signal data in a random access memory RAM in the FPGA;

[0041] From the time when the collected signal data meets the termination condition, delaying and stopping the signal data collection;

[0042] Reading test data from the signal data stored in the RAM; wherein the test data is signal data collected continuously in the sampling depth clock cycles, and the test data includes signal data collected in the clock cycle that meets the termination condition;

[0043] A test file is generated according to the test data, and the test file is sent to the debugging machine.

[0044] In a possible embodiment, the configuration information further indicates a trigger position, where the trigger position is the order of the signal data collected in the clock cycle that meets the termination condition in the test data; the FPGA is specifically used for:

[0045] Starting from the time when the collected signal data meets the termination condition, continuing to collect valid signal data in a target clock cycle and then stopping the collection; wherein the number of the target clock cycles is the difference between the sampling depth and the trigger position;

[0046] The FPGA is specifically used for:

[0047] The test data including the valid signal data is read from the signal data stored in the RAM.

[0048] In a possible embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, the FPGA is specifically used for:

[0049] storing different parts of the signal data collected in the same clock cycle in rows of the same order in a plurality of RAMs in the FPGA;

[0050] The FPGA is specifically used for:

[0051] Reading data from the plurality of RAMs respectively;

[0052] The data read from the plurality of RAMs are combined into test data, wherein each test data is composed of data recorded in rows of the plurality of RAMs in the same order.

[0053] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0054] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0055] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0056] In a fourth aspect of the embodiment of the present application, a debugging machine is further provided, the debugging machine is connected to a field programmable gate array FPGA, and the debugging machine includes a memory, a transceiver, and a processor:

[0057] A memory for storing a computer program; a transceiver for transmitting and receiving data under the control of the processor; and a processor for reading the computer program in the memory and performing the following operations:

[0058] Acquire configuration information; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0059] Sending configuration information to the FPGA so that the FPGA collects signal data processed by the FPGA according to the configuration information, generates a test file containing test data in the collected signal data, and sends the test file to the debugging machine; wherein the test data is signal data collected continuously and collected in clock cycles of the sampling depth, and the test data contains signal data collected in clock cycles that meet the termination condition;

[0060] Receive a test file sent by the FPGA.

[0061] In a possible embodiment, the configuration information further indicates a trigger position, where the trigger position is the order of the signal data collected by the FPGA in a clock cycle that meets the termination condition in the test data.

[0062] In a possible embodiment, the processor is further configured to:

[0063] The signal waveform represented by the test file is displayed in the signal waveform display interface.

[0064] In a possible embodiment, the processor is specifically configured to:

[0065] Receiving a configuration information input signal; wherein the configuration information input signal is used to indicate the value of a parameter included in the configuration information to be generated;

[0066] Configuration information is generated according to the configuration information input signal.

[0067] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0068] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0069] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0070] In a fifth aspect of the embodiment of the present application, there is also provided an FPGA test data acquisition device, which is applied to a field programmable gate array FPGA, wherein the FPGA is connected to a debugging machine, and the device comprises:

[0071] An information receiving module, used to receive configuration information sent by a debugging machine; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0072] A first acquisition module, used for acquiring signal data processed by the FPGA, and storing the acquired signal data in a random access memory RAM in the FPGA;

[0073] A second acquisition module, used for delaying and stopping signal data acquisition from the time when the acquired signal data meets the termination condition;

[0074] A data reading module, used to read test data from the signal data stored in the RAM; wherein the test data is signal data collected continuously in the sampling depth clock cycles, and the test data includes signal data collected in the clock cycle that meets the termination condition;

[0075] The file sending module is used to generate a test file according to the test data and send the test file to the debugging machine.

[0076] In a possible embodiment, the configuration information further indicates a trigger position, and the trigger position is the order of the signal data collected in the clock cycle that meets the termination condition in the test data;

[0077] The second acquisition module is specifically used for:

[0078] Starting from the time when the collected signal data meets the termination condition, continuing to collect valid signal data in a target clock cycle and then stopping the collection; wherein the number of the target clock cycles is the difference between the sampling depth and the trigger position;

[0079] The data reading module is specifically used for:

[0080] The test data including the valid signal data is read from the signal data stored in the RAM.

[0081] In a possible embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, the first collection module is specifically used to:

[0082] storing different parts of the signal data collected in the same clock cycle in rows of the same order in a plurality of RAMs in the FPGA;

[0083] The data reading module is specifically used for:

[0084] Reading data from the plurality of RAMs respectively;

[0085] The data read from the plurality of RAMs are combined into test data, wherein each test data is composed of data recorded in rows of the plurality of RAMs in the same order.

[0086] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0087] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0088] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0089] In a sixth aspect of the embodiment of the present application, there is also provided an FPGA test data acquisition device, which is applied to a debugging machine, the debugging machine is connected to a field programmable gate array FPGA, and the device comprises:

[0090] An information acquisition module, used to acquire configuration information; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0091] An information sending module, used for sending configuration information to the FPGA, so that the FPGA collects the signal data processed by the FPGA according to the configuration information, generates a test file containing test data in the collected signal data, and sends the test file to the debugging machine; wherein the test data is signal data collected continuously and collected in the sampling depth clock cycles, and the test data contains signal data collected in the clock cycle that meets the termination condition;

[0092] The file receiving module is used to receive the test file sent by the FPGA.

[0093] In a possible embodiment, the configuration information further indicates a trigger position, where the trigger position is the order of the signal data collected by the FPGA in a clock cycle that meets the termination condition in the test data.

[0094] In a possible embodiment, after the file receiving module receives the test file sent by the FPGA, the method further includes:

[0095] The waveform display module is used to display the signal waveform represented by the test file in the signal waveform display interface.

[0096] In a possible embodiment, the information acquisition module is specifically used to:

[0097] Receiving a configuration information input signal; wherein the configuration information input signal is used to indicate the value of a parameter included in the configuration information to be generated;

[0098] Configuration information is generated according to the configuration information input signal.

[0099] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0100] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0101] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0102] In another aspect of the implementation of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the method steps described in any one of the first aspect or the second aspect are implemented.

[0103] Beneficial effects of the embodiments of the present application:

[0104] The FPGA test data acquisition method provided in the embodiment of the present application, when the FPGA receives the configuration information sent by the debugger, collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA. Since the configuration information indicates the termination condition and sampling depth of the signal data acquisition, the FPGA stops the signal data acquisition with a delay from when the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data acquisition process.

[0105] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0106] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0107] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0108] Figure 1 A schematic diagram of an FPGA test scenario in the related art;

[0109] Figure 2 A flowchart of a first FPGA test data acquisition method provided in an embodiment of the present application;

[0110] Figure 3 A flowchart of a second FPGA test data acquisition method provided in an embodiment of the present application;

[0111] Figure 4 A waveform acquisition schematic diagram provided in an embodiment of the present application;

[0112] Figure 5 A flowchart of a third FPGA test data acquisition method provided in an embodiment of the present application;

[0113] Figure 6 A schematic diagram of a parallel-to-serial conversion provided in an embodiment of the present application;

[0114] Figure 7A schematic diagram of a fourth FPGA test data acquisition method provided in an embodiment of the present application;

[0115] Figure 8 A flowchart of a fifth FPGA test data acquisition method provided in an embodiment of the present application;

[0116] Fig. 9 A schematic diagram of a signal waveform display interface of a debugging machine provided in an embodiment of the present application;

[0117] Fig.10 A flowchart of a sixth FPGA test data acquisition method provided in an embodiment of the present application;

[0118] Fig.11 A schematic diagram of a termination condition configuration interface of a debugging machine provided in an embodiment of the present application;

[0119] Fig.12 A schematic diagram of the structure of an SSA logic IP provided in an embodiment of the present application;

[0120] Fig.13 A connection diagram between an FPGA and a debugging machine provided in an embodiment of the present application;

[0121] Fig.14 A schematic diagram of the structure of a debugging machine provided in an embodiment of the present application;

[0122] Fig.15 A schematic diagram of the structure of a first FPGA test data acquisition device provided in an embodiment of the present application;

[0123] Fig.16 A schematic diagram of the structure of a second FPGA test data acquisition device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0124] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0125] The present application embodiment provides a FPGA test data collection method, which is applied to FPGA, see Figure 2 , is a flow chart of the first FPGA test data acquisition method provided in an embodiment of the present application, and the method includes S201-S205.

[0126] S201, receiving configuration information sent by a debugging machine.

[0127] In S201, the configuration information is input by the user through the debugging machine. The configuration information indicates the termination condition and sampling depth of signal data acquisition.

[0128] The termination condition refers to the condition under which the FPGA stops signal data acquisition after a delay. The sampling depth refers to the depth of the signal data collected by the FPGA.

[0129] For example, assuming that the depth of the RAM (Random Access Memory) in the FPGA is Y, the maximum amount of data stored in the RAM by the FPGA is Y. For example, the depth of the RAM in the FPGA is 512, which means that the FPGA can store data of 512 clock cycles at most in the RAM.

[0130] In a possible embodiment, the minimum value of the sampling depth may be 128, 256, 512, etc., and the maximum value may be 32768, 65536, etc. The sampling depth may be greater than the RAM depth, or may be equal to the RAM depth or less than the RAM depth.

[0131] In a possible embodiment, the termination condition includes one or more trigger conditions; when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0132] Specifically, when there are multiple trigger conditions, the termination condition is determined by the trigger condition and the logical relationship between adjacent trigger conditions. The logical relationship includes AND, OR and other logical relationships. The trigger condition can be one or more.

[0133] For example, assuming that there is one trigger condition, trigger condition A, then the termination condition is A. Assuming that there are two termination conditions, trigger conditions A and B, and the logical relationship between A and B is &, then the termination condition is A&B, indicating that the termination condition is satisfied when both trigger condition A and trigger condition B are satisfied. Assuming that there are two termination conditions, trigger conditions B and C, and the logical relationship between B and C is I, then the termination condition is BIC, indicating that the termination condition is satisfied when either trigger condition A or trigger condition B is satisfied.

[0134] In addition, in one embodiment of the present application, there may be a logical relationship only between adjacent trigger conditions. For example, assuming there are three trigger conditions, A, B, and C, and the logical relationship between any two of them is &, then the termination condition can be A&B, B&C, A&B&C, but not A&C.

[0135] The above embodiment is selected. Since the termination condition includes one or more trigger conditions, and when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions. By setting the termination condition, the condition for FPGA delay stop signal data collection can be determined.

[0136] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0137] Specifically, the signal value represents the parameter type that needs to be limited, the trigger threshold represents the specific value corresponding to the signal value, and the relationship symbol between the signal value and the trigger threshold refers to the numerical relationship between the parameter type and the specific value corresponding to the signal value.

[0138] Among them, when the signal value is a single bit, the trigger threshold supports the following configurations: x (don't care), 0 (low level), 1 (high level), R (rising edge), F (falling edge), and B (rising edge or falling edge).

[0139] When the signal value is multi-bit, the trigger threshold supports configuration of any value and supports mask. The trigger threshold can be a binary number or a hexadecimal number.

[0140] Relational symbols may include: == (equal to), >= (greater than or equal to), <= (less than or equal to), > (greater than), < (less than), != (not equal to).

[0141] Exemplarily, assuming that the trigger condition is A, the signal value is sop (Start Of Packet), the trigger threshold is R, and the relationship symbol between the signal value and the trigger threshold is ==, then the trigger condition A is sop ==R.

[0142] Among them, the above x, 0, 1, R, F, and B are only one way of expression, and the parameters of the trigger threshold can also be expressed in other ways. For example, 1 represents a low level, 0 represents a high level, M represents a rising edge, and N represents a falling edge.

[0143] By selecting the above embodiment, the trigger condition can be constructed through the signal value, the trigger threshold, and the relationship between the signal value and the trigger threshold, and then the termination condition of signal data acquisition can be determined according to the trigger condition.

[0144] In a possible embodiment, the configuration information also indicates a trigger mode and a sampling enable. The trigger mode indicates that when the termination condition is met, the FPGA generates a trigger (trigger signal) and delays the stop of signal data acquisition. When the sampling enable is pulled high, the FPGA starts to collect signal data.

[0145] S202, collecting signal data processed by the FPGA, and storing the collected signal data in the RAM in the FPGA.

[0146] In S202, the maximum amount of signal data stored in the RAM is related to the depth of the RAM.

[0147] The FPGA stores the collected signal data in the RAM in the FPGA, which means that the FPGA writes data in the RAM.

[0148] When the storage space of the RAM is full, the signal data stored in the RAM may be overwritten. For example, assuming that the depth of the RAM is 512, the address of the signal data written by the FPGA for the first time in the RAM is 0-511, that is, the storage space of the RAM is full. After that, the signal data will continue to be written from address 0 in the RAM, and the original signal data at the same position will be overwritten by the newly written data. For example, if the address of the signal data written by the FPGA for the second time in the RAM is 0-50, then the signal data collected in the first 51 clock cycles of the signal data collected within the 512 clock cycles stored in the RAM will be overwritten by the signal data written by the FPGA for the second time.

[0149] S203, from the time when the collected signal data meets the termination condition, delay and stop the signal data collection.

[0150] In S203, when the signal data collected by the FPGA meets the termination condition, the FPGA does not stop collecting the signal data immediately, but stops collecting the signal data after collecting a period of valid signal data. Exemplarily, when the signal data collected by the FPGA meets the termination condition, the FPGA generates a trigger signal and stops collecting the signal data with a delay.

[0151] In one case, the delay clock period of the delayed stop signal data acquisition can be to stop the signal data acquisition after a preset delay clock period. In another case, the delay clock period of the delayed stop signal data acquisition can be related to the trigger position. For details, see Figure 3 The embodiments in which this is performed will not be described in detail here.

[0152] S204, reading test data from the signal data stored in the RAM.

[0153] In S204, the test data is signal data collected continuously in a sampling depth of clock cycles, and the test data includes signal data collected in a clock cycle that meets the termination condition.

[0154] Since the signal data stored in the RAM may be overwritten when the RAM storage space is full, this means that not all signal data collected by the FPGA will be read, and the data previously overwritten in the RAM no longer exists and will not be read by the FPGA.

[0155] For example, assuming that the depth of the RAM is 512, and the address of the signal data written by the FPGA for the first time in the RAM is 0-511, that is, the storage space of the RAM is full, if the address of the signal data written by the FPGA for the second time in the RAM is 0-50, then the signal data collected in the first 51 clock cycles of the signal data collected in the 512 clock cycles already stored in the RAM will be overwritten by the signal data written by the FPGA for the second time. In this case, the test data read by the FPGA from the signal data stored in the RAM includes: the signal data written by the FPGA for the second time at the address 0-50 in the RAM, and the signal data written by the FPGA for the first time at the address 51-511 in the RAM. That is, the FPGA first reads the signal data written by the FPGA for the first time at the address 51-511 from the RAM, and then reads the signal data written by the FPGA for the second time at the address 0-50.

[0156] Among them, the signal data written by the FPGA for the second time at addresses 0-50 in the RAM and the signal data written by the FPGA for the first time at addresses 51-511 in the RAM are collected continuously and include signal data collected in the clock cycle that meets the termination condition.

[0157] S205, generating a test file according to the test data, and sending the test file to the debugging machine.

[0158] In S205, the FPGA generates a test file according to the test data, and after sending the test file to the debugger, the debugger can generate a test result according to the test file. In one possible case, the debugger can generate a waveform according to the test file, and the user can debug and locate the FPGA according to the waveform.

[0159] The test file may be a vcd (Value Change Dump) file.

[0160] In a possible embodiment, the FPGA generates a test file according to the test data, and sends the test file carrying a verification code to the debugging machine.

[0161] The debugging machine determines whether the test file is intact based on the checksum. If the test file is intact, the waveform is displayed according to the test file. If the test file is abnormal, the debugging machine sends a message indicating data retransmission to the FPGA, and the FPG resends the test file to the debugging machine.

[0162] In a possible embodiment, the FPGA converts the test data into a binary string, obtains the binary data of the corresponding address according to the bit width of the signal data, converts it into decimal, and writes it into the test file.

[0163] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0164] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0165] In a possible embodiment, the configuration information further indicates a trigger position, which is the order of the signal data collected in the clock cycle that meets the termination condition in the test data. Figure 3 , is a flow chart of a second FPGA test data acquisition method provided in an embodiment of the present application, which is similar to the aforementioned Figure 2 Compared with the embodiment shown, the above S203 can be implemented through S203A, and S204 can be implemented through S204A.

[0166] S203A, starting from when the collected signal data meets the termination condition, continue to collect valid signal data in the target clock cycle and then stop collecting.

[0167] The number of target clock cycles is the difference between the sampling depth and the trigger position.

[0168] For example, assuming that the sampling depth is 512 and the trigger position is 256, the order of the signal data collected in the clock cycle that meets the termination condition in the test data is 256, and the number of target clock cycles is equal to 512-256=256, that is, from the time the collected signal data meets the termination condition, the FPGA still needs to collect valid signal data for 256 clock cycles.

[0169] The address of valid signal data in RAM is determined by way of example below.

[0170] Assuming the sampling depth is 512 and the trigger position is 256, when the collected signal data meets the termination condition, the address where the FPGA writes data in the RAM is 50. In theory, before the termination condition is met, the FPGA should have written a large amount of signal data in the RAM, of which some of the signal data written earlier has been overwritten by the signal data written later. Since the FPGA also needs to collect valid signal data of 512-256=256 clock cycles, the address of the valid signal data in the RAM is 50+256=306, that is, the address where the valid signal data in the RAM is located is 51-306. The signal data at addresses 0-50 and 307-511 in the RAM are the signal data written by the FPGA before, and the signal data at addresses 307-511 is written before the signal data at addresses 0-50.

[0171] S204A, reading test data including valid signal data from the signal data stored in the RAM.

[0172] In S204A, since the trigger position is the order of the signal data collected in the clock cycle that meets the termination condition in the test data, assuming that the sampling depth is 512 and the trigger position is 256, it means that half of the test data read by the FPGA from the signal data stored in the RAM is valid signal data, and the other half is signal data collected before the termination condition is met.

[0173] Assuming the sampling depth is 512 and the trigger position is 10, it means that the valid signal data in the test data read by the FPGA from the signal data stored in the RAM is the signal data collected in 502 clock cycles, and the signal data collected before the termination condition is met is the signal data collected in 10 clock cycles.

[0174] The following takes the sampling depth as 512, the trigger position as 256, and the address 50 where the FPGA writes data in the RAM when the collected signal data meets the termination condition as an example to illustrate the process of FPGA reading signal data from the RAM.

[0175] Step 1: Determine the location where the FPGA reads the first test data.

[0176] Since the signal data at addresses 0-50 and 307-511 in the RAM are the signal data written before by the FPGA, and the signal data at addresses 307-511 are written before the signal data at addresses 0-50, the signal data at addresses 51-306 in the RAM are the valid signal data collected by the FPGA after the termination condition is met, and the signal data at addresses 0-50 are written before the valid signal data at addresses 51-603, the location where the FPGA reads the first test data is the location at address 307 in the RAM.

[0177] Step 2: After the FPGA reads to the end of the RAM, if the sampling depth test data has not been read, it continues to read data from the starting position of the RAM until the sampling depth test data is read.

[0178] For example, the FPGA starts reading data from the address 307 in the RAM and continues to read data to the address 511 in the RAM. At this time, the FPGA has only read 205 data, which does not meet the sampling depth. The FPGA then continues to read data from the address 0 in the RAM and stops at the address 306 in the RAM. At this point, the FPGA has read 512 data, that is, the FPGA has read the sampling depth test data.

[0179] See also Figure 4 , which is a waveform acquisition schematic diagram provided in an embodiment of the present application.

[0180] The first row I_cap_clk (Input Capture Clock) represents a clock signal.

[0181] The second line I_dump_en (Input Dump Enable) indicates that after the sampling enable is pulled high, the FPGA starts to collect signal data.

[0182] The third line I_start_trig (Input Start Trigger) is pulled high to indicate that a trigger signal is generated when the termination condition is met.

[0183] The fourth line I_trig_position (Input Trigger Position) indicates that the trigger position is 256.

[0184] The fifth line ram_wen (Random Access Memory Write Enable) indicates that when the level is high, the FPGA writes signal data into the RAM, and the written signal data ends at the address 306 in the RAM.

[0185] The sixth line ram_waddr (random memory write address) indicates the address of the signal data written in the RAM, that is, the address of the signal data written by the FPGA in the RAM starts from 0, 1, ..., 511, and then from 0, 1, ..., 50, ..., 306.

[0186] Among them, vertical parallel lines mean omission.

[0187] Figure 4It means that the sampling enable is pulled high in the second clock cycle, and the termination condition is met to generate a trigger signal. Figure 4 The write position of the last row of RAM is 50, and the trigger position is 256, which means that the order of the signal data collected in the clock cycle that meets the termination condition in the test data is 256. Assuming the sampling depth is 512, the FPGA needs to collect signal data for 512-256=256 clock cycles. When the FPGA stops writing data to the RAM Figure 4 The write position of the last row of RAM is 306, indicating that the FPGA has continued to collect signal data for 512-256=256 clock cycles, which means that when the RAM address is 306, the FPGA stops writing data.

[0188] When the above embodiment is selected, since the trigger position in the configuration information is the order of the signal data collected in the clock cycle that meets the termination condition in the test data, the amount of valid signal data in the test data read by the FPGA from the RAM can be controlled by the trigger position and the sampling depth.

[0189] The amount of signal data collected in one clock cycle can be less than or equal to the data bit width of a RAM, or greater than the data bit width of a RAM. Assuming that the data bit width of the RAM is Mbit, the amount of signal data collected in one clock cycle can be less than Mbit, or equal to or greater than Mbit.

[0190] In a possible embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, see Figure 5 , is a flow chart of a third FPGA test data acquisition method provided in an embodiment of the present application, which is similar to the aforementioned Figure 2 Compared with the embodiment shown, the above S202 can be implemented through S202A, and S204 can be implemented through S204B-S204C.

[0191] S202A, collecting signal data processed by the FPGA, and storing different parts of the signal data collected in the same clock cycle in rows of the same order in multiple RAMs in the FPGA.

[0192] In S202A, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, different parts of the signal data collected in the same clock cycle are stored in rows of the same order in multiple RAMs in the FPGA.

[0193] For example, assuming that the data bit width of the RAM is 32 bits, and the amount of signal data collected in one clock cycle is 64 bits, 32 bits of the signal data collected in the same clock cycle are stored in the Xth row of RAM0, and another 32 bits of the signal data collected in the same clock cycle are stored in the Xth row of RAM1. The maximum value of X is the value of the sampling depth.

[0194] Assuming that the data bit width of the RAM is 32 bits and the amount of signal data collected in one clock cycle is 80 bits, then 32 bits of the signal data collected in the same clock cycle are stored in the Xth row in RAM0, another 32 bits of the signal data collected in the same clock cycle are stored in the Xth row in RAM1, and the remaining 16 bits of the signal data collected in the same clock cycle are stored in the Xth row in RAM2.

[0195] The number of signal data collected in one clock cycle and stored in the RAM is related to the data volume of the signal data collected in one clock cycle.

[0196] S204B, read data from multiple RAMs respectively.

[0197] For example, assuming that the data bit width of the RAM is 32 bits, the amount of signal data collected in one clock cycle is 64 bits, 32 bits of the signal data collected in the same clock cycle are stored in the Xth row in RAM0, and another 32 bits of the signal data collected in the same clock cycle are stored in the Xth row in RAM1. If the FPGA wants to read the data of the Xth clock cycle, the data is read from the Xth row in RAM0 and the Xth row in RAM1 respectively. For example, if the FPGA wants to read the data of the 1st clock cycle, the data is read from the 1st row in RAM0 and the 1st row in RAM1 respectively.

[0198] S204C, combining the data read from the multiple RAMs into test data.

[0199] Each test data is composed of data recorded in the same order in multiple rows of RAM.

[0200] For example, assuming that the data bit width of the RAM is 32 bits, the amount of signal data collected in one clock cycle is 64 bits, 32 bits of the signal data collected in the same clock cycle are stored in the Xth row in RAM0, and another 32 bits of the signal data collected in the same clock cycle are stored in the Xth row in RAM1. When the FPGA reads the data in the first clock cycle, it first reads data data_ram[1][Data[0]] from the first row in RAM0, reads data data_ram[0][Data[0]] from the first row in RAM0, and then combines data_ram[1][Data[0]] with data_ram[0][Data[0]] as the test data for the first clock cycle.

[0201] Among them, in the combined test signal, the signal data stored in the RAM with a larger number is in front, and the signal data stored in the RAM with a smaller number is in the back.

[0202] The above process of storing different parts of the signal data collected in the same clock cycle in parallel in the same order rows of multiple RAMs in the FPGA, and then reading data from the multiple RAMs respectively, and serially combining the data in the multiple RAMs into test data can be called parallel-to-serial conversion, that is, converting a parallel data stream into a serial data stream.

[0203] By selecting the above embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, the FPGA stores different parts of the signal data collected in the same clock cycle in rows of the same order in multiple RAMs in the FPGA, and combines the data read from the multiple RAMs into test data, so that the signal data can be restored.

[0204] See also Figure 6 , is a schematic diagram of a parallel-to-serial conversion provided in an embodiment of the present application.

[0205] from Figure 6 It can be seen that the signal data is stored in RAM0 and RAM1, and RAM2 stores sop, eop (End Of Packet), valid, and channel data. Among them, sop is abbreviated as s, eop is abbreviated as e, and valid is abbreviated as v. RAM3 stores zero.

[0206] The depth of each RAM is 512 bits, and the data width is 32 bits. RAM0, RAM1, RAM2, and RAM3 each contain 512 data, namely data0, ..., data511.

[0207] Each RAM includes a HEADER and 512 data, namely Data[0], Data[1], ..., Data

[511] .

[0208] FPGA sequentially takes out signal data from RAM0 and stores them in the first element of the data_ram array, i.e., data_ram[0]:[Data[0], Data[1], Data[2], ..., Data

[511] ], and sequentially takes out signal data from RAM1 and stores them in the second element of the data_ram array, i.e., data_ram[1]:[Data[0], Data[1], Data[2], ..., Data

[511] ], and then combines Data[0] and Data[0] in the two elements and stores them in org_data[0] in the org_data array. Combine Data[1] and Data[1] and store them in org_data[1] in the org_data array, and so on. After the signal data is combined, the original signal data can be obtained. In the combined data, the data in RAM 1 is in front and the data in RAM 0 is in the back.

[0209] org_data[] includes 512 signal data. For example, the first data org_data[0] is the data collected in the first clock cycle: [data_ram[1][Data[0]], data_ram[0][Data[0]]], the second data org_data[1] is the data collected in the second clock cycle: [data_ram[1][Data[1]], data_ram[0][Data[1]]], and so on.

[0210] The present application also provides a method for collecting FPGA test data, which is applied to a debugging machine connected to the FPGA. Figure 7 , is a flow chart of the fourth FPGA test data acquisition method provided in an embodiment of the present application, and the above method includes S701-S703.

[0211] S701, obtaining configuration information.

[0212] The configuration information indicates the termination condition and sampling depth of signal data acquisition.

[0213] In S1101, the configuration information is input by the user through the termination condition configuration interface of the debugging machine. The termination condition refers to the condition under which the FPGA delays and stops signal data acquisition. The sampling depth refers to the depth of the signal data acquired by the FPGA.

[0214] In a possible embodiment, the termination condition includes one or more trigger conditions; when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0215] The above embodiment is selected. Since the termination condition includes one or more trigger conditions, and when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions. By setting the termination condition, the condition for FPGA delay stop signal data collection can be determined.

[0216] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0217] By selecting the above embodiment, the trigger condition can be constructed through the signal value, the trigger threshold, and the relationship between the signal value and the trigger threshold, and then the termination condition of signal data acquisition can be determined according to the trigger condition.

[0218] In a possible embodiment, the configuration information further indicates a trigger position, where the trigger position is the order of signal data collected by the FPGA in a clock cycle that meets the termination condition in the test data.

[0219] When the above embodiment is selected, since the trigger position in the configuration information is the order of the signal data collected in the clock cycle that meets the termination condition in the test data, the amount of valid signal data in the test data read by the FPGA from the RAM can be controlled by the trigger position and the sampling depth.

[0220] S702, sending configuration information to the FPGA, so that the FPGA collects signal data processed by the FPGA according to the configuration information, generates a test file containing test data in the collected signal data, and sends the test file to the debugging machine.

[0221] The test data is signal data collected continuously in a sampling depth of clock cycles, and the test data includes signal data collected in a clock cycle that meets a termination condition.

[0222] S703, receiving a test file sent by the FPGA.

[0223] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0224] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0225] In one possible embodiment, see Figure 8 , is a flowchart of a fifth FPGA test data acquisition method provided in an embodiment of the present application, and Figure 7 Compared with the embodiment shown in the figure, after the above S703, S801 is further included.

[0226] S801, displaying a signal waveform represented by a test file in a signal waveform display interface.

[0227] See also Fig. 9 , which is a schematic diagram of a signal waveform display interface of a debugging machine provided in an embodiment of the present application.

[0228] from Fig. 9 It can be seen that when channel[31:0]=0000, data[63:0]=0000, eop=0, sop=1, valid=1, the waveform of Signals is displayed. Fig. 9 The waveform on the right in the middle is the displayed waveform.

[0229] By selecting the above embodiment, the debugging machine displays the signal waveform represented by the test file in the signal waveform display interface, and the user can debug and locate the FPGA according to the signal waveform.

[0230] In one possible embodiment, see Fig.10 , is a flow chart of a sixth FPGA test data acquisition method provided in an embodiment of the present application, and Figure 7 Compared with the embodiment shown, the above S701 can be implemented by S701A-S701B.

[0231] S701A, receiving a configuration information input signal.

[0232] The configuration information input signal is used to indicate the values ​​of the parameters contained in the configuration information to be generated.

[0233] In S701A, the values ​​of the parameters included in the configuration information may be manually input by the user through the termination condition configuration interface of the debugging machine, or may be preset. Alternatively, the user determines the values ​​of the parameters included in the configuration information by inputting a command line.

[0234] The parameters included in the configuration information may include a termination condition and a sampling depth. For example, the termination condition includes data[63:0]==xxxx, sop==R, eop==X, valid==1 and channel[31:0]==89ECABCD, and the sampling depth is 512.

[0235] See also Fig.11 , which is a schematic diagram of a termination condition configuration interface of a debugging machine provided in an embodiment of the present application.

[0236] from Fig.11 It can be seen that the termination condition is composed of five trigger conditions, including signal value, logical relationship, relationship symbol, base and trigger threshold.

[0237] Trigger condition 1 is data[63:0]==XXXX, trigger condition 2 is sop==R, trigger condition 3 is eop==X, trigger condition 4 is valid==1, and trigger condition 5 is Channel[31:0]==89ECABCD.

[0238] The logical relationship between the five trigger conditions is AND, that is, when the five trigger conditions are met at the same time, the FPGA delays and stops signal data acquisition.

[0239] In addition, the base number of trigger conditions 1 and 5 is [H], that is, a hexadecimal number, and the base number of trigger conditions 2-4 is [B], that is, a binary number.

[0240] S701B, generating configuration information according to the configuration information input signal.

[0241] Specifically, the debugging machine generates the configuration information according to the values ​​of the parameters contained in the configuration information to be generated.

[0242] By using the above embodiment, the debugging machine generates configuration information according to the configuration information input signal, so that the FPGA collects signal data according to the configuration information, thereby completing the FPGA test data collection process.

[0243] See also Fig.12 , is a structural diagram of an SSA logical IP provided in an embodiment of the present application.

[0244] Among them, the SSA (Signal Scope Analyzer) logic IP (Intellectual Property) includes hreg_config (Hardware Register Configuration) unit, gen_trigger (Generation Trigger) unit, and data_dump (data dump) unit. The gen_trigger unit is used to generate trigger signals, and the data_dump unit is used to save and send test files.

[0245] The data_dump unit reads the test data from the collected signal data, generates the test file, and then outputs the test file to the debugging machine.

[0246] After receiving the termination condition in the configuration information through the CPU (Central Processing Unit) read / write bus of the debugging machine, the hreg_config unit starts to configure the termination condition.

[0247] In addition, SSA logic IP is mainly used to implement the following functions:

[0248] Function 1, provides register read and write interface, uses CPU read and write bus interface, supports multiple CPU transmission modes, such as serial port / network port / PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus), etc.

[0249] Function 2 provides a set of sampling data interfaces. The sampling clock and the signal data to be collected are directly connected to the SSA logic IP, supporting a single set of clock domains.

[0250] Function 3 supports trigger condition setting and 6 relationship symbols: ==, >=, <=, >, <, !=.

[0251] Function 4 supports trigger threshold configuration. In the case of single bit, the trigger threshold supports configuration: x (don't care), 0 (low level), 1 (high level), R (rising edge), F (falling edge), B (rising edge or falling edge). In the case of multiple bits, the trigger threshold supports configuration of any value and supports mask.

[0252] Function 5, supports up to a preset number of groups of trigger condition configurations, and can configure the logical relationship between adjacent trigger conditions. Supports configuration of logical relationships and / or, for example, supports up to 8 groups of trigger condition configurations, supporting A&B&C, A|B|C, A&B|C, A|B&C, etc.;

[0253] Function 6, supports adjusting the trigger position.

[0254] Function 7, supports sampling depth configuration.

[0255] Function 8, the total bit width of the signal data is unlimited, but if the bit width of the signal data is large, greater than the bit width of a RAM, the signal data collected in one clock cycle cannot all be written into the same RAM, so it will occupy multiple RAMs.

[0256] Function 9 supports test file upload and can provide a standard FIFO (First Input First Output) interface to output test files to the debugger.

[0257] Function 10, supports data verification and data retransmission.

[0258] Function 11 does not support multiple consecutive triggers, but only supports single triggers. If the termination condition is met multiple times, only the first time the termination condition is met will the delay stop signal data acquisition be triggered. If you need to start collecting signal data again, you need to configure "Re-collect signal data", that is, re-collect data according to the original termination condition.

[0259] See also Fig.13 , is a connection relationship diagram between an FPGA and a debugging machine provided in an embodiment of the present application.

[0260] in, Fig.13 On the left is the SSA logic IP (FPGA), which is configured in the FPGA, in the middle is the termination condition configuration interface of the debugger, and on the right is the signal waveform display interface of the debugger.

[0261] The termination condition configuration interface is as mentioned above. Fig.11 , the signal waveform display interface is shown in the previous Fig. 9 .

[0262] Corresponding to the aforementioned FPGA test data collection method, the embodiment of the present application further provides an FPGA, the FPGA is connected to a debugging machine, and the FPGA is used to perform the following operations:

[0263] receiving configuration information sent by the debugging machine; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0264] Collecting signal data processed by the FPGA, and storing the collected signal data in a random access memory RAM in the FPGA;

[0265] From the moment the collected signal data meets the termination condition, the signal data collection is stopped with a delay;

[0266] Reading test data from the signal data stored in the RAM; wherein the test data is signal data collected continuously and collected in a sampling depth of clock cycles, and the test data includes signal data collected in a clock cycle that meets the termination condition;

[0267] Generate a test file based on the test data and send the test file to the debugging machine.

[0268] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0269] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0270] In a possible embodiment, the configuration information further indicates a trigger position, which is the order of the signal data collected in the clock cycle that meets the termination condition in the test data; the FPGA is specifically used for:

[0271] From the time when the collected signal data meets the termination condition, the collection of valid signal data continues in the target clock cycle and then stops; wherein the number of the target clock cycle is the difference between the sampling depth and the trigger position;

[0272] FPGA is specifically used for:

[0273] The test data including the valid signal data is read from the signal data stored in the RAM.

[0274] When the above embodiment is selected, since the trigger position in the configuration information is the order of the signal data collected in the clock cycle that meets the termination condition in the test data, the amount of valid signal data in the test data read by the FPGA from the RAM can be controlled by the trigger position and the sampling depth.

[0275] In a possible embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, the FPGA is specifically used to:

[0276] Different parts of the signal data collected in the same clock cycle are stored in the same order rows of multiple RAMs in the FPGA;

[0277] FPGA is specifically used for:

[0278] Read data from multiple RAMs respectively;

[0279] The data read from the multiple RAMs are combined into test data, wherein each test data is composed of data recorded in rows in the same order in the multiple RAMs.

[0280] By selecting the above embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, the FPGA stores different parts of the signal data collected in the same clock cycle in rows of the same order in multiple RAMs in the FPGA, and combines the data read from the multiple RAMs into test data, so that the signal data can be restored.

[0281] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0282] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0283] The above embodiment is selected. Since the termination condition includes one or more trigger conditions, and when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions. By setting the termination condition, the condition for FPGA delay stop signal data collection can be determined.

[0284] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0285] By selecting the above embodiment, the trigger condition can be constructed through the signal value, the trigger threshold, and the relationship between the signal value and the trigger threshold, and then the termination condition of signal data acquisition can be determined according to the trigger condition.

[0286] Corresponding to the aforementioned FPGA test data collection method, the embodiment of the present application further provides a debugging machine, which is connected to the field programmable gate array FPGA, see Fig.14 , is a schematic diagram of the structure of a debugging machine provided in an embodiment of the present application, the debugging machine includes a memory 1401, a transceiver 1402, and a processor 1403:

[0287] The memory 1401 is used to store computer programs; the transceiver 1402 is used to send and receive data under the control of the processor 1403; the processor 1403 is used to read the computer program in the memory and perform the following operations:

[0288] Acquire configuration information; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0289] Sending configuration information to the FPGA so that the FPGA collects signal data processed by the FPGA according to the configuration information, generates a test file containing test data in the collected signal data, and sends the test file to the debugging machine; wherein the test data is signal data collected continuously and collected in sampling depth clock cycles, and the test data contains signal data collected in the clock cycle that meets the termination condition;

[0290] Receive the test file sent by FPGA.

[0291] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0292] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0293] Among them, Fig.14 In the embodiment, the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 1403 and various circuits of memory represented by memory 1401 are linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 1402 may be a plurality of components, namely, a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium, which transmission medium may include a wireless channel, a wired channel, an optical cable, and other transmission media. The processor 1403 is responsible for managing the bus architecture and general processing, and the memory 1401 may store data used by the processor 1403 when performing operations.

[0294] The processor 1403 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or a complex programmable logic device (CPLD). The processor 1403 may also adopt a multi-core architecture.

[0295] It should be noted here that the above-mentioned debugging machine provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effect. The parts of this embodiment that are the same as the method embodiment will not be described in detail here.

[0296] In a possible embodiment, the configuration information further indicates a trigger position, where the trigger position is the order of signal data collected by the FPGA in a clock cycle that meets the termination condition in the test data.

[0297] When the above embodiment is selected, since the trigger position in the configuration information is the order of the signal data collected in the clock cycle that meets the termination condition in the test data, the amount of valid signal data in the test data read by the FPGA from the RAM can be controlled by the trigger position and the sampling depth.

[0298] In a possible embodiment, the processor 1403 is further configured to:

[0299] The signal waveform represented by the test file is displayed in the signal waveform display interface.

[0300] By selecting the above embodiment, the debugging machine displays the signal waveform represented by the test file in the signal waveform display interface, and the user can debug and locate the FPGA according to the signal waveform.

[0301] In a possible embodiment, the processor 1403 is specifically configured to:

[0302] Receiving a configuration information input signal; wherein the configuration information input signal is used to indicate the value of a parameter included in the configuration information to be generated;

[0303] Configuration information is generated according to a configuration information input signal.

[0304] By using the above embodiment, the debugging machine generates configuration information according to the configuration information input signal, so that the FPGA collects signal data according to the configuration information, thereby completing the FPGA test data collection process.

[0305] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0306] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0307] The above embodiment is selected. Since the termination condition includes one or more trigger conditions, and when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions. By setting the termination condition, the condition for FPGA delay stop signal data collection can be determined.

[0308] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0309] By selecting the above embodiment, the trigger condition can be constructed through the signal value, the trigger threshold, and the relationship between the signal value and the trigger threshold, and then the termination condition of signal data acquisition can be determined according to the trigger condition.

[0310] Corresponding to the aforementioned FPGA test data acquisition method, the present application embodiment also provides an FPGA test data acquisition device, which is applied to FPGA, and the FPGA is connected to a debugging machine, see Fig.15 , is a structural diagram of a first FPGA test data acquisition device provided in an embodiment of the present application, the device comprising:

[0311] The information receiving module 1501 is used to receive the configuration information sent by the debugging machine; wherein the configuration information indicates the termination condition and sampling depth of the signal data acquisition;

[0312] The first acquisition module 1502 is used to acquire signal data processed by the FPGA and store the acquired signal data in a random access memory RAM in the FPGA;

[0313] The second acquisition module 1503 is used to delay and stop the signal data acquisition from the time when the acquired signal data meets the termination condition;

[0314] The data reading module 1504 is used to read the test data from the signal data stored in the RAM; wherein the test data is the signal data collected continuously and collected in the sampling depth clock cycles, and the test data includes the signal data collected in the clock cycle that meets the termination condition;

[0315] The file sending module 1505 is used to generate a test file according to the test data and send the test file to the debugging machine.

[0316] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0317] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0318] In a possible embodiment, the configuration information further indicates a trigger position, and the trigger position is the order of the signal data collected in the clock cycle that meets the termination condition in the test data;

[0319] The second acquisition module 1503 is specifically used for:

[0320] From the time when the collected signal data meets the termination condition, the collection of valid signal data continues in the target clock cycle and then stops; wherein the number of the target clock cycle is the difference between the sampling depth and the trigger position;

[0321] The data reading module 1504 is specifically used for:

[0322] The test data including the valid signal data is read from the signal data stored in the RAM.

[0323] When the above embodiment is selected, since the trigger position in the configuration information is the order of the signal data collected in the clock cycle that meets the termination condition in the test data, the amount of valid signal data in the test data read by the FPGA from the RAM can be controlled by the trigger position and the sampling depth.

[0324] In a possible embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, the first collection module 1502 is specifically configured to:

[0325] Different parts of the signal data collected in the same clock cycle are stored in the same order rows of multiple RAMs in the FPGA;

[0326] The data reading module 1504 is specifically used for:

[0327] Read data from multiple RAMs respectively;

[0328] The data read from the multiple RAMs are combined into test data, wherein each test data is composed of data recorded in rows in the same order in the multiple RAMs.

[0329] By selecting the above embodiment, when the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, the FPGA stores different parts of the signal data collected in the same clock cycle in rows of the same order in multiple RAMs in the FPGA, and combines the data read from the multiple RAMs into test data, so that the signal data can be restored.

[0330] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0331] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0332] The above embodiment is selected. Since the termination condition includes one or more trigger conditions, and when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions. By setting the termination condition, the condition for FPGA delay stop signal data collection can be determined.

[0333] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0334] By selecting the above embodiment, the trigger condition can be constructed through the signal value, the trigger threshold, and the relationship between the signal value and the trigger threshold, and then the termination condition of signal data acquisition can be determined according to the trigger condition.

[0335] Corresponding to the aforementioned FPGA test data acquisition method, the present application embodiment also provides an FPGA test data acquisition device, which is applied to a debugging machine, and the debugging machine is connected to the FPGA, see Fig.16 , is a structural diagram of a second FPGA test data acquisition device provided in an embodiment of the present application, the device comprising:

[0336] The information acquisition module 1601 is used to acquire configuration information; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition;

[0337] The information sending module 1602 is used to send configuration information to the FPGA, so that the FPGA collects signal data processed by the FPGA according to the configuration information, generates a test file containing test data in the collected signal data, and sends the test file to the debugging machine; wherein the test data is signal data collected continuously and collected in sampling depth clock cycles, and the test data includes signal data collected in the clock cycle that meets the termination condition;

[0338] The file receiving module 1603 is used to receive the test file sent by the FPGA.

[0339] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0340] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0341] In a possible embodiment, the configuration information further indicates a trigger position, where the trigger position is the order of signal data collected by the FPGA in a clock cycle that meets the termination condition in the test data.

[0342] When the above embodiment is selected, since the trigger position in the configuration information is the order of the signal data collected in the clock cycle that meets the termination condition in the test data, the amount of valid signal data in the test data read by the FPGA from the RAM can be controlled by the trigger position and the sampling depth.

[0343] In a possible embodiment, after the file receiving module receives the test file sent by the FPGA, the above device further includes:

[0344] The waveform display module is used to display the signal waveform represented by the test file in the signal waveform display interface.

[0345] By selecting the above embodiment, the debugging machine displays the signal waveform represented by the test file in the signal waveform display interface, and the user can debug and locate the FPGA according to the signal waveform.

[0346] In a possible embodiment, the information acquisition module 1601 is specifically used to:

[0347] Receiving a configuration information input signal; wherein the configuration information input signal is used to indicate the value of a parameter included in the configuration information to be generated;

[0348] Configuration information is generated according to a configuration information input signal.

[0349] By using the above embodiment, the debugging machine generates configuration information according to the configuration information input signal, so that the FPGA collects signal data according to the configuration information, thereby completing the FPGA test data collection process.

[0350] In a possible embodiment, the termination condition includes one or more trigger conditions;

[0351] When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

[0352] The above embodiment is selected. Since the termination condition includes one or more trigger conditions, and when the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions. By setting the termination condition, the condition for FPGA delay stop signal data collection can be determined.

[0353] In a possible embodiment, the trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

[0354] By selecting the above embodiment, the trigger condition can be constructed through the signal value, the trigger threshold, and the relationship between the signal value and the trigger threshold, and then the termination condition of signal data acquisition can be determined according to the trigger condition.

[0355] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned FPGA test data acquisition methods are implemented.

[0356] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0357] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0358] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any FPGA test data collection method in the above embodiments.

[0359] When the above embodiment is selected, the FPGA collects the signal data processed by the FPGA and stores the collected signal data in the RAM in the FPGA when receiving the configuration information sent by the debugger. Since the configuration information indicates the termination condition and sampling depth of the signal data collection, the FPGA stops the signal data collection after the collected signal data meets the termination condition, reads the test data from the signal data stored in the RAM, generates a test file based on the test data, and sends the test file to the debugger, thereby completing the FPGA test data collection process.

[0360] In addition, since the FPGA is connected to the debugging machine during the collection of FPGA test data, there is no need for a dedicated JTAG loading box and EDA software, which saves the cost of a dedicated JTAG loading box and EDA software, thereby reducing the debugging cost of the FPGA.

[0361] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0362] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0363] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the FPGA, debugging machine, device, and storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0364] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A method for collecting FPGA test data, characterized in that: Applied to a field programmable gate array FPGA, the FPGA is connected to a debugging machine, and the method comprises: Receiving configuration information sent by the debugging machine; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition; Collecting signal data processed by the FPGA, and storing the collected signal data in a random access memory RAM in the FPGA; From the time when the collected signal data meets the termination condition, delaying and stopping the signal data collection; Reading test data from the signal data stored in the RAM; wherein the test data is signal data collected continuously in the sampling depth clock cycles, and the test data includes signal data collected in the clock cycle that meets the termination condition; A test file is generated according to the test data, and the test file is sent to the debugging machine.

2. The method according to claim 1, characterized in that The configuration information further indicates a trigger position, where the trigger position is the order of the signal data collected in the clock cycle that meets the termination condition in the test data; After the collected signal data meets the termination condition, delaying and stopping the signal data collection includes: Starting from the time when the collected signal data meets the termination condition, continuing to collect valid signal data in a target clock cycle and then stopping the collection; wherein the number of the target clock cycles is the difference between the sampling depth and the trigger position; The step of reading the test data from the signal data stored in the RAM comprises: The test data including the valid signal data is read from the signal data stored in the RAM.

3. The method according to claim 1, characterized in that When the amount of signal data collected in one clock cycle is greater than the data bit width of a RAM, storing the collected signal data in a random access memory RAM in the FPGA includes: storing different parts of the signal data collected in the same clock cycle in rows of the same order in a plurality of RAMs in the FPGA; The step of reading the test data from the signal data stored in the RAM comprises: Reading data from the plurality of RAMs respectively; The data read from the plurality of RAMs are combined into test data, wherein each test data is composed of data recorded in rows of the plurality of RAMs in the same order.

4. The method according to any one of claims 1 to 3, characterized in that The termination condition includes one or more trigger conditions; When the termination condition includes multiple trigger conditions, there is a logical relationship between adjacent trigger conditions.

5. The method according to claim 4, characterized in that The trigger condition includes: a signal value, a trigger threshold, and a relationship symbol between the signal value and the trigger threshold.

6. An FPGA, characterized in that: The field programmable gate array FPGA is connected to a debugging machine, and the FPGA is used to perform the following operations: Receiving configuration information sent by the debugging machine; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition; Collecting signal data processed by the FPGA, and storing the collected signal data in a random access memory RAM in the FPGA; From the time when the collected signal data meets the termination condition, delaying and stopping the signal data collection; Reading test data from the signal data stored in the RAM; wherein the test data is signal data collected continuously in the sampling depth clock cycles, and the test data includes signal data collected in the clock cycle that meets the termination condition; A test file is generated according to the test data, and the test file is sent to the debugging machine.

7. An FPGA test data acquisition device, characterized in that: Applied to a field programmable gate array FPGA, the FPGA is connected to a debugging machine, and the device comprises: An information receiving module, used to receive configuration information sent by a debugging machine; wherein the configuration information indicates the termination condition and sampling depth of signal data acquisition; A first acquisition module, used for acquiring signal data processed by the FPGA, and storing the acquired signal data in a random access memory RAM in the FPGA; A second acquisition module, used for delaying and stopping signal data acquisition from the time when the acquired signal data meets the termination condition; A data reading module, used to read test data from the signal data stored in the RAM; wherein the test data is signal data collected continuously in the sampling depth clock cycles, and the test data includes signal data collected in the clock cycle that meets the termination condition; The file sending module is used to generate a test file according to the test data and send the test file to the debugging machine.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1 to 5 are implemented.

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