Data communication system and communication method thereof

Abstract

The present invention relates to the field of data communication technology, and in particular to a data communication system and a communication method thereof, wherein the data communication system comprises: a CPU, a master IC module, a slave IC module and a counting module. The present invention enables one time to represent the transmission of 4 bits of data by adding a code reduction unit, a decoding unit, a counting unit, a counting detection and verification unit and a bit comparison unit, which greatly saves the time for the CPU to process data, and because the transmission volume is small at one time, it can greatly reduce the CPU's occupancy time and improve the data communication rate in many aspects; only according to the demand, the corresponding enable signal line is enabled, which can perfectly avoid the data loss during the transmission process, and through the processing of the code reduction unit and the decoding unit, the conversion is performed between 16 lines and 4 lines, which solves the problem that the data communication enable signal lines are too many and complicated during chip layout and wiring.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a data communication system and a communication method thereof. Background Art

[0002] Data communication refers to the use of transmission channels to connect data terminals with computers to achieve sharing of hardware, software and information resources between data terminals in different locations. According to the transmission medium, data communication is divided into wired data communication and wireless data communication.

[0003] At present, the data communication between chips usually adopts direct communication, including: SPI bus communication (Serial Peripheral Interface), IIC bus communication (Inter-Integrated Circuit bus), UART bus communication (Universal Asynchronous Receiver Transmitter);

[0004] 1. SPI bus communication. In the current digital chip SPI bus communication technology, the SPI serial bus is mainly used for data communication between off-chip chips. In the SPI bus communication, there is only one host (Master) and one or more slaves (Slave). The host and the slave have four data enable signal lines, mainly including: serial clock line SCLK, master-out slave-in enable signal line MOSI, master-in slave-out enable signal line MISO and chip select enable signal line CS. The four data lines of the host and the slave are connected respectively. When the chip select enable signal line CS on the host is enabled, data communication between chips can be realized;

[0005] 2. IIC bus communication mainly uses the host broadcast addressing to find the slave device that needs to communicate with it, so as to establish communication with the slave device. It has two bidirectional enable signal lines, one for sending and receiving data, and one for clock synchronization. IIC bus communication is mostly used for master-slave communication between the master controller and the slave device. It is used in occasions with small data volume, short transmission distance, and intelligently has one host at any time.

[0006] 3. UART bus communication mainly has two enable signal lines, one for receiving data and one for sending data. It is an asynchronous transceiver. Therefore, it does not require a clock signal. It mainly matches the baud rate to communicate between the two machines.

[0007] Direct communication is very likely to cause data loss when the amount of data to be communicated is large. In addition, the data transmission time is long and the CPU processing time is long. Summary of the invention

[0008] The technical problem to be solved by the present invention is: in order to solve the technical problem that in the existing direct communication method, when the communication data volume is large, data is very easy to be lost and the CPU processing time is long, the present invention provides a data communication system and a communication method thereof. By improving the data communication method, when the communication data volume is large, data is not easily lost and the CPU processing time can be shortened.

[0009] The technical solution adopted by the present invention to solve the technical problem is: a data communication system, comprising: a CPU, a main IC module, a slave IC module and a counting module, the main IC module comprising: a code reduction enabling unit and a code reduction unit, the code reduction enabling unit is connected to the CPU, and the code reduction enabling unit is connected to the code reduction unit; the slave IC module comprises: a decoding unit, a decoding enabling unit, a standard data pre-storage unit and a first Buffer cache unit, the decoding enabling unit is connected to the CPU, the code reduction unit is connected to the decoding unit, the decoding enabling unit is connected to the decoding unit, the decoding unit is connected to the standard data pre-storage unit, and the standard data pre-storage unit is connected to the first Buffer cache unit. The storage unit is connected to the first Buffer cache unit; the counting module includes: a counting unit, a counting detection and verification unit, a counting reset unit, a bit comparison unit and a second Buffer cache unit, the code reduction unit and the decoding unit are both connected to the counting unit, the counting reset unit is connected to the counting unit, the counting unit is connected to the counting detection and verification unit, the counting detection and verification unit is connected to the bit comparison unit, the first Buffer cache unit is connected to the bit comparison unit, the bit comparison unit is connected to the second Buffer cache unit, and the second Buffer cache unit is connected to the CPU.

[0010] Therefore, by adding the code reduction unit, the decoding unit, the counting unit, the counting detection and verification unit and the bit comparison unit, enabling once can represent the transmission of 4 bits of data at a time, which greatly saves the time for the CPU to process data, and because the transmission volume is small at a time, it can greatly reduce the CPU occupancy time and improve the data communication rate in many aspects; only according to the needs, the corresponding enable signal line is enabled, which can perfectly avoid the data loss that occurs during the transmission process, and through the processing of the code reduction unit and the decoding unit, the conversion between 16 lines and 4 lines is performed, which solves the problem of many and complicated data communication enable signal lines during chip layout and wiring; in addition, by adding the counting unit, the counting detection and verification unit and the bit comparison unit, the layout of the data detection and verification part during data transmission is completed, and the control and feedback of the correctness of data transmission during data transmission are improved, so that the data transmission result can be correctly processed in real time.

[0011] Furthermore, the abbreviated code enabling unit is used to enable or disable the abbreviated code.

[0012] Furthermore, the coding reduction unit includes: an encoder; the coding reduction unit is used to process the 16-bit input into a 4-bit output through the encoder.

[0013] Furthermore, the code reduction unit and the decoding unit are connected in a bidirectional manner, thereby establishing a connection between the master IC module and the slave IC module.

[0014] Furthermore, the decoding unit includes: a decoder; the decoding unit is used to parse the received data compression packet, convert the 4-bit input into a 16-bit output after decoding; the decoding enabling unit is used to start or not use decoding.

[0015] Furthermore, the standard data pre-storage unit includes: a data array consisting of 16 hexadecimal data; the standard data pre-storage unit responds to the data to be sent by the host and reacts; the first Buffer cache unit includes: an 8-bit Buffer space consisting of high 4 bits and low 4 bits; the first Buffer cache unit is used to collect and cache the data after the slave responds.

[0016] Furthermore, the counting unit is used to individually count the number of times the four enable signal lines are enabled, and to feed back the counting results to the counting detection and verification unit; the counting detection and verification unit is used to verify the enable calculation results of the current enable signal line through the counting unit, and to determine the consistency between the actual data sending results and the desired data transmission results.

[0017] Furthermore, the counting Reset unit is used to reset data after a data transmission is completed; the bit comparison unit is used to perform a one-to-one comparison of the data collected by the first Buffer cache unit and the counting unit.

[0018] Furthermore, the counting unit is connected to a CLK clock.

[0019] A communication method of a data communication system comprises the following steps:

[0020] S1. Open up an address space at one end in the master IC module and the slave IC module, pre-store data from 0 to F in it, and correspond one-to-one with the output of the coding unit and the input of the decoding unit, and each data occupies 4 bits of space;

[0021] S2, when the master IC module communicates with the slave IC module, according to the configured input-output correspondence table, the corresponding enable signal line is enabled according to which four-bit data is to be sent, and after passing through the code reduction unit, four enable signal lines are led out from the inside of the master IC module;

[0022] S3, the code reduction unit inputs 16 enable signal lines and outputs 4 enable signal lines after being processed by the code reduction unit;

[0023] S4, adding another decoding unit in the slave, decoding the 4 enable signal lines into 16 lines, and connecting them one by one to the standard data pre-storage unit;

[0024] S5. After enabling the corresponding data, the corresponding data will be automatically filled into the first buffer cache unit of the slave every two times, forming 8-bit 1-byte data. The corresponding data will be enabled as the high 4 bits first, and then the corresponding data will be enabled as the low 4 bits.

[0025] S6. Each enable signal line must have a separate count. Each time it is enabled, the count is incremented by 1. The counting unit must simultaneously collect the states of the four enable signal lines. The states of the four enable signal lines correspond to the data in the first buffer cache unit one by one. After the collection, a total of 4 bits of feedback data are obtained;

[0026] S7, the counting detection and verification unit collects the data in the first buffer cache unit and first collects the lower four bits of data, and compares the data collected by the first buffer cache unit and the counting unit one by one through the bit comparison unit;

[0027] S8. If the comparison results are the same, output 1; if the comparison results are different, output 0 and store the result in the second Buffer cache unit;

[0028] The operations of step S9, step S7 and step S8 are performed twice in one cycle. The result of the first calculation is placed in the upper 4 bits of the Buffer, and the result of the second calculation is placed in the lower 4 bits of the Buffer. After two cycles, 8-bit 1-byte data is formed. The counting and detection verification results are fed back to the counting module. The counting results and the data detection and verification results are used to double verify the correctness of the data transmission.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] By adding a code reduction unit, a decoding unit, a counting unit, a counting detection and verification unit and a bit comparison unit, enabling once can represent a transmission of 4 bits of data at a time, which greatly saves the time for the CPU to process data, and because of its small transmission volume at a time, it can greatly reduce the CPU occupancy time and improve the data communication rate in many aspects; only according to the needs, the corresponding enable signal line is enabled, which can perfectly avoid the data loss that occurs during the transmission process, and through the processing of the code reduction unit and the decoding unit, the conversion between 16 lines and 4 lines is performed, which solves the problem of many and complicated data communication enable signal lines during chip layout and wiring; in addition, by adding a counting unit, a counting detection and verification unit and a bit comparison unit, the layout of the data detection and verification part during data transmission is completed, and the control and feedback of the correctness of data transmission during data transmission are improved, so that the data transmission results can be correctly processed in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0032] Figure 1 A framework diagram of a data communication system of the present invention;

[0033] Figure 2 A schematic diagram of a data array of a standard data pre-storage unit of the present invention;

[0034] Figure 3 Schematic diagram of the 8-bit space of the second Buffer cache unit of the present invention;

[0035] Figure 4 It is a schematic diagram of 4- and 16-line conversion of the decoding unit and the code reduction unit of the present invention;

[0036] Figure 5 It is a schematic diagram of the connection between the counting detection and verification unit of the present invention, the first buffer cache unit in the slave IC module, and the XOR gate circuit in the bit comparison unit;

[0037] Figure 6 A schematic diagram of the connection between the decoding unit of the present invention and the buffer pre-stored data array in a one-to-one correspondence;

[0038] Figure 7The figure is a flow chart of the communication method of the data communication system of the present invention.

[0039] In the figure: 1. CPU; 2. Main IC module; 201. Code reduction enabling unit; 202. Code reduction unit; 3. Slave IC module; 301. Decoding unit; 302. Decoding enabling unit; 303. Standard data pre-storage unit; 304. First Buffer cache unit; 4. Counting module; 401. Counting unit; 402. Counting detection and verification unit; 403. Counting Reset unit; 404. Bit comparison unit; 405. Second Buffer cache unit; 5. CLK clock. DETAILED DESCRIPTION

[0040] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0041] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] like Figures 1 to 6As shown, it is the best embodiment of the present invention. The data communication system of this embodiment includes: CPU1, main IC module 2, slave IC module 3 and counting module 4. The main IC module 2 includes: code reduction enabling unit 201 and code reduction unit 202. Code reduction enabling unit 201 is connected to CPU1, and code reduction enabling unit 201 is connected to code reduction unit 202; slave IC module 3 includes: decoding unit 301, decoding enabling unit 302, standard data pre-storage unit 303 and first Buffer cache unit 304. Decoding enabling unit 302 is connected to CPU1, code reduction unit 202 is connected to decoding unit 301, decoding enabling unit 302 is connected to decoding unit 301, decoding unit 301 is connected to standard data pre-storage unit 303, and standard data pre-storage unit 304 is connected to CPU1. 3 is connected to the first Buffer cache unit 304; the counting module 4 includes: a counting unit 401, a counting detection and verification unit 402, a counting reset unit 403, a bit comparison unit 404 and a second Buffer cache unit 405, the code reduction unit 202 and the decoding unit 301 are connected to the counting unit 401, the counting reset unit 403 is connected to the counting unit 401, the counting unit 401 is connected to the counting detection and verification unit 402, the counting detection and verification unit 402 is connected to the bit comparison unit 404, the first Buffer cache unit 304 is connected to the bit comparison unit 404, the bit comparison unit 404 is connected to the second Buffer cache unit 405, and the second Buffer cache unit 405 is connected to CPU1. Therefore, by adding the code reduction unit 202, the decoding unit 301, the counting unit 401, the counting detection and verification unit 402 and the bit comparison unit 404, enabling once can represent the transmission of 4 bits of data at a time, which greatly saves the time for CPU1 to process data, and because of its small transmission volume at a time, it can greatly reduce the occupancy time of CPU1, and improve the data communication rate in many aspects; only according to the needs, the corresponding enable signal line is enabled, which can perfectly avoid the data loss that occurs during the transmission process, and through the processing of the code reduction unit 202 and the decoding unit 301, the conversion between 16 lines and 4 lines is performed, which solves the problem of many and complicated data communication enable signal lines during chip layout and wiring; in addition, by adding the counting unit 401, the counting detection and verification unit 402 and the bit comparison unit 404, the layout of the data detection and verification part during data transmission is completed, and the control and feedback of the correctness of data transmission during data transmission are improved, so as to make correct processing of the data transmission result in real time.

[0044] Specifically, the code reduction unit 202 and the decoding unit 301 are both connected to the counting unit 401 , which means that the counting unit 401 collects data on the enable signal lines of the master IC module 2 and the slave IC module 3 .

[0045] In this embodiment, the code reduction enabling unit 201 is used to start or not use the code reduction; the code reduction unit 202 includes: an encoder; the code reduction unit 202 is used to process the 16-bit input into a 4-bit output through the encoder.

[0046] In this embodiment, the connection mode between the code reduction unit 202 and the decoding unit 301 is a bidirectional connection, thereby establishing a connection between the master IC module 2 and the slave IC module 3.

[0047] In this embodiment, the decoding unit 301 includes: a decoder; the decoding unit 301 is used to parse the received data compression packet, and convert the 4-bit input into a 16-bit output after decoding; the decoding enable unit 302 is used to start or not use decoding; the standard data pre-storage unit 303 includes: a data array composed of 16 hexadecimal data; the standard data pre-storage unit 303 responds to the data to be sent by the host and reacts; the first buffer cache unit 304 includes: an 8-bit buffer space composed of high 4 bits and low 4 bits; the first buffer cache unit 304 is used to collect and cache the data after the slave responds.

[0048] In this embodiment, the counting unit 401 is used to count the number of times the four enable signal lines are enabled separately, and the counting result is fed back to the counting detection verification unit 402; the counting detection verification unit 402 is used to verify the enable calculation result of the current enable signal line through the counting unit 401, and to determine the consistency between the actual data transmission result and the desired data transmission result; the counting reset unit 403 is used to reset the data after a data transmission is completed; the bit comparison unit 404 is used to compare the data collected by the first buffer cache unit 304 with the counting unit 401 one by one.

[0049] In this embodiment, the counting unit 401 is connected to a CLK clock 5 .

[0050] like Figure 7 As shown, a communication method of a data communication system comprises the following steps:

[0051] S1, open up an address space at one end in the master IC module 2 and the slave IC module 3, pre-store data from 0 to F in it, and correspond one-to-one with the output of the code reduction unit 202 and the input of the decoding unit 301, and each data occupies 4 bits of space;

[0052] S2, when the master IC module 2 and the slave IC module 3 communicate, according to the configured input-output correspondence table, which four-bit data is to be sent, the corresponding enable signal line is enabled, and after passing through the code reduction unit 202, four enable signal lines are drawn from the inside of the master IC module 2;

[0053] S3, the code reduction unit 202 inputs 16 enable signal lines and outputs 4 enable signal lines after being processed by the code reduction unit 202;

[0054] S4, add another decoding unit 301 in the slave, decode the 4 enable signal lines into 16 lines, and connect them one by one to the standard data pre-storage unit 303;

[0055] S5. After enabling the corresponding data, the corresponding data is automatically filled into the first buffer cache unit 304 of the slave every two times to form 8-bit 1-byte data. The corresponding data is first enabled as the high 4 bits, and then the corresponding data is enabled as the low 4 bits.

[0056] S6. Each enable signal line must have a separate count. Each time it is enabled, the count is incremented by 1. The counting unit 401 must simultaneously collect the states of the four enable signal lines. The states of the four enable signal lines correspond to the data in the first buffer unit 304 one by one. After the collection, a total of 4 bits of feedback data are obtained.

[0057] S7, the counting detection and verification unit 402 collects the data in the first buffer cache unit 304 and first collects the lower four bits of data, and compares the data collected by the first buffer cache unit 304 and the counting unit 401 one by one through the bit comparison unit 404;

[0058] S8. If the comparison results are the same, output 1; if the comparison results are different, output 0 and store the result in the second Buffer cache unit 405;

[0059] The operations of step S9, step S7 and step S8 are performed twice in one cycle. The result of the first calculation is placed in the upper 4 bits of the Buffer, and the result of the second calculation is placed in the lower 4 bits of the Buffer. After two cycles, 8-bit 1-byte data is formed. The counting and detection verification results are fed back to the counting module 4. The counting result and the data detection and verification result are used to double verify the correctness of the data transmission.

[0060] It should be noted that: 1. In step S3, the space for wiring inside the entire chip can be saved;

[0061] 2. In step S4, the 4 and 16 lines of the decoding unit 301 and the code reduction unit 202 are converted as follows: Figure 4 As shown, since the pre-stored data is 16 data, the corresponding relationship between 4 lines and 16 data is shown in Table 1. The host only needs to enable the enable signal line corresponding to the data to be sent, which means that 4 bits of data have been sent once. Only one enable signal line can be enabled at a time;

[0062] 3. In step S7, the bit comparison unit 404 is actually an XOR gate circuit. If the two inputs are the same after XOR, the output result is 1, and if they are different, the output result is 0. Therefore, a four-bit XOR gate circuit is required to compare the four-bit collected data one by one.

[0063] Table 1 Correspondence table of 16 inputs and 4 outputs of the code reduction unit 202

[0064]

[0065] Table 2 Decoding unit 301 4 input 16 output correspondence table

[0066]

[0067]

[0068] Take an example to illustrate: suppose the host wants to send 0XFF to the slave, 0XFF is converted into binary as 11111111. Since only one data enable signal line can be enabled, to send one byte of data, that is, 8-bit data, the enable signal line corresponding to F needs to be enabled twice; according to the corresponding table of abbreviation and decoding input and output, the sending needs to make Y15 at the output end of the decoding unit 301 in the slave IC module 3 1, therefore, the four input enable signal lines of the decoding unit 301 need to be 1, and the four input enable signal lines of the decoding unit 301 and the four output enable signal lines of the abbreviation unit 202 are connected one by one, that is, A15 of the abbreviation unit 202 needs to be enabled; to the master IC module 2, only the enable signal line at the A15 end needs to be enabled, and the others are not enabled; therefore, to receive 0XFF, the slave needs to enable A 15 enable signal line, then, after passing through the code reduction unit 202 and the decoding unit 301, the F corresponding to the data array in the standard data pre-stored courtyard in the slave is found. After finding it, the slave IC module 3 copies F to the first Buffer cache unit 304 in the slave IC module 3 and places it in the high 4 bits. At the same time, the counter hung by the corresponding enable signal line is increased by 1. At the same time, the counting detection and verification unit 402 collects data and then transmits the data to the input port corresponding to the bit comparison unit 404. At the same time, the bit comparison unit 404 transmits the data collected from the first Buffer cache unit 304 in the IC module 3 to each corresponding input port of the bit comparison unit 404; the connection relationship between the counting detection and verification unit 402 and the Buffer cache unit in the slave IC module 3 and the XOR gate circuit in the bit comparison unit 404 is as follows Figure 5As shown; after the calculation by the bit comparison unit 404, the data detection and verification result is placed in the external second Buffer cache unit 405 and then output to the CPU1 master control; because the second data is still F, the A15 enable signal line is still enabled, and then after the code reduction decoding, the F obtained after the second enable is placed in the lower 4 bits, and the counter connected to the corresponding enable signal line is increased by 1, which can represent that the transmission of one byte of data has been completed; when one data transmission is completed, the counting Reset unit 403 continues to count and reset in preparation for the next data transmission.

[0069] In summary, the present invention enables one time to represent the transmission of 4 bits of data at one time by adding the code reduction unit 202, the decoding unit 301, the counting unit 401, the counting detection and verification unit 402 and the bit comparison unit 404, which greatly saves the time for CPU1 to process data, and because of its small transmission volume at one time, it can greatly reduce the occupancy time of CPU1, and improve the data communication rate in many aspects; only according to the demand, the corresponding enable signal line is enabled, which can perfectly avoid the data loss that occurs during the transmission process, and through the processing of the code reduction unit 202 and the decoding unit 301, the conversion between 16 lines and 4 lines is performed, which solves the problem that there are many and complicated data communication enable signal lines during chip layout and wiring; in addition, by adding the counting unit 401, the counting detection and verification unit 402 and the bit comparison unit 404, the layout of the data detection and verification part during data transmission is completed, and the control and feedback of the correctness of data transmission during data transmission are improved, so that the data transmission result can be correctly processed in real time.

[0070] The above description is based on the ideal embodiment of the present invention. Through the above description, relevant personnel can make various changes and modifications without departing from the technical concept of the present invention. The technical scope of the present invention is not limited to the content of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A data communication system, characterized in that: include: CPU (1), and A main IC module (2), wherein the main IC module (2) comprises: A code reduction enabling unit (201) and a code reduction unit (202), wherein the code reduction enabling unit (201) is connected to the CPU (1), and the code reduction enabling unit (201) is connected to the code reduction unit (202); A slave IC module (3), wherein the slave IC module (3) comprises: A decoding unit (301), a decoding enabling unit (302), a standard data pre-storage unit (303) and a first buffer cache unit (304), wherein the decoding enabling unit (302) is connected to the CPU (1), the coding unit (202) is connected to the decoding unit (301), the decoding enabling unit (302) is connected to the decoding unit (301), the decoding unit (301) is connected to the standard data pre-storage unit (303), and the standard data pre-storage unit (303) is connected to the first buffer cache unit (304); A counting module (4), wherein the counting module (4) comprises: A counting unit (401), a counting detection and verification unit (402), a counting reset unit (403), a bit comparison unit (404) and a second buffer cache unit (405), wherein the code reduction unit (202) and the decoding unit (301) are both connected to the counting unit (401), the counting reset unit (403) is connected to the counting unit (401), the counting unit (401) is connected to the counting detection and verification unit (402), the counting detection and verification unit (402) is connected to the bit comparison unit (404), the first buffer cache unit (304) is connected to the bit comparison unit (404), the bit comparison unit (404) is connected to the second buffer cache unit (405), and the second buffer cache unit (405) is connected to the CPU (1); The code reduction unit (202) comprises: Encoder; The coding unit (202) is used to process the 16-bit input into a 4-bit output through an encoder; The decoding unit (301) comprises: Decoder; The decoding unit (301) is used to parse the received data compression packet and convert the 4-bit input into a 16-bit output after decoding; The decoding enabling unit (302) is used to enable or disable decoding.

2. The data communication system according to claim 1, characterized in that: The abbreviation enabling unit (201) is used to enable or disable abbreviation.

3. The data communication system according to claim 1, characterized in that: The coding unit (202) and the decoding unit (301) are connected in a bidirectional manner.

4. The data communication system according to claim 1, characterized in that: The standard data pre-storage unit (303) comprises: A data array consisting of 16 hexadecimal data; The standard data pre-storage unit (303) responds to the data to be sent by the main IC module (2) and reacts; The first buffer cache unit (304) includes: The 8-bit buffer space consists of the high 4 bits and the low 4 bits; The first buffer unit (304) is used to collect and cache the data responded by the slave IC module (3).

5. The data communication system according to claim 1, characterized in that: The counting unit (401) is used to count the number of times the four enable signal lines are enabled individually, and feed back the counting result to the counting detection and verification unit (402); The counting detection verification unit (402) is used to verify the enable calculation result of the current enable signal line through the counting unit (401), and to determine the consistency between the actual data transmission result and the desired data transmission result.

6. The data communication system according to claim 1, characterized in that: The counting Reset unit (403) is used to reset data after a data transmission is completed; The bit comparison unit (404) is used to perform a one-to-one comparison of the bits collected by the first buffer unit (304) and the data collected by the counting unit (401).

7. The data communication system according to claim 1, characterized in that: The counting unit (401) is connected to a CLK clock (5).

8. A communication method of a data communication system according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1, opening an address space at one end in the master IC module (2) and the slave IC module (3), pre-storing data from 0 to F therein, and corresponding one to one with the output of the code reduction unit (202) and the input of the decoding unit (301), with each data occupying 4 bits of space; S2, when the master IC module (2) and the slave IC module (3) communicate, according to the configured input-output correspondence table, which four-bit data is to be sent, the corresponding enable signal line is enabled, and after passing through the code reduction unit (202), four enable signal lines are led out from the inside of the master IC module (2); S3, the coding reduction unit (202) inputs 16 enable signal lines, and after being processed by the coding reduction unit (202), outputs 4 enable signal lines; S4, adding another decoding unit (301) to the slave IC module (3), decoding the four enable signal lines into 16 lines, and connecting them one by one to the standard data pre-storage unit (303); S5, after enabling the corresponding data, each time it is enabled twice, the corresponding data will be automatically filled into the first buffer cache unit (304) in the slave IC module (3) to form 8-bit 1-byte data, first enabling the corresponding data as the upper 4 bits, and then enabling the corresponding data as the lower 4 bits; S6. Each enable signal line shall have a separate count. Each time it is enabled, the count is incremented by 1. The counting unit (401) shall simultaneously collect the states of the four enable signal lines. The states of the four enable signal lines correspond to the data in the first buffer cache unit (304) one by one. After the collection, a total of 4 bits of feedback data are obtained. S7, the counting detection and verification unit (402) will collect the data in the first buffer cache unit (304), first collect the lower four bits of data, and compare the data collected by the first buffer cache unit (304) and the counting unit (401) one by one through the bit comparison unit (404); S8. If the comparison results are the same, output 1; if the comparison results are different, output 0 and store the results in the second Buffer cache unit (405); S9, step S7 and step S8 are operated twice in one cycle. The result of the first calculation is placed in the upper 4 bits of the buffer, and the result of the second calculation is placed in the lower 4 bits of the buffer. After two cycles, 8-bit 1-byte data is formed. The counting and detection verification results are fed back to the backward counting module (4). The counting result and the data detection and verification result are used to double verify the correctness of the data transmission.

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