A chip layout system for front-end and back-end design collaboration

Abstract

The present application relates to the field of chip design technology, and in particular to a chip layout system for front-end and back-end design collaboration. The system includes: a processor and a memory storing a computer program. When the computer program is executed by the processor, the following steps are implemented: extracting attribute information of each module from initial code information of the front-end design to form topology information, using physical constraints of the back-end design as basic parameter information, generating a chip layout image through a generation model and a discrimination model based on the topology information and the basic parameter information, and when the discrimination result fails, timely generating a warning message for the front-end designer to make code adjustments, and when the discrimination result passes, providing the back-end designer with a first layout image as a layout reference, thereby improving the convenience of chip front-end and back-end design collaboration, thereby improving the overall efficiency of chip design.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a chip layout system for front-end and back-end design collaboration. Background Art

[0002] Chip design can be roughly divided into front-end design and back-end design. The front-end design chip mainly focuses on the functions, connection relationships, hierarchical relationships, etc. of each module. The front-end design results are usually expressed in the form of RTL code. The back-end design mainly performs physical layout and routing tasks based on the RTL code.

[0003] However, due to the different focuses of front-end designers and back-end designers, it may happen that the layout plan of the RTL code obtained by the front-end design cannot meet the physical constraints of the back-end design. Every time such a situation occurs, the back-end designers are required to communicate and collaborate with the front-end designers, which greatly increases the communication cost of the front-end and back-end design collaboration, resulting in the overall low efficiency of chip design. Therefore, how to improve the convenience of chip front-end and back-end design collaboration and thereby improve the overall efficiency of chip design has become an urgent problem to be solved. Summary of the invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is:

[0005] A chip layout system for front-end and back-end design collaboration, the system comprising: a processor and a memory storing a computer program, when the computer program is executed by the processor, the following steps are implemented:

[0006] S101, extracting type information, connection information, first size information and identification information corresponding to each module in the initial code information, wherein the type information includes a main module type, a submodule type and a virtual module type, the connection information includes a connection relationship between the corresponding module and other modules and pins, the identification information is used to indicate the main module to which the corresponding module belongs, and the first size information is used to indicate the physical size of the corresponding module.

[0007] S102, forming topology information according to type information, connection information, first size information and identification information corresponding to all modules respectively.

[0008] S103, obtaining basic parameter information of the back-end design, where the basic parameter information includes second size information and pin position information corresponding to the chip.

[0009] S104, initializing the number of iterations to one.

[0010] S105: Generate a first layout image using a pre-trained generation model according to the topology information and the basic parameter information.

[0011] S106, input the first layout image into the trained discriminant model to obtain a discrimination result, if the discrimination result is not passed, increase the number of iterations by one, return to execute step S104, until the discrimination result is passed or the number of iterations is greater than the preset number threshold, and obtain the layout result, wherein when the discrimination result is passed, the corresponding first layout image is used as the layout result, when the number of iterations is greater than the number threshold, a warning message is used as the layout result.

[0012] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solution, the chip layout system for front-end and back-end design collaboration provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0013] The present invention provides a chip layout system for front-end and back-end design collaboration, the system comprising: a processor and a memory storing a computer program, when the computer program is executed by the processor, the following steps are implemented: extracting type information, connection information, first size information and identification information corresponding to each module in the initial code information, forming topology information according to the type information, connection information, first size information and identification information corresponding to all modules, obtaining basic parameter information of the back-end design, initializing the number of iterations to one, generating a first layout image according to the topology information and the basic parameter information using a pre-trained generation model, inputting the first layout image into a trained discrimination model to obtain a discrimination result, if the discrimination result is not passed, increasing the number of iterations by one, returning to execute the step of generating the first layout image according to the topology information and the basic parameter information using the pre-trained generation model, until the discrimination result is passed or the number of iterations is greater than a preset number threshold, to obtain a layout result.

[0014] It can be seen that the attribute information of each module is extracted from the initial code information of the front-end design to form the topology information, and the physical constraints of the back-end design are used as the basic parameter information. According to the topology information and the basic parameter information, the chip layout image is generated through the generation model and the discrimination model. When the discrimination result fails, a warning message is generated in time for the front-end designer to make code adjustments. When the discrimination result passes, the first layout image is provided to the back-end designer as a layout reference, thereby improving the convenience of the front-end and back-end design collaboration of the chip, thereby improving the overall efficiency of the chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A flowchart of a computer program executed by a processor in a chip layout system for front-end and back-end design collaboration provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0018] This embodiment provides a chip layout system for front-end and back-end design collaboration, the system comprising: a processor and a memory storing a computer program, see Figure 1 , is a flow chart of a computer program executed by a processor in a chip layout system for front-end and back-end design collaboration provided by an embodiment of the present invention. When the computer program is executed by the processor, the following steps are implemented:

[0019] S101, extracting type information, connection information, first size information and identification information corresponding to each module in the initial code information, wherein the type information includes a main module type, a submodule type and a virtual module type, the connection information includes a connection relationship between the corresponding module and other modules and pins, the identification information is used to indicate the main module to which the corresponding module belongs, and the first size information is used to indicate the physical size of the corresponding module;

[0020] S102, forming topology information according to type information, connection information, first size information and identification information corresponding to all modules respectively;

[0021] S103, obtaining basic parameter information of the backend design, where the basic parameter information includes second size information and pin position information corresponding to the chip;

[0022] S104, initializing the number of iterations to one;

[0023] S105, generating a first layout image using a pre-trained generation model according to the topology information and the basic parameter information;

[0024] S106, input the first layout image into the trained discriminant model to obtain a discriminant result. If the discriminant result is not passed, increase the number of iterations by one, and return to execute step S105 until the discriminant result is passed or the number of iterations is greater than the preset number threshold, to obtain a layout result. When the discriminant result is passed, the corresponding first layout image is used as the layout result. When the number of iterations is greater than the number threshold, a warning message is used as the layout result.

[0025] Among them, the initial code information may refer to the RTL code obtained from the early design of the chip, a single module may be connected to several other modules or pins, the first size information may refer to the physical size of the corresponding module during layout design, and the first size information may include width and height.

[0026] The identification information corresponding to the module of the main module type is its own identification, and the identification information corresponding to the modules of the sub-module type and virtual module type is the identification of the main module to which it belongs, and the identifications corresponding to the main modules are different.

[0027] This embodiment is described by taking a module with a master-slave hierarchy as an example. The implementer should be aware that when there are multiple levels of modules, the identification information may represent the identification of the upper-level module to which the corresponding module belongs.

[0028] Topology information can be used to describe the connection relationship between modules, between modules and pins, and the properties of the module itself.

[0029] The basic parameter information is determined by the back-end designer according to the physical constraints of the chip. Similarly, the second size information also includes width and height, and the pin position information may include pin position information corresponding to a plurality of pins.

[0030] In a specific implementation, step S102 includes the following steps:

[0031] S1021, for any module, taking the module as a node, and taking type information, first size information, and identification information corresponding to the module as node information of the node corresponding to the module;

[0032] S1022, for a pin that is connected to any module, use the pin as a node, and use the pin type corresponding to the pin as node information of the node corresponding to the pin;

[0033] S1023, forming graph data according to all nodes and their corresponding node information, as well as the connection relationship between each node, and using the graph data as the topology information.

[0034] Among them, the pin type can include input type and output type, the connection relationship between each node can be regarded as the edge between the nodes, and the obtained graph data is undirected and unweighted graph data, that is, the edges in the graph data have no direction and edge weight.

[0035] In a specific embodiment, the pre-training process of the generative model includes:

[0036] Using the layout sample image as the first label, and using the sample topology information extracted from the code information corresponding to the layout sample image and the sample parameter information corresponding to the layout sample image as the first training sample;

[0037] Inputting the first training sample into the generation model to obtain a sample generation image;

[0038] A first loss is calculated based on the sample generated image, the first label and a preset first loss function, and the parameters of the generation model are iteratively adjusted according to the first loss until the first loss converges to obtain the pre-trained generation model.

[0039] Among them, the layout sample image may refer to a historical layout image obtained when a chip layout design task was performed historically. The historical layout image may be designed by a back-end designer. Obviously, there is a corresponding RTL code for the historical layout image, that is, the code information corresponding to the layout sample image. The sample topology information can be extracted according to the code information using step S102. There is a corresponding physical constraint for the historical layout image, that is, the sample parameter information, so that a first training sample can be formed according to the sample parameter information and the sample topology information. The layout sample image is the first label corresponding to the first training sample. Through the above method, the implementer can obtain several groups of first training samples and their corresponding first labels to form a training data set.

[0040] The first loss function may refer to a mean square error loss function, which is used to calculate the mean square error between the sample generated image and the first label.

[0041] This embodiment uses historical data for pre-training so that the generative model can learn the generalized relationship between topological information, parameter information and layout images, thereby having basic layout image generation capabilities, so that the layout image can be generated according to the actual topological information and basic parameter information and the generative model can be fine-tuned, thereby improving the efficiency of chip layout through artificial intelligence models.

[0042] In a specific implementation, step S105 includes the following steps:

[0043] S1051, inputting the topological information and the basic parameter information into the pre-trained generation model to obtain a temporary image, wherein the temporary image includes first pixel regions corresponding to each module;

[0044] S1052, determining the minimum bounding rectangle of the first pixel area corresponding to all modules in the temporary image, and obtaining a third size of the minimum bounding rectangle;

[0045] S1053, calculate the second loss according to the third size, the second size and the preset second loss function, iteratively adjust the parameters of the pre-trained generation model according to the second loss until the second loss converges, and obtain the trained generation model, and use the output of the trained generation model as the first layout image.

[0046] Among them, in the temporary image, each first pixel area is covered with a number of pixel points. According to the minimum circumscribed rectangle of the first pixel areas corresponding to all modules in the temporary image, the theoretical minimum size of the chip layout in the temporary image, that is, the third size, can be determined. By comparing the third size with the second size, it can be determined whether the chip layout in the temporary image exceeds the chip size limit.

[0047] Specifically, let the width in the third dimension be w 3 , height h 3 , the width in the second dimension is w 2 , height h 2 , then the second loss function L 2 It can be expressed as L 2 =exp[k 1 (w 3 -w 2 )]+exp[k 1 (h 3 -h 2 )], where exp can be an exponential function with e as the base, e is a natural constant, k 1 is the first adjustment coefficient, k 1 is a value greater than 1. In this embodiment, it can be set to 10. It can be seen that when w 3 Greater than w 2 or h 3 Greater than h 2 When the second loss function L 2 is a larger value, otherwise, the second loss function L 2 It is close to 0. Therefore, in order to ensure the convergence of the second loss, the generative model will adjust its own parameters so that the third size of the minimum circumscribed rectangle of the first pixel area corresponding to all modules in the output temporary image is smaller than the second size, thereby satisfying the chip size constraint in the chip layout.

[0048] In a specific implementation, the temporary image further includes second pixel regions corresponding to the respective pins;

[0049] Step S1053 also includes the following steps:

[0050] For any second pixel region, calculating a first distance between a coordinate point corresponding to the centroid of the second pixel region and the pin position information of the pin closest to the centroid of the second pixel region;

[0051] Calculate a third loss according to all the first distances and a preset third loss function;

[0052] Accordingly, iteratively adjusting the parameters of the pre-trained generative model according to the second loss until the second loss converges to obtain a trained generative model includes:

[0053] The sum of the second loss and the third loss is taken as the target loss, and the parameters of the pre-trained generation model are iteratively adjusted according to the target loss until the target loss converges to obtain the trained generation model.

[0054] The pin position information may be represented by coordinate points. When there are multiple pins, the pin position information includes multiple coordinate points. The first distance may be calculated by Euclidean distance.

[0055] Specifically, the third loss function can be expressed as the sum of all first distances. When the coordinate point corresponding to the centroid of the second pixel area corresponding to any pin is too far from its closest pin position information, the third loss function is large. Otherwise, the third loss function is close to 0. Therefore, in order to ensure the convergence of the third loss, the generation model will adjust its own parameters so that the first distance between the centroid of the second pixel area corresponding to all pins in the output temporary image and their closest pin position information is as small as possible, thereby satisfying the constraints on the pin position in the chip layout.

[0056] In a specific implementation, the basic parameter information also includes virtual module position information;

[0057] Step S1053 also includes the following steps:

[0058] For any virtual module, calculating a second distance between the coordinate point corresponding to the centroid of the first pixel region corresponding to the virtual module and the virtual module position information of the virtual module closest to the centroid of the first pixel region corresponding to the virtual module;

[0059] Calculate a fourth loss according to all the second distances and a preset fourth loss function;

[0060] Accordingly, taking the sum of the second loss and the third loss as the target loss, iteratively adjusting the parameters of the pre-trained generative model according to the target loss until the target loss converges, and obtaining the trained generative model, including:

[0061] The sum of the second loss, the third loss and the fourth loss is taken as the target loss, and the parameters of the pre-trained generation model are iteratively adjusted according to the target loss until the target loss converges to obtain the trained generation model.

[0062] Among them, the second distance can also be calculated by Euclidean distance, the virtual module position information can be represented by coordinate points, the virtual module position information can include multiple coordinate points to indicate that there are multiple positions supporting virtual module placement, and the fourth loss function can be expressed as the sum of all second distances. This embodiment is used to meet the constraints of the virtual module position in the chip layout.

[0063] In a specific implementation, the training process of the discriminant model includes:

[0064] Using a reference generated image as a second training sample, the reference generated image includes first reference areas corresponding to each reference module, second reference areas corresponding to each reference pin, and reference connection lines, wherein the reference connection lines are connection lines between two reference modules or between a reference module and a reference pin;

[0065] If the length of any reference connection line is greater than a preset length threshold, determining that the second label corresponding to the second training sample is not passed; otherwise, determining that the second label corresponding to the second training sample is passed;

[0066] The discriminant model is trained according to the second training sample and the second label to obtain the trained discriminant model.

[0067] Among them, when the reference connecting line is a connecting line between two reference modules, the connecting line between the centroids of the first reference areas corresponding to the two reference modules is used as the reference connecting line; when the reference connecting line is a connecting line between the reference module and the reference pin, the connecting line between the centroid of the first reference area corresponding to the reference module and the centroid of the second reference area corresponding to the reference pin is used as the reference connecting line.

[0068] The preset length threshold can be set by the back-end designer according to actual conditions.

[0069] Specifically, the discriminant model is essentially a classification model. The second label of the second training sample can be determined by threshold comparison of the reference connection line without manual determination. When training the discriminant model, the loss function can use a binary cross entropy loss function.

[0070] In a specific implementation, the first layout image includes a target connection line, where the target connection line is a connection line between two modules or between a module and a pin.

[0071] In this embodiment, the attribute information of each module is extracted from the initial code information of the front-end design to form the topology information, and the physical constraints of the back-end design are used as the basic parameter information. According to the topology information and the basic parameter information, the chip layout image is generated by the generation model and the discrimination model. When the discrimination result fails, the warning information is generated in time to allow the front-end designer to adjust the code. When the discrimination result passes, the first layout image is provided to the back-end designer as a layout reference, thereby improving the convenience of the chip front-end and back-end design collaboration, thereby improving the overall efficiency of the chip design.

[0072] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A chip layout system for front-end and back-end design collaboration, characterized in that: The system comprises: a processor and a memory storing a computer program, and when the computer program is executed by the processor, the following steps are implemented: S101, extracting type information, connection information, first size information and identification information corresponding to each module in the initial code information, wherein the type information includes a main module type, a submodule type and a virtual module type, the connection information includes a connection relationship between the corresponding module and other modules and pins, the identification information is used to indicate the main module to which the corresponding module belongs, and the first size information is used to indicate the physical size of the corresponding module; S102, forming topology information according to type information, connection information, first size information and identification information corresponding to all modules respectively; S103, obtaining basic parameter information of the backend design, where the basic parameter information includes second size information and pin position information corresponding to the chip; S104, initializing the number of iterations to one; S105, generating a first layout image using a pre-trained generation model according to the topology information and the basic parameter information, wherein step S105 includes the following steps: S1051, inputting the topological information and the basic parameter information into the pre-trained generation model to obtain a temporary image, wherein the temporary image includes first pixel regions corresponding to each module; S1052, determining the minimum bounding rectangle of the first pixel area corresponding to all modules in the temporary image, and obtaining a third size of the minimum bounding rectangle; S1053, calculating a second loss according to the third size, the second size and a preset second loss function, iteratively adjusting the parameters of the pre-trained generation model according to the second loss until the second loss converges to obtain a trained generation model, and using the output of the trained generation model as the first layout image; S106, input the first layout image into the trained discriminant model to obtain a discriminant result. If the discriminant result is not passed, increase the number of iterations by one, and return to execute step S105 until the discriminant result is passed or the number of iterations is greater than the preset number threshold, to obtain a layout result. When the discriminant result is passed, the corresponding first layout image is used as the layout result. When the number of iterations is greater than the number threshold, a warning message is used as the layout result.

2. The chip layout system for front-end and back-end design collaboration according to claim 1, characterized in that: Step S102 includes the following steps: S1021, for any module, taking the module as a node, and taking type information, first size information, and identification information corresponding to the module as node information of the node corresponding to the module; S1022, for a pin that is connected to any module, use the pin as a node, and use the pin type corresponding to the pin as node information of the node corresponding to the pin; S1023, forming graph data according to all nodes and their corresponding node information, as well as the connection relationship between each node, and using the graph data as the topology information.

3. The chip layout system for front-end and back-end design collaboration according to claim 1, characterized in that: The pre-training process of the generative model includes: Using the layout sample image as the first label, and using the sample topology information extracted from the code information corresponding to the layout sample image and the sample parameter information corresponding to the layout sample image as the first training sample; Inputting the first training sample into the generation model to obtain a sample generation image; A first loss is calculated based on the sample generated image, the first label and a preset first loss function, and the parameters of the generation model are iteratively adjusted according to the first loss until the first loss converges to obtain the pre-trained generation model.

4. The chip layout system for front-end and back-end design collaboration according to claim 1, characterized in that: The temporary image also includes second pixel areas corresponding to the respective pins; Step S1053 also includes the following steps: For any second pixel region, calculating a first distance between a coordinate point corresponding to the centroid of the second pixel region and the pin position information of the pin closest to the centroid of the second pixel region; Calculate a third loss according to all the first distances and a preset third loss function; Accordingly, iteratively adjusting the parameters of the pre-trained generative model according to the second loss until the second loss converges to obtain a trained generative model includes: The sum of the second loss and the third loss is taken as the target loss, and the parameters of the pre-trained generation model are iteratively adjusted according to the target loss until the target loss converges to obtain the trained generation model.

5. The chip layout system for front-end and back-end design collaboration according to claim 4, characterized in that: The basic parameter information also includes virtual module position information; Step S1053 also includes the following steps: For any virtual module, calculating a second distance between the coordinate point corresponding to the centroid of the first pixel region corresponding to the virtual module and the virtual module position information of the virtual module closest to the centroid of the first pixel region corresponding to the virtual module; Calculate a fourth loss according to all the second distances and a preset fourth loss function; Accordingly, taking the sum of the second loss and the third loss as the target loss, iteratively adjusting the parameters of the pre-trained generative model according to the target loss until the target loss converges, and obtaining the trained generative model, including: The sum of the second loss, the third loss and the fourth loss is taken as the target loss, and the parameters of the pre-trained generation model are iteratively adjusted according to the target loss until the target loss converges to obtain the trained generation model.

6. The chip layout system for front-end and back-end design collaboration according to claim 1, characterized in that: The training process of the discriminant model includes: Using a reference generated image as a second training sample, the reference generated image includes first reference areas corresponding to each reference module, second reference areas corresponding to each reference pin, and reference connection lines, wherein the reference connection lines are connection lines between two reference modules or between a reference module and a reference pin; If the length of any reference connection line is greater than a preset length threshold, determining that the second label corresponding to the second training sample is not passed, otherwise, determining that the second label corresponding to the second training sample is passed; The discriminant model is trained according to the second training sample and the second label to obtain the trained discriminant model.

7. The chip layout system for front-end and back-end design collaboration according to claim 6, characterized in that: The first layout image includes a target connection line, where the target connection line is a connection line between two modules or between a module and a pin.

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