Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a display area and a non-display area, and the non-display area surrounds at least part of the display area; the display area comprises a plurality of pixel circuits, the non-display area comprises a plurality of groups of shift register circuits, and the same pixel circuit is electrically connected with the plurality of groups of shift register circuits; the display panel further comprises a plurality of groups of clock signal lines, and the clock signal lines are electrically connected with the shift register circuit. The number of groups of the clock signal lines is smaller than that of groups of the shift register circuits. The number of groups of clock signal lines in the display panel can be reduced, the number of pins for a driving chip to provide clock signals for different groups of clock signal lines can be reduced, and the power consumption of the display panel is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In a display panel, a pixel circuit is usually electrically connected to multiple groups of shift register circuits, which are used to provide control signals to transistors in the pixel circuit. The shift register circuit is connected to a clock signal line, and the signal output of the shift register circuit is controlled by a clock signal on the clock signal line, which is usually provided by a driver chip.

[0003] In existing display panels, the power consumption of the clock signal provided by the driver chip is usually large, which is not conducive to energy saving and consumption reduction, and easily causes the display panel to overheat. Therefore, a solution is urgently needed. Summary of the invention

[0004] In view of this, embodiments of the present application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a display area and a non-display area, wherein the non-display area surrounds at least a portion of the display area; the display area comprises a plurality of pixel circuits, and the non-display area comprises a plurality of groups of shift register circuits, wherein the same pixel circuit is electrically connected to the plurality of groups of shift register circuits; the display panel further comprises a plurality of groups of clock signal lines, and the clock signal lines are electrically connected to the shift register circuits; the number of groups of clock signal lines is less than the number of groups of shift register circuits.

[0006] In an implementation of the first aspect, the pixel circuit includes a driving transistor, and a gate reset transistor, a threshold capture transistor, a light emitting control transistor, and a bias voltage writing transistor electrically connected to the driving transistor;

[0007] The plurality of shift register circuits include a first shift register circuit and a second shift register circuit. Among the gate reset transistor, the threshold capture transistor, the light emission control transistor, and the bias voltage writing transistor, one is electrically connected to the first shift register circuit, and the other is electrically connected to the second shift register circuit. The first shift register circuit and the second shift register circuit are electrically connected to the same clock signal line.

[0008] In an implementation of the first aspect, a first group of shift register circuits is electrically connected to a gate reset transistor, and a second group of shift register circuits is electrically connected to a threshold grab transistor; the plurality of groups of shift register circuits further include a third group of shift register circuits and a fourth group of shift register circuits, the third group of shift register circuits is electrically connected to a light emitting control transistor, and the fourth group of shift register circuits is electrically connected to a bias voltage writing transistor;

[0009] At least two of the first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits, and the fourth group of shift register circuits are electrically connected to the same group of clock signal lines.

[0010] In an implementation manner of the first aspect, the first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits, and the fourth group of shift register circuits are all electrically connected to the same group of clock signal lines.

[0011] In an implementation of the first aspect, the multiple groups of clock signal lines include a first group of clock signal lines and a second group of clock signal lines, and the first group of clock signal lines and the second group of clock signal lines can be used to transmit different clock signals;

[0012] The first group of shift register circuits and the second group of shift register circuits are both electrically connected to the first group of clock signal lines, and the third group of shift register circuits and the fourth group of shift register circuits are both electrically connected to the second group of clock signal lines.

[0013] In an implementation of the first aspect, the multiple groups of clock signal lines include a first group of clock signal lines and a second group of clock signal lines, and the first group of clock signal lines and the second group of clock signal lines can be used to transmit different clock signals; the first group of shift register circuits, the second group of shift register circuits and the third group of shift register circuits are all electrically connected to the first group of clock signal lines, and the fourth group of shift register circuits is electrically connected to the second group of clock signal lines.

[0014] In an implementation of the first aspect, the shift register circuit includes a plurality of cascaded shift register units; in the first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits, and the fourth group of shift register circuits, the number of rows of pixel circuits electrically connected to a shift register unit is the same.

[0015] In an implementation manner of the first aspect, in the first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits, and the fourth group of shift register circuits, one shift register unit is electrically connected to two rows of pixel circuits.

[0016] In an implementation of the first aspect, the pixel circuit includes a driving transistor, and a gate reset transistor, a threshold capture transistor, a light emitting control transistor, and a bias voltage writing transistor electrically connected to the driving transistor;

[0017] The plurality of shift register circuits include a first shift register circuit, a second shift register circuit and a third shift register circuit, the first shift register circuit is electrically connected to the gate reset transistor and the threshold capture transistor, the second shift register circuit is electrically connected to the light emission control transistor, and the third shift register circuit is electrically connected to the bias voltage writing transistor;

[0018] At least two of the first group of shift register circuits, the second group of shift register circuits, and the third group of shift register circuits are electrically connected to the same group of clock signal lines.

[0019] In an implementation of the first aspect, both the gate reset transistor and the threshold grab transistor include metal oxide.

[0020] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0021] In an embodiment of the present application, the number of groups of clock signal lines is set to be smaller than the number of groups of shift register circuits, that is, different groups of shift register circuits are set to share the same group of clock signal lines. This can reduce the number of groups of clock signal lines in the display panel, which is beneficial to reducing the number of pins of the driving chip that provide clock signals to different groups of clock signal lines, thereby reducing the power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0024] Figure 2 for Figure 1 A schematic diagram of connecting multiple groups of shift register circuits and clock signal lines;

[0025] Figure 3 for Figure 1 Another connection diagram of multiple groups of shift register circuits and clock signal lines;

[0026] Figure 4 A connection diagram of a pixel circuit provided in an embodiment of the present application;

[0027] Figure 5 for Figure 1 Another connection diagram of the shift register circuit and the clock signal line;

[0028] Figure 6 for Figure 1 Another connection diagram of the shift register circuit and the clock signal line;

[0029] Figure 7 for Figure 1 Another connection diagram of the shift register circuit and the clock signal line;

[0030] Figure 8 A schematic diagram of a first group of shift register circuits provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of a second group of shift register circuits provided in an embodiment of the present application;

[0032] Fig.10 A schematic diagram of a third group of shift register circuits provided in an embodiment of the present application;

[0033] Fig.11 A schematic diagram of a fourth group of shift register circuits provided in an embodiment of the present application;

[0034] Fig.12 for Figure 8 A timing diagram of the first group of shift register circuits shown;

[0035] Fig.13 for Fig. 9 A timing diagram of the second group of shift register circuits shown;

[0036] Fig.14 for Fig.10 A timing diagram of the third group of shift register circuits shown;

[0037] Fig.15 for Fig.11 A timing diagram of the fourth group of shift register circuits shown;

[0038] Fig.16 A schematic plan view of another display panel provided in an embodiment of the present application;

[0039] Fig.17 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0040] Fig.18 for Fig.16 A connection diagram of a shift register circuit and a clock signal line;

[0041] Fig.19 for Fig.16 Another connection diagram of the shift register circuit and the clock signal line;

[0042] Fig. 20 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0044] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0045] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0046] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0047] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0048] The present application embodiment provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes a display area AA and a non-display area NA, and the non-display area NA surrounds at least a portion of the display area AA. Figure 1 As shown, the non-display area NA surrounds the entire display area AA.

[0049] The display area AA includes a plurality of pixel circuits 11 and a plurality of light emitting devices 12. The pixel circuits 11 are used to drive the light emitting devices 12 to emit light. The non-display area NA includes a plurality of shift register circuits 21. The same shift register circuit 21 includes a plurality of cascaded shift register units 210. The plurality of cascaded shift register units 210 can sequentially output enable signals to the scan lines 13 in the display area AA. The scan lines 13 and the transistors ( Figure 1 The scanning line 13 is electrically connected to the transistor (not shown), and the signal transmitted by the scanning line 13 can control the switching state of the transistor connected thereto. Here, the enable signal means that after the scanning line 13 receives the enable signal, the transistor connected thereto is turned on.

[0050] like Figure 1 As shown, the same pixel circuit 11 is electrically connected to multiple groups of shift register circuits 11. That is, one pixel circuit 11 can receive signals output by multiple groups of shift register circuits 11, and transistors with different functions in the pixel circuit 11 can be controlled by signals output by different groups of shift register circuits 11.

[0051] For example, Figure 1 As shown, the multiple groups of shift register circuits 21 include a first group of shift register circuits 211, a second group of shift register circuits 212, a third group of shift register circuits 213, a fourth group of shift register circuits 214 and a fifth group of shift register circuits 215. A pixel circuit 11 can be electrically connected to the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213, the fourth group of shift register circuits 214 and the fifth group of shift register circuits 215. The signals output by the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213, the fourth group of shift register circuits 214 and the fifth group of shift register circuits 215 respectively control the switching states of the non-functional transistors in the pixel circuit 11.

[0052] Combination Figure 2 As shown, Figure 2 for Figure 1 A connection diagram of multiple groups of shift register circuits and clock signal lines is shown in FIG. 1 , where the display panel 01 further includes multiple groups of clock signal lines 31, which are electrically connected to the shift register circuits 21. Of course, one group of shift register circuits 21 is connected to one group of clock signal lines 31, and the clock signal transmitted on the clock signal lines 31 can control the signal output of the shift register circuits 21. The clock signal can be provided by a driver chip.

[0053] For example, Figure 2 As shown, a group of clock signal lines 31 may include a first clock line 31A and a second clock line 31B. Different groups of clock signal lines 31 may transmit different clock signals.

[0054] The number of groups of clock signal lines 31 is smaller than the number of groups of shift register circuits 21 . That is, in the display panel 01 , some different groups of shift register circuits 21 can share the same group of clock signal lines 31 .

[0055] For example, Figure 2 As shown, the multiple groups of clock signal lines 31 include a first group of clock signal lines 311, a second group of clock signal lines 312, a third group of clock signal lines 313 and a fourth group of clock signal lines 314, the first group of shift register circuits 211 and the second group of shift register circuits 212 are both electrically connected to the first group of clock signal lines 311, the third group of shift register circuits 213 are electrically connected to the second group of clock signal lines 312, the fourth group of shift register circuits 214 are electrically connected to the third group of clock signal lines 313, and the fifth group of shift register circuits 215 are electrically connected to the fourth group of clock signal lines 314.

[0056] It should be noted that, in the embodiment of the present application, the same group of clock signal lines 31 refers to clock signal lines electrically connected to the same driver chip pins. For the convenience of routing, in the same group of clock signal lines 31, the first clock line 31A may include a plurality of first routing lines electrically connected to each other, and the second clock line 31B may include a plurality of second routing lines electrically connected to each other. The first routing line and the second routing line may refer to routing lines extending along the cascade direction of the shift register unit 210.

[0057] For example, Figure 2 As shown, in the first group of clock signal lines 311, the first clock line 31A includes a first routing line CK1, the second clock line 31B includes a second routing line CK2, and the first group of shift register circuits 211 and the second group of shift register circuits 212 are both electrically connected to the first routing line CK1 and the second routing line CK2.

[0058] For example, Figure 3 As shown, Figure 3 for Figure 1 Another connection diagram of multiple groups of shift register circuits and clock signal lines, the first clock line 31A includes two first routing lines CK1, the second clock line 31B includes two second routing lines CK2, the first group of shift register circuits 211 and the second group of shift register circuits 212 are respectively electrically connected to different first routing lines CK1 in the first clock line 31A, and the first group of shift register circuits 211 and the second group of shift register circuits 212 are respectively electrically connected to different second routing lines CK2 in the second clock line 31B.

[0059] The inventor of the present application has found through research that in the prior art, the number of groups of clock signal lines required to be provided is the same as the number of groups of shift register circuits provided in the display panel. For example, if 5 groups of shift register circuits are provided in the display panel, 5 groups of clock signal lines are required. The clock signal jump frequency on the clock signal line is usually high, and a large number of groups of clock signal lines will increase the number of pins of the driver chip that transmit clock signals to different groups of clock signal lines, which is likely to increase the power consumption of the display panel, which is not conducive to energy saving and consumption reduction, and is likely to cause the display panel to overheat.

[0060] In view of this, in the embodiment of the present application, the number of groups of clock signal lines 31 is set to be smaller than the number of groups of shift register circuits 21, that is, different groups of shift register circuits 21 are set to share the same group of clock signal lines 31, which can reduce the number of groups of clock signal lines 31 in the display panel 01, which is beneficial to reducing the number of pins of the driving chip that provide clock signals to different groups of clock signal lines 31, thereby reducing the power consumption of the display panel 01.

[0061] Figure 4 A connection diagram of a pixel circuit provided in an embodiment of the present application.

[0062] In one embodiment of the present application, Figure 4 As shown, the pixel circuit 11 includes a driving transistor Td, and a gate reset transistor T1 electrically connected to the driving transistor Td, a threshold capture transistor T2, a light emitting control transistor T3, a power supply voltage writing transistor T4, a bias voltage writing transistor T5 and a data voltage writing transistor T6.

[0063] Among them, the driving transistor Td is used to generate a light-emitting driving current, the first electrode of the gate reset transistor T1 is electrically connected to the first reset signal line SL1, the second electrode is electrically connected to the gate of the driving transistor Td, and the gate is electrically connected to the first scan line S1N, and the first reset signal line SL1 transmits a first reset voltage VREF1. The first electrode of the threshold capture transistor T2 is electrically connected to the second electrode of the driving transistor Td, the second electrode is electrically connected to the gate of the driving transistor Td, and the gate is electrically connected to the second scan line S2N. The first electrode of the light-emitting control transistor T3 is electrically connected to the second electrode of the driving transistor Td, the second electrode is electrically connected to the first electrode of the light-emitting device 12, and the gate is electrically connected to the third scan line EM. The first electrode of the power supply voltage writing transistor T4 is electrically connected to the first power supply signal line DL1, the second electrode is electrically connected to the first electrode of the driving transistor Td, and the gate is electrically connected to the third scan line EM, and the first power supply signal line DL1 transmits the first power supply voltage PVDD. The first electrode of the bias voltage writing transistor T5 is electrically connected to the bias voltage signal line DL2, the second electrode is electrically connected to the first electrode of the driving transistor Td, and the gate is electrically connected to the fourth scanning line SP*. The bias voltage signal line DL2 transmits the bias voltage VDH. The first electrode of the data power writing transistor T6 is electrically connected to the data signal line DL3, the second electrode is electrically connected to the first electrode of the driving transistor Td, and the gate is electrically connected to the fifth scanning line SP. The data signal line DL3 transmits the data voltage Data.

[0064] In addition, the pixel circuit 11 further includes a light emitting reset transistor T7, a first electrode of the light emitting reset transistor T7 is electrically connected to the second reset signal line SL2, a second electrode is electrically connected to the first electrode of the light emitting device 12, and a gate is electrically connected to the fifth scanning line SP, and the second reset signal line SL2 transmits a second reset voltage VREF2. The pixel circuit 11 further includes a storage capacitor Cst, one plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor Td, and the other plate is electrically connected to the first power signal line DL1.

[0065] Exemplarily, the gate reset transistor T1 and the threshold grab transistor T2 both include metal oxide, the gate reset transistor T1 and the threshold grab transistor T2 are N-type transistors, the driving transistor Td, the light emitting control transistor T3, the power supply voltage writing transistor T4, the bias voltage writing transistor T5, the data voltage writing transistor T6 and the light emitting reset transistor T7 are P-type transistors.

[0066] The first scan line S1N, the second scan line S2N, the third scan line EM, the fourth scan line SP*, and the fifth scan line SP are electrically connected to different groups of shift register circuits 21, respectively.

[0067] The working process of the pixel circuit 11 may be the same as that in the prior art, and will not be described in detail herein.

[0068] The multiple groups of shift register circuits 21 include a first group of shift register circuits 211 and a second group of shift register circuits 212. Among the gate reset transistor T1, the threshold capture transistor T2, the light emitting control transistor T3, and the bias voltage writing transistor T5, one is electrically connected to the first group of shift register circuits 211, and the other is electrically connected to the second group of shift register circuits 212.

[0069] That is, one of the first scan line S1N, the second scan line S2N, the third scan line EM, and the fourth scan line SP* is electrically connected to the first group of shift register circuits 211 , and another one of them is electrically connected to the second group of shift register circuits 212 .

[0070] For example, Figure 4 As shown, the gate reset transistor T1 is electrically connected to the first group of shift register circuits 211 through the first scan line S1N, and the threshold capture transistor T2 is electrically connected to the second group of shift register circuits 212 through the second scan line S2N.

[0071] The first group of shift register circuits 211 and the second group of shift register circuits 212 share the same group of clock signal lines 31. Figure 2 and Figure 3 As shown, the first group of shift register circuits 211 and the second group of shift register circuits 212 are both electrically connected to the first group of clock signal lines 311 .

[0072] The inventors of the present application have found through research that in different groups of shift register circuits 21 to which the gate reset transistor T1, the threshold capture transistor T2, the light emission control transistor T3, and the bias voltage writing transistor T5 are respectively connected, the number of rows of pixel circuits 11 driven by a shift register unit 210 in each group of shift register circuits 21 is usually the same. These groups of shift register circuits 21 can receive the same clock signal and output different signals through different trigger signals.

[0073] Therefore, the embodiment of the present application sets a first group of shift register circuits 211 electrically connected to one of the gate reset transistor T1, the threshold capture transistor T2, the light emission control transistor T3, and the bias voltage writing transistor T5, and a second group of shift register circuits 212 electrically connected to another one of the gate reset transistor T1, the threshold capture transistor T2, the light emission control transistor T3, and the bias voltage writing transistor T5 share the same group of clock signal lines 31. While ensuring that the gate reset transistor T1, the threshold capture transistor T2, the light emission control transistor T3, and the bias voltage writing transistor T5 can all work normally, the number of groups of clock signal lines 31 in the display panel 01 can be reduced, which is beneficial to reducing the power consumption of the display panel 01.

[0074] In one embodiment of the present application, please continue to refer to Figure 4 The first group of shift register circuits 211 is electrically connected to the gate reset transistor T1, and the second group of shift register circuits 212 is electrically connected to the threshold grab transistor T2.

[0075] The plurality of shift register circuits 21 further include a third shift register circuit 213 and a fourth shift register circuit 214. The third shift register circuit 213 is electrically connected to the light emitting control transistor T3, and the fourth shift register circuit 214 is electrically connected to the bias voltage writing transistor T5.

[0076] In addition, the plurality of shift register circuits 21 may further include a fifth shift register circuit 215 , and the fifth shift register circuit 215 is electrically connected to the data voltage writing transistor T6 through the fifth scanning line SP.

[0077] Among the first group of shift register circuits 211 , the second group of shift register circuits 212 , the third group of shift register circuits 213 and the fourth group of shift register circuits 214 , at least two are electrically connected to the same group of clock signal lines 31 .

[0078] That is, any two of the first group of shift register circuits 211 , the second group of shift register circuits 212 , the third group of shift register circuits 213 , and the fourth group of shift register circuits 214 may be arranged to share the same group of clock signal lines 31 .

[0079] For example, Figure 2 and Figure 3As shown, the display panel 01 includes four groups of clock signal lines 31, and the four groups of clock signal lines 31 include a first group of clock signal lines 311, a second group of clock signal lines 312, a third group of clock signal lines 313, and a fourth group of clock signal lines 314. Among them, the first group of shift register circuits 211 and the second group of shift register circuits 212 are both electrically connected to the first group of clock signal lines 311, the third group of shift register circuits 213 are electrically connected to the second group of clock signal lines 312, the fourth group of shift register circuits 214 are electrically connected to the third group of clock signal lines 313, and the fifth group of shift register circuits 215 are electrically connected to the fourth group of clock signal lines 314.

[0080] For example, Figure 5 As shown, Figure 5 for Figure 1 Another connection diagram of the shift register circuit and the clock signal line in the display panel 01 includes three groups of clock signal lines 31, and the three groups of clock signal lines 31 include a first group of clock signal lines 311, a second group of clock signal lines 312 and a third group of clock signal lines 313. Among them, the first group of shift register circuits 211 and the second group of shift register circuits 212 are both electrically connected to the first group of clock signal lines 311, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 are both electrically connected to the second group of clock signal lines 312, and the fifth group of shift register circuits 214 are electrically connected to the third group of clock signal lines 313.

[0081] Any three of the first group of shift register circuits 211 , the second group of shift register circuits 212 , the third group of shift register circuits 213 and the fourth group of shift register circuits 214 may also be arranged to share the same group of clock signal lines 31 .

[0082] For example, Figure 6 As shown, Figure 6 for Figure 1 Another connection diagram of the shift register circuit and the clock signal line in the display panel 01 includes three groups of clock signal lines 31, and the three groups of clock signal lines 31 include a first group of clock signal lines 311, a second group of clock signal lines 312, and a third group of clock signal lines 313. Among them, the first group of shift register circuits 211, the second group of shift register circuits 212, and the third group of shift register circuits 213 are all electrically connected to the first group of clock signal lines 311, the fourth group of shift register circuits 214 are electrically connected to the second group of clock signal lines 312, and the fifth group of shift register circuits 215 are electrically connected to the third group of clock signal lines 313.

[0083] It is also possible to set the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 to share the same group of clock signal lines 31. That is, the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 are all electrically connected to the same group of clock signal lines 31.

[0084] For example, Figure 7 As shown, Figure 7 for Figure 1 Another connection diagram of the shift register circuit and the clock signal line, the display panel 01 includes two groups of clock signal lines 31, the two groups of clock signal lines 31 include a first group of clock signal lines 311 and a second group of clock signal lines 312, the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 are all electrically connected to the first group of clock signal lines 311, and the fifth group of shift register circuits 215 is electrically connected to the second group of clock signal lines 312.

[0085] Optional, such as Figure 1 As shown, the shift register circuit 21 includes a plurality of cascaded shift register units 210. In the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214, the number of rows of pixel circuits 11 electrically connected to one shift register unit 210 is the same.

[0086] For example, Figure 1 As shown, in the first group of shift register circuits 211 , the second group of shift register circuits 212 , the third group of shift register circuits 213 and the fourth group of shift register circuits 214 , one shift register unit 210 is electrically connected to two rows of pixel circuits 11 .

[0087] Based on this setting method, it is beneficial to enable the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 to share the same group of clock signal lines 31. By flexibly setting the trigger signal, the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 can output the signal required by the pixel circuit 11.

[0088] To facilitate understanding of the technical solution of the present application, the signal output conditions of each group of shift register circuits 21 are described below by taking the example that the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 share the first group of clock signal lines 311.

[0089] Figure 8 A schematic diagram of a first group of shift register circuits provided in an embodiment of the present application, Fig. 9 A schematic diagram of a second group of shift register circuits provided in an embodiment of the present application, Fig.10 A schematic diagram of a third group of shift register circuits provided in an embodiment of the present application, Fig.11 A schematic diagram of a fourth group of shift register circuits provided in an embodiment of the present application. Fig.12 for Figure 8 A timing diagram of the first group of shift register circuits shown, Fig.13 for Fig. 9 A timing diagram of the second group of shift register circuits shown, Fig.14 for Fig.10 A timing diagram of the third group of shift register circuits shown, Fig.15 for Fig.11 A timing diagram of the fourth group of shift register circuits shown.

[0090] like Figure 8 As shown, the first group of shift register circuits 211 includes transistors M1-M13 and capacitors C1-C3. The connection method of the transistors M1-M13 and the capacitors C1-C3 is as follows: Figure 8 As shown, no further details are given here. In the first group of shift register circuits 211, the first electrode of transistor M6, the first electrode of transistor M8, the first electrode of transistor M9 and the first electrode of transistor M13 receive the first fixed potential VGH, the first electrode of transistor M5, the first electrode of transistor 10, the gate of transistor M11 and the gate of transistor M12 receive the second fixed potential VGL, and the second electrode of transistor M9 and the second electrode of transistor M10 are electrically connected to the output terminal OUT1 of the first group of shift register circuits 211. The first electrode of transistor M4 is electrically connected to the trigger signal I N1, the first electrode of transistor M2, the gate of transistor M4 and the gate of transistor M5 are electrically connected to the first clock line 31A in the first group of clock signal lines 31, and the first electrode of transistor M1, the first electrode of transistor M3 and the gate of transistor M7 are electrically connected to the second clock line 31B in the first group of clock signal lines 31. The gate of transistor M13 is electrically connected to the first control line Cr. In one working cycle of the first group of shift register circuits 211, the signal transmitted by the first control line Cr can control transistor 13 to remain in the off state.

[0091] Combination Fig.12 As shown, in one working cycle of the first group of shift register circuits 211, under the combined action of the trigger signal I N1, the signals on the first clock line 31A and the second clock line 31B, the output terminal OUT1 of the first group of shift register circuits 211 outputs the signal required by the pixel circuit 11. The working process of the first group of shift register circuits 211 can be the same as that of the prior art, and will not be described in detail herein.

[0092] like Fig. 9 As shown, the second group of shift register circuits 212 includes transistors M1-M16 and capacitors C1-C3. The connection method of transistors M1-M16 and capacitors C1-C3 is as follows: Figure 8 As shown, no further details are given here. In the second group of shift register circuits 212, the first electrodes of transistors M6, transistors M8, transistors M9 and transistors M13 receive the first fixed potential VGH, the first electrode of transistor M5, the first electrode of transistor M10, the gate of transistor M11, the gate of transistor M12 and the gate of transistor M15 receive the second fixed potential VGL, and the second electrode of transistor M9 and the second electrode of transistor M10 are electrically connected to the output terminal OUT2 of the first group of shift register circuits 211. The first electrode of transistor M4 and the first electrode of transistor M14 are electrically connected to the trigger signal I N2, the first electrode of transistor M2, the gate of transistor M4, the gate of transistor M5 and the gate of transistor M14 are electrically connected to the first clock line 31A in the first group of clock signal lines 31, and the first electrode of transistor M1, the first electrode of transistor M3 and the gate of transistor M7 are electrically connected to the second clock line 31B in the first group of clock signal lines 31. The gate of the transistor M13 is electrically connected to the second control line RST. In one working cycle of the second group of shift register circuits 212, the signal transmitted by the second control line RST can control the transistor M13 to remain in the off state.

[0093] Combination Fig.13 As shown, in one working cycle of the second shift register circuit 212, under the combined action of the trigger signal IN2, the signals on the first clock line 31A and the second clock line 31B, the output terminal OUT2 of the second shift register circuit 212 outputs the signal required by the pixel circuit 11. The working process of the second shift register circuit 212 can be the same as that of the prior art, which will not be described in detail herein.

[0094] like Fig.10 As shown, the third group of shift register circuits 213 may have the same circuit structure as the first group of shift register circuits 211, which will not be described in detail. The third group of shift register circuits 213 receives the trigger signal IN3, and the output terminal of the third group of shift register circuits 213 is OUT3.

[0095] Combination Fig.14 As shown, in one working cycle of the third shift register circuit 213, under the combined action of the trigger signal IN3, the signals on the first clock line 31A and the second clock line 31B, the output terminal OUT3 of the third shift register circuit 213 outputs the signal required by the pixel circuit 11. The working process of the third shift register circuit 213 can be the same as that of the prior art, and will not be described in detail herein.

[0096] like Fig.11 As shown, the fourth group of shift register circuits 214 includes transistors M1-M8 and capacitors C1-C2. The connection method of the transistors M1-M8 and the capacitors C1-C2 is as follows: Fig.11 In the fourth shift register circuit 214, the first electrodes of the transistors M5 and M7 receive the first fixed potential VGH, the first electrode of the transistor M2 and the gate of the transistor M3 receive the second fixed potential VGL, and the second electrode of the transistor M7 and the second electrode of the transistor M8 are electrically connected to the output terminal OUT4 of the fourth shift register circuit 214. The gate of the transistor M1, the gate of the transistor M2 and the first electrode of the transistor M6 are electrically connected to the first clock line 31A in the first group of clock signal lines 31, and the gate of the transistor M4 and the first electrode of the transistor M8 are electrically connected to the second clock line 31B in the first group of clock signal lines 31.

[0097] Combination Fig.15 As shown, in one working cycle of the fourth shift register circuit 214, under the combined action of the trigger signal IN4, the signals on the first clock line 31A and the second clock line 31B, the output terminal OUT4 of the fourth shift register circuit 214 outputs the signal required by the pixel circuit 11. The working process of the fourth shift register circuit 214 can be the same as that of the prior art, and will not be described in detail herein.

[0098] Combination Figure 12-Figure 15 As shown, when the first group of shift register circuits 211, the second group of shift register circuits 212, the third group of shift register circuits 213 and the fourth group of shift register circuits 214 share the same group of clock signal lines 31, each group of shift register circuits 21 can output the signal required by the pixel circuit 11 by controlling the trigger signals IN1-I N4.

[0099] It should be noted that Figure 12-Figure 15 The signals output by the shift register circuit 21 shown in the figure are only for illustration. In the display panel 01 , the trigger signals IN1 - IN4 can be flexibly set according to actual needs, thereby flexibly adjusting the signals output by each group of shift register circuits 21 .

[0100] In one embodiment of the present application, Figure 5 As shown, the multiple groups of clock signal lines 31 include a first group of clock signal lines 311 and a second group of clock signal lines 312. The first group of clock signal lines 311 and the second group of clock signal lines 312 can be used to transmit different clock signals.

[0101] The first group of shift register circuits 211 and the second group of shift register circuits 212 are both electrically connected to the first group of clock signal lines 311 , and the third group of shift register circuits 213 and the fourth group of shift register circuits 214 are both electrically connected to the second group of clock signal lines 312 .

[0102] In addition, the plurality of groups of clock signal lines 31 further include a third group of clock signal lines 313 , and the fifth group of shift register circuits 215 are electrically connected to the third group of clock signal lines 313 .

[0103] Since the first shift register circuit 211 is electrically connected to the gate reset transistor T1 and the second shift register circuit 212 is electrically connected to the threshold capture transistor T2, during the operation of the pixel circuit 11, the turn-on frequencies of the gate reset transistor T1 and the threshold capture transistor T2 can be reduced together.

[0104] Therefore, in the embodiment of the present application, the first group of shift register circuits 211 and the second group of shift register circuits 212 share the first group of clock signal lines 311. This can reduce the number of clock signal line groups in the display panel 01 while also reducing the frequency of the clock signal on the first group of clock signal lines 311, thereby further reducing power consumption.

[0105] At the same time, by arranging the third group of shift register circuits 213 and the fourth group of shift register circuits 214 to share the second group of clock signal lines 312, the number of groups of clock signal lines 31 in the display panel 01 can be reduced to a large extent, thereby facilitating a large degree of reduction in power consumption.

[0106] like Figure 6 As shown, in one embodiment of the present application, the plurality of groups of clock signal lines 31 include a first group of clock signal lines 311 and a second group of clock signal lines 312 , and the first group of clock signal lines 311 and the second group of clock signal lines 312 can be used to transmit different clock signals.

[0107] The first group of shift register circuits 211 , the second group of shift register circuits 212 and the third group of shift register circuits 213 are all electrically connected to the first group of clock signal lines 311 , and the fourth group of shift register circuits 214 is electrically connected to the second group of clock signal lines 312 .

[0108] In addition, the plurality of groups of clock signal lines 31 further include a third group of clock signal lines 313 , and the fifth group of shift register circuits 215 are electrically connected to the third group of clock signal lines 313 .

[0109] Since the bias voltage writing transistor T5 can write the bias voltage VDH on the bias voltage signal line DL2 into the driving transistor Td to adjust the bias state of the driving transistor Td, it is used to improve the flicker problem of the display panel 01. Therefore, the fourth group of shift register circuits 214 electrically connected to the bias voltage writing transistor T5 is set to be connected to the second group of clock signal lines 312 separately, and the timing of the output signal of the fourth group of shift register circuits 214 can be controlled by flexibly adjusting the clock signal on the second group of clock signal lines 312, so as to flexibly adjust the start timing of the bias voltage writing transistor T5, thereby optimizing the flicker problem of the display panel 01.

[0110] At the same time, the first group of shift register circuits 211, the second group of shift register circuits 212 and the third group of shift register circuits 213 are set to share the first group of clock signal lines 311, so that the number of groups of clock signal lines 31 in the display panel 01 can be greatly reduced, which is beneficial to greatly reduce power consumption.

[0111] Fig.16 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig.17 A schematic diagram of another pixel circuit provided in an embodiment of the present application.

[0112] In one embodiment of the present application, Fig.16 and Fig.17 As shown, the pixel circuit 11 includes a driving transistor Td, and a gate reset transistor T1 electrically connected to the driving transistor Td, a threshold capture transistor T2, a light emitting control transistor T3, a power supply voltage writing transistor T4, a bias voltage writing transistor T5 and a data voltage writing transistor T6.

[0113] Among them, the driving transistor Td is used to generate a light-emitting driving current, the first electrode of the gate reset transistor T1 is electrically connected to the first reset signal line SL1, the second electrode is electrically connected to the gate of the driving transistor Td, and the gate is electrically connected to the first scan line SN, and the first reset signal line SL1 transmits a first reset voltage VREF1. The first electrode of the threshold capture transistor T2 is electrically connected to the second electrode of the driving transistor Td, the second electrode is electrically connected to the gate of the driving transistor Td, and the gate is electrically connected to the first scan line SN. The first electrode of the light-emitting control transistor T3 is electrically connected to the second electrode of the driving transistor Td, the second electrode is electrically connected to the first electrode of the light-emitting device 12, and the gate is electrically connected to the second scan line EM. The first electrode of the power supply voltage writing transistor T4 is electrically connected to the first power supply signal line DL1, the second electrode is electrically connected to the first electrode of the driving transistor Td, and the gate is electrically connected to the second scan line EM, and the first power supply signal line DL1 transmits the first power supply voltage PVDD. The first electrode of the bias voltage writing transistor T5 is electrically connected to the bias voltage signal line DL2, the second electrode is electrically connected to the first electrode of the driving transistor Td, and the gate is electrically connected to the third scan line SP*. The data power writing transistor T6 has a first electrode electrically connected to the data signal line DL3 , a second electrode electrically connected to the first electrode of the driving transistor Td, and a gate electrically connected to the fourth scanning line SP.

[0114] In addition, the pixel circuit 11 also includes a light-emitting reset transistor T7, the first electrode of the light-emitting reset transistor T7 is electrically connected to the second reset signal line SL2, the second electrode is electrically connected to the first electrode of the light-emitting device 12, and the gate is electrically connected to the fourth scan line SP. The second reset signal line SL2 transmits the second reset voltage VREF2.

[0115] Exemplarily, the gate reset transistor T1 and the threshold grab transistor T2 both include metal oxide, the gate reset transistor T1 and the threshold grab transistor T2 are N-type transistors, the driving transistor Td, the light emitting control transistor T3, the power supply voltage writing transistor T4, the bias voltage writing transistor T5, the data voltage writing transistor T6 and the light emitting reset transistor T7 are P-type transistors.

[0116] The first scan line SN, the second scan line EM, the third scan line SP* and the fourth scan line SP are respectively electrically connected to different groups of shift register circuits 21. The operation process of the pixel circuit 11 can be the same as that of the prior art, which will not be described in detail here.

[0117] The multiple groups of shift register circuits 21 include a first group of shift register circuits 211, a second group of shift register circuits 212, a third group of shift register circuits 213 and a fourth group of shift register circuits 214. The first group of shift register circuits 211 are electrically connected to the gate reset transistor T1 and the threshold capture transistor T2 through the first scan line SN, the second group of shift register circuits 212 are electrically connected to the light emitting control transistor T3 and the power supply voltage writing transistor T4 through the second scan line EM, the third group of shift register circuits 213 are electrically connected to the bias voltage writing transistor T5 through the third scan line SP*, and the fourth group of shift register circuits 214 are electrically connected to the data voltage writing transistor T6 through the fourth scan line SP.

[0118] At least two of the first group of shift register circuits 211 , the second group of shift register circuits 212 , and the third group of shift register circuits 213 are electrically connected to the same group of clock signal lines 31 .

[0119] That is to say, in the embodiment of the present application, any two of the first group of shift register circuits 211 , the second group of shift register circuits 212 , and the third group of shift register circuits 213 may be configured to share the same group of clock signal lines 31 .

[0120] For example, Fig.18 As shown, Fig.18 for Fig.16 A schematic diagram of a connection between a shift register circuit and a clock signal line in the display panel 01 includes three groups of clock signal lines 31, and the three groups of clock signal lines 31 include a first group of clock signal lines 311, a second group of clock signal lines 312, and a third group of clock signal lines 313. Among them, the first group of shift register circuits 211 and the second group of shift register circuits 212 are both electrically connected to the first group of clock signal lines 311, the third group of shift register circuits 213 is electrically connected to the second group of clock signal lines 312, and the fourth group of shift register circuits 214 is electrically connected to the third group of clock signal lines.

[0121] The first group of shift register circuits 211 , the second group of shift register circuits 212 , and the third group of shift register circuits 213 may also be arranged to share the same group of clock signal lines 31 .

[0122] For example, Fig.19 As shown, Fig.19 for Fig.16 Another connection diagram of the shift register circuit and the clock signal line, the display panel 01 includes two groups of clock signal lines 31, the two groups of clock signal lines 31 include a first group of clock signal lines 311 and a second group of clock signal lines 312, the first group of shift register circuits 211, the second group of shift register circuits 212, and the third group of shift register circuits 213 are all electrically connected to the first group of clock signal lines 311, and the fourth group of shift register circuits 214 is electrically connected to the second group of clock signal lines 312.

[0123] From the above analysis, it can be known that the shift register circuit 21 connected to the gate reset transistor T1, the threshold capture transistor T2, the light emission control transistor T3, and the bias voltage writing transistor T5 can receive the same clock signal.

[0124] Therefore, in the embodiment of the present application, at least two of the first group of shift register circuits 211, the second group of shift register circuits 212 and the third group of shift register circuits 213 share the same group of clock signal lines 31, which can reduce the number of groups of clock signal lines 31 in the display panel 01 while ensuring the normal operation of the pixel circuit 11, thereby reducing power consumption.

[0125] It should be noted that, in the embodiment of the present application, when the gate reset transistor T1 and the threshold grabbing transistor T2 are connected to the same group of shift register circuits 21, that is, when the gate reset transistor T1 and the threshold grabbing transistor T2 are both connected to the first group of shift register circuits 211, the circuit structure of the first group of shift register circuits 211 at this time can be the same as the structure of the second group of shift register circuits 212 electrically connected to the threshold grabbing transistor T2 in the previous embodiment, that is, it can be Fig. 9 Of course, the timing of the first group of shift register circuits 211 in the embodiment of the present application can also be as follows: Fig.13 shown.

[0126] Fig. 20 A schematic diagram of a display device provided in an embodiment of the present application.

[0127] like Fig. 20 As shown, the embodiment of the present application provides a display device 02, including the display panel 01 provided in the above embodiment. For example, the display device provided in the embodiment of the present application can be an electronic device such as a mobile phone, a computer, a television, a car display, etc., and the present application does not make any specific limitation.

[0128] In the display device 02, the number of groups of clock signal lines 31 is set to be smaller than the number of groups of shift register circuits 21, that is, different groups of shift register circuits 21 are set to share the same group of clock signal lines 31. This can reduce the number of groups of clock signal lines 31 in the display panel 01, which is beneficial to reducing the number of pins of the driving chip that provide clock signals to different groups of clock signal lines 31, thereby reducing the power consumption of the display device 02.

[0129] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The device comprises a display area and a non-display area, wherein the non-display area surrounds at least a portion of the display area; the display area comprises a plurality of pixel circuits, the non-display area comprises a plurality of shift register circuits, and the same pixel circuit is electrically connected to the plurality of shift register circuits; The display panel further includes a plurality of groups of clock signal lines, and the clock signal lines are electrically connected to the shift register circuits; the number of groups of the clock signal lines is smaller than the number of groups of the shift register circuits.

2. The display panel according to claim 1, characterized in that: The pixel circuit includes a driving transistor, and a gate reset transistor, a threshold capture transistor, a light emission control transistor, and a bias voltage writing transistor electrically connected to the driving transistor; The plurality of shift register circuits include a first shift register circuit and a second shift register circuit, and among the gate reset transistor, the threshold capture transistor, the light emission control transistor and the bias voltage writing transistor, one is electrically connected to the first shift register circuit, and the other is electrically connected to the second shift register circuit; The first group of shift register circuits and the second group of shift register circuits are electrically connected to the same group of clock signal lines.

3. The display panel according to claim 2, characterized in that: The first group of shift register circuits is electrically connected to the gate reset transistor, and the second group of shift register circuits is electrically connected to the threshold grab transistor; The plurality of groups of shift register circuits further include a third group of shift register circuits and a fourth group of shift register circuits, the third group of shift register circuits being electrically connected to the light emitting control transistor, and the fourth group of shift register circuits being electrically connected to the bias voltage writing transistor; At least two of the first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits, and the fourth group of shift register circuits are electrically connected to the same group of the clock signal lines.

4. The display panel according to claim 3, characterized in that: The first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits and the fourth group of shift register circuits are all electrically connected to the same group of clock signal lines.

5. The display panel according to claim 3, characterized in that: The plurality of groups of clock signal lines include a first group of clock signal lines and a second group of clock signal lines, and the first group of clock signal lines and the second group of clock signal lines can be used to transmit different clock signals; The first group of shift register circuits and the second group of shift register circuits are both electrically connected to the first group of clock signal lines, and the third group of shift register circuits and the fourth group of shift register circuits are both electrically connected to the second group of clock signal lines.

6. The display panel according to claim 3, characterized in that: The plurality of groups of clock signal lines include a first group of clock signal lines and a second group of clock signal lines, and the first group of clock signal lines and the second group of clock signal lines can be used to transmit different clock signals; The first group of shift register circuits, the second group of shift register circuits and the third group of shift register circuits are all electrically connected to the first group of clock signal lines, and the fourth group of shift register circuits is electrically connected to the second group of clock signal lines.

7. The display panel according to claim 3, characterized in that: The shift register circuit includes a plurality of cascaded shift register units; in the first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits and the fourth group of shift register circuits, the number of rows of the pixel circuits electrically connected to one shift register unit is the same.

8. The display panel according to claim 7, characterized in that: In the first group of shift register circuits, the second group of shift register circuits, the third group of shift register circuits and the fourth group of shift register circuits, one shift register unit is electrically connected to two rows of pixel circuits.

9. The display panel according to claim 1, characterized in that: The pixel circuit includes a driving transistor, and a gate reset transistor, a threshold capture transistor, a light emission control transistor, and a bias voltage writing transistor electrically connected to the driving transistor; The plurality of shift register circuits include a first shift register circuit, a second shift register circuit and a third shift register circuit, the first shift register circuit is electrically connected to the gate reset transistor and the threshold capture transistor, the second shift register circuit is electrically connected to the light emission control transistor, and the third shift register circuit is electrically connected to the bias voltage writing transistor; At least two of the first group of shift register circuits, the second group of shift register circuits, and the third group of shift register circuits are electrically connected to the same group of the clock signal lines.

10. The display panel according to claim 2 or 9, characterized in that: The gate reset transistor and the threshold grab transistor each include a metal oxide.

11. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-10.

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