High-speed signal time sequence bias method and device applied to reliability test

Abstract

The invention discloses a high-speed signal time sequence bias method and device applied to a reliability test. The method comprises the following steps: finding out an effective capture time interval of each bit DQ signal during read-write operation; calculating the midpoint time of each bit DQ signal, and aligning the midpoint time with the DQS to serve as an optimal capture time point; starting from the optimal capturing time point, deviating leftwards or rightwards by a set step length, and performing time deviation of different degrees; performing read-write left pulling deviation or right pulling deviation operation tests under different temperature conditions, and recording test results; according to a test result, finding out a limit boundary causing a test failure; and judging whether the current design margin is enough or not according to the limit boundary, and if not, adjusting the currently set driving parameters. According to the method, the product limit boundary is found out through batch sample data, whether the margin is enough to cover the design parameter deviation or not is evaluated, the normal read-write service of the memory can be ensured even in an extreme scene, error code failure is avoided, and the robustness of the product is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data storage, and more specifically to a high-speed signal timing deviation method and device used in reliability testing. Background Art

[0002] Flash media storage (such as SSD, EMMC, UFS, etc.) often encounters data transmission problems such as UECC and read / write error. The main reason is the bit error caused by abnormal information transmission between the embedded host controller and the flash storage medium. These failures are usually caused by the deviation of parameters such as clock deviation, jitter, delay, impedance mismatch, etc. in the synchronous clock signal transmission process from the normal value. The reasons for these parameter deviations come from device errors, PCB material errors, environmental impacts, etc.

[0003] To solve such problems, hardware developers often use signal integrity simulation and single-unit waveform testing to determine margins to ensure design, but such traditional methods are only considered from a theoretical and single-unit perspective, and cannot guarantee whether the signal quality margin is sufficient after mass shipment of products, and will still cause high probability failures due to signal quality fluctuations. In addition, for small package integrated products such as EMMC and USF, it is impossible to test the waveform by physical means, and the signal quality can only be accepted by SI simulation, DQ Rx Eye Mask virtual evaluation and data verification methods. It is also impossible to find the signal quality deviation boundary, identify SI signal quality risks in advance, and take preventive measures. Summary of the invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a high-speed signal timing deviation method and device for reliability testing.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] In a first aspect, the present invention provides a high-speed signal timing deviation method for reliability testing, comprising:

[0007] Find out the effective capture time interval of each bit DQ signal during read and write operations;

[0008] Calculate the midpoint time of each bit DQ signal and align it with DQS as the best capture time point;

[0009] Starting from the best capture time point, shift left or right by a set step length to perform different degrees of time deviation;

[0010] Perform left-pull or right-pull operation tests for reading and writing under different temperature conditions and record the test results;

[0011] According to the test results, find out the limit boundary that causes test failure;

[0012] Determine whether the current design margin is sufficient based on the limit boundary. If not, adjust the currently set drive parameters.

[0013] Further, the step of finding out the effective capture time interval of each bit DQ signal during the read and write operations includes:

[0014] Perform initial alignment training on DQS and DQ signals;

[0015] In the initial alignment training, the time point at which the high or low level of each bit DQ signal is captured is recorded;

[0016] Record the delay time point when each bit DQ signal starts to be captured at a high level or a low level;

[0017] Record the delay time point at which the high level or low level cutoff of each bit DQ signal is captured;

[0018] The effective capture time interval is calculated according to the start capture delay time point and the end capture delay time point.

[0019] Furthermore, the effective capture time interval is calculated according to the start capture delay time point and the end capture delay time point, and the calculation formula is as follows:

[0020] Δtx=tx2-tx1;

[0021] Wherein, tx2 represents the delay time point from which the capture is terminated, and tx1 represents the delay time point from which the capture is initiated.

[0022] Furthermore, the midpoint time of each bit DQ signal is calculated and aligned with DQS as the optimal capture time point. The calculation formula is as follows:

[0023]

[0024] Where tx1 represents the delay time point of the start of capture, and Δtx represents the effective capture time interval.

[0025] Furthermore, starting from the optimal capture time point, shifting to the left or right by a set step length to perform time shifting to different degrees includes:

[0026] Set the time deviation step length;

[0027] Starting from the optimal capture time point, the time is shifted to the left and right by the time shift step size.

[0028] Further, the reading and writing left-pull bias or right-pull bias operation test is performed under different temperature conditions, and the test results are recorded, including:

[0029] Setting a temperature range, wherein the temperature range includes low temperature, normal temperature and high temperature;

[0030] In low temperature, normal temperature and high temperature environments, read and write offsets are performed to the left and right according to the set time deviation step, and the results are recorded.

[0031] Further, judging whether the current design margin is sufficient according to the limit boundary, and if not sufficient, adjusting the currently set driving parameters, includes:

[0032] Compare limit boundaries to current design margins;

[0033] If the limit boundary is greater than the current design margin, the current design margin is determined to be insufficient.

[0034] In a second aspect, the present invention further provides a high-speed signal timing deviation pulling device for reliability testing, comprising:

[0035] A search unit, used to find out the effective capture time interval of each bit DQ signal during the read and write operations;

[0036] A first calculation unit is used to calculate the midpoint time of each bit DQ signal and align it with DQS as the best capture time point;

[0037] The time deviation unit is used to shift the set step length to the left or right from the optimal capture time point to perform different degrees of time deviation;

[0038] Temperature shock test unit, used to perform read and write left-pull bias or right-pull bias operation tests under different temperature conditions and record the test results;

[0039] A screening unit is used to find the limit boundary causing test failure according to the test results;

[0040] The determination unit is used to determine whether the current design margin is sufficient according to the limit boundary, and if not, adjust the currently set driving parameters.

[0041] In a third aspect, the present invention also provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the high-speed signal timing deviation method for reliability testing as described above is implemented.

[0042] In a fourth aspect, the present invention further provides a computer-readable storage medium, the storage medium stores a computer program, the computer program includes program instructions, and when the program instructions are executed by a processor, the processor executes the high-speed signal timing deviation method applied to reliability testing as described above. The beneficial effect of the present invention compared with the prior art is: the high-speed signal timing deviation method applied to reliability testing includes: finding the effective capture time interval of each bit DQ signal during read and write operations; calculating the midpoint time of each bit DQ signal, and aligning it with DQS as the optimal capture time point; starting from the optimal capture time point, shifting the set step length to the left or right, and performing different degrees of time deviation; performing read and write left deviation or right deviation operation tests under different temperature conditions, and recording the test results; according to the test results, finding the limit boundary that causes the test failure; judging whether the current design margin is sufficient according to the limit boundary, if not, adjusting the currently set drive parameters. The present invention performs biasing based on the timing of DQS and DQ, finds out the product limit boundary through batch sample data, and evaluates whether the margin is sufficient to cover the design parameter deviation. Even in extreme scenarios, it can ensure that the memory read and write services are normal, and error-related failures will not occur, thereby improving the robustness of the product.

[0043] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0045] Figure 1 A flowchart of a high-speed signal timing deviation method for reliability testing provided by a specific embodiment of the present invention;

[0046] Figure 2 A schematic block diagram of a high-speed signal timing deviation pulling device for reliability testing provided by a specific embodiment of the present invention;

[0047] Figure 3 A schematic block diagram of a computer device provided for a specific embodiment of the present invention;

[0048] Figure 4 A hardware framework diagram provided for a specific embodiment of the present invention;

[0049] Figure 5 A schematic diagram of left-pull and right-pull of a write operation provided in a specific embodiment of the present invention;

[0050] Figure 6 A schematic diagram of left-pull and right-pull deflections in a read operation provided in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0053] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an" and "the" are intended to include plural forms unless the context clearly indicates otherwise.

[0054] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0055] like Figure 4 As shown, the flash media memory is mainly composed of an embedded controller and a flash storage medium, and the interface between the two is read / write operation through the Toggle / ONFI protocol. At the same time, it is agreed that the embedded controller IO data output and the flash storage medium IO reception are write operations, and the flash storage medium IO data output and the embedded controller IO data reception are read operations. The 8-bit DQ (data) bidirectional synchronous clock signal constitutes the output bus. During the read / write operation, each DQ must be sampled with the center or edge of the DQS_c / DQS_t (source synchronous clock) to ensure that each DQ data can be received correctly.

[0056] It should be noted that during the data transmission process, the 8-bit DQ bidirectional synchronous clock signal only allows read operation or write operation at a certain moment, and the two cannot be performed at the same time. When performing a read operation, DQS (DQS_c / DQS_t) and DQx (DQ0, DQ1, DQ2, ..., DQ7) are edge-aligned; when performing a write operation, DQS and DQ are center-aligned.

[0057] Next, a high-speed signal timing deviation method is introduced with a specific embodiment.

[0058] like Figure 1 As shown, an embodiment of the present invention provides a high-speed signal timing deviation method applied to reliability testing, including the following steps: S10-S60.

[0059] S10, finding out the effective capture time interval of each bit DQ signal during the read and write operations.

[0060] In one embodiment, step S10 specifically includes the following steps: S101 - S1015 .

[0061] S101 , perform initial alignment training on DQS and DQ signals.

[0062] This process is to ensure that the signals are synchronized in the initial state.

[0063] S102 . In the initial alignment training, record the time point at which the high level or low level of each bit DQ signal is captured.

[0064] S103, recording the delayed time point at which the high level or low level of each bit DQ signal starts to be captured.

[0065] S104, recording the delayed time point at which the high level or low level of each bit DQ signal is cut off and captured.

[0066] For steps S102-S104, Figure 5-Figure 6 As shown, in this embodiment, for each bit DQ signal (e.g., DQ0, DQ1, DQ2, ..., DQ7), the delay time point tx1 (e.g., t01, t11, t21, ..., t71) at which the high level or low level starts to be captured is recorded. Similarly, the delay time point tx2 (e.g., t02, t12, t22, ..., t72) at which the high level or low level of each bit DQ signal is cut off and captured is recorded. Specifically, tx1: represents the earliest time when the signal is just captured. tx2: represents the latest time when the signal is just captured.

[0067] S105: Calculate an effective capture time interval according to a capture start delay time point and a capture end delay time point.

[0068] The capture range of the signal is determined by calculating the effective capture time interval Δtx of each bit DQ signal.

[0069] The calculation formula is as follows:

[0070] Δtx=tx2-tx1;

[0071] Wherein, tx2 represents the delay time point from which the capture is terminated, and tx1 represents the delay time point from which the capture is initiated.

[0072] For example, for DQ0, Δt0=t02-t01; similarly, for DQ1, Δt1=t12-t11, and so on.

[0073] Through the above steps, the effective capture time interval and the best capture time point of each bit DQ signal are found. Then, specific read and write operations can be performed at these best time points to ensure the accuracy of signal capture. At the same time, this information also provides basic data for subsequent time deviation tests.

[0074] S20, calculating the midpoint time of each bit DQ signal and aligning it with DQS as the optimal capture time point.

[0075] In one embodiment, step S20 specifically includes the following steps:

[0076] The midpoint time is calculated as follows:

[0077]

[0078] Where tx1 represents the delay time point of the start of capture, and Δtx represents the effective capture time interval.

[0079] By setting the midpoint time as the optimal delay time point for DQS to capture the high or low level of DQx during read and write operations, it is ensured that there is enough time margin to the left or right.

[0080] S30, starting from the optimal capture time point, shifting to the left or right by a set step length to perform time shifting to different degrees.

[0081] In one embodiment, step S30 specifically includes the following steps: S301 - S302 .

[0082] S301, setting the time deviation step length.

[0083] S302, starting from the optimal capture time point, shift the time to the left and right by the time deviation step length respectively.

[0084] For steps S301-S302, Figure 5-Figure 6As shown, in this embodiment, taking the optimal delay time point of DQx high level or low level (i.e., the optimal capture time point) as the starting point, the minimum step (offset step) is set according to the controller parameters. If DQx is offset to the left by n*step, the offset time is tx3. At this time, tx3 is set to the optimal delay time point for DQS to capture the high level of DQx, and the left pull is realized; if the right pull is realized, it is obtained by offsetting to the right by n*step.

[0085] S40, performing a read / write left-pull bias or right-pull bias operation test under different temperature conditions, and recording the test results.

[0086] In one embodiment, step S40 specifically includes the following steps: S401 - S402 .

[0087] S401, setting a temperature range, wherein the temperature range includes low temperature, normal temperature and high temperature.

[0088] S402, respectively, in low temperature, normal temperature and high temperature environments, read and write offsets to the left and right according to the set time offset step length, and record the results.

[0089] For steps S401-S402, in this embodiment, performing read and write left-pull bias or right-pull bias operation tests under different temperature conditions can help evaluate the performance of the system under extreme environments. Specifically:

[0090] Set a temperature range, including low temperature, normal temperature and high temperature. For example: low temperature is -40℃, normal temperature is 25℃, and high temperature is 85℃. Set a time deviation step (step), for example: step = 1ns.

[0091] Then, read and write left-pull bias and right-pull bias operation tests were carried out under different temperature conditions.

[0092] Low temperature condition test: In a low temperature environment, i.e. -40℃, starting from the best capture time point, shift to the left and right by a certain time step, perform read and write operations, and record whether errors occur. Among them, shift to the left, that is, shift to the left by the step length (e.g. 1ns) from the best capture time point, perform read and write operations, and record the results. If there is no error, continue to increase the offset (e.g. step = 2ns), perform read and write operations, and record the results. Repeat the above steps until the minimum offset at which an error occurs is found. Shift to the right, that is, shift to the right by the step length (e.g. 1ns) from the best capture time point, perform read and write operations, and record the results. If there is no error, continue to increase the offset (e.g. step = 2ns), perform read and write operations, and record the results.

[0093] Normal temperature test: In a normal temperature environment, i.e. 25°C, repeat the test steps under low temperature conditions and record the read and write operation results.

[0094] High temperature condition test: In a high temperature environment, i.e. 85°C, repeat the test steps under low temperature conditions and record the read and write operation results.

[0095] Record the results of read and write operations after each bias pull under different temperature conditions, especially the offset where errors occurred.

[0096] S50. According to the test results, find out the limit boundary causing the test failure.

[0097] The limiting boundary is the time margin.

[0098] Assuming that the optimal capture time point for DQ0 is 15ns, the recorded data is as follows:

[0099] Low temperature conditions:

[0100] Leftward deviation: Errors begin to occur after a deviation of 2ns (13ns), and the minimum deviation is 2ns.

[0101] Offset to the right: Errors begin to occur at an offset of 2ns (17ns), and the minimum offset = 2ns.

[0102] Normal temperature conditions:

[0103] Leftward deviation: Errors begin to occur when the deviation is 3ns (12ns), and the minimum deviation is 3ns.

[0104] Offset to the right: Errors begin to occur when the offset is 3ns (18ns), and the minimum offset = 3ns.

[0105] High temperature conditions:

[0106] Leftward deviation: Errors begin to occur after a deviation of 1ns (14ns), and the minimum deviation is 1ns.

[0107] Offset to the right: Errors begin to occur when the offset is 1ns (16ns), and the minimum offset is 1ns.

[0108] Final time margin:

[0109] Low temperature condition: minimum time margin = 2ns;

[0110] Normal temperature conditions: minimum time margin = 3ns;

[0111] High temperature condition: minimum time margin = 1ns.

[0112] S60: Determine whether the current design margin is sufficient according to the limit boundary; if not, adjust the currently set drive parameters.

[0113] In one embodiment, step S60 specifically includes the following steps: S601 - S602 .

[0114] S601. Compare the limit boundary with the current design margin.

[0115] S602: If the limit boundary is greater than the current design margin, it is determined that the current design margin is insufficient.

[0116] For steps S601-S602,

[0117] Compare the recorded minimum time margin with the design target to evaluate whether the design requirements are met.

[0118] If the minimum time margin recorded under all test conditions (low temperature, normal temperature, high temperature) is greater than or equal to the design target, it means that the design margin is sufficient. If the minimum time margin recorded under certain temperature test conditions is less than the design target, it means that the design margin is insufficient and needs to be adjusted.

[0119] The present invention performs biasing based on the timing of DQS and DQ, finds out the product limit boundary through batch sample data, and evaluates whether the margin is sufficient to cover the design parameter deviation. Even in extreme scenarios, it can ensure that the memory read and write services are normal, and error-related failures will not occur, thereby improving the robustness of the product.

[0120] The embodiment of the present invention also provides a high-speed signal timing deviation device for reliability testing, which is used to perform the steps in any embodiment of the high-speed signal timing deviation method for reliability testing. Figure 2 , Figure 2 A schematic block diagram of a high-speed signal timing deviation pulling device 100 for reliability testing provided in an embodiment of the present application is shown. The high-speed signal timing deviation pulling device 100 for reliability testing specifically includes:

[0121] The search unit 110 is used to find out the effective capture time interval of each bit DQ signal during the read and write operations; the first calculation unit 120 is used to calculate the midpoint time of each bit DQ signal and align it with DQS as the optimal capture time point; the time deviation unit 130 is used to shift the set step size to the left or right from the optimal capture time point to perform different degrees of time deviation; the temperature shock test unit 140 is used to perform read and write left deviation or right deviation operation tests under different temperature conditions and record the test results; the screening unit 150 is used to find out the limit boundary that causes the test failure based on the test results; the judgment unit 160 is used to judge whether the current design margin is sufficient based on the limit boundary, and if not, adjust the currently set driving parameters.

[0122] In one embodiment, the search unit 110 includes:

[0123] An alignment training module is used to perform initial alignment training on DQS and DQ signals; a first recording module is used to record the time point when the high level or low level of each bit DQ signal is captured during the initial alignment training; a second recording module is used to record the delay time point when the high level or low level of each bit DQ signal starts to be captured; a third recording module is used to record the delay time point when the high level or low level of each bit DQ signal stops being captured; a calculation module is used to calculate the effective capture time interval based on the delay time point when the start is captured and the delay time point when the end is captured.

[0124] In one embodiment, the time deviation unit 130 includes:

[0125] The first setting module is used to set the time deviation step; the offset module is used to offset the time deviation step to the left and right respectively starting from the optimal capture time point.

[0126] In one embodiment, the temperature shock testing unit 140 includes:

[0127] The second setting module is used to set the temperature range, which includes low temperature, normal temperature and high temperature; the offset recording module is used to perform left and right read and write offsets according to the set time deviation step in low temperature, normal temperature and high temperature environments, and record the results.

[0128] In one embodiment, the determination unit 160 includes:

[0129] The comparison module is used to compare the limit boundary with the current design margin; the determination module is used to determine that the current design margin is insufficient if the limit boundary is greater than the current design margin.

[0130] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the high-speed signal timing biasing device 100 and each unit used for reliability testing can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and conciseness of the description, it will not be repeated here.

[0131] The high-speed signal timing biasing device for reliability testing can be implemented in the form of a computer program. The computer program can be used in Figure 3 Runs on the computer device shown.

[0132] See also Figure 3 , Figure 3 700 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 700 may be a server, wherein the server may be an independent server or a server cluster composed of multiple servers.

[0133] like Figure 3As shown, the computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the high-speed signal timing deviation method for reliability testing described above are implemented.

[0134] The computer device 700 may be a terminal or a server. The computer device 700 includes a processor 720 , a memory, and a network interface 750 connected via a system bus 710 , wherein the memory may include a non-volatile storage medium 730 and an internal memory 740 .

[0135] The non-volatile storage medium 730 can store an operating system 731 and a computer program 732. When the computer program 732 is executed, the processor 720 can execute a high-speed signal timing deviation method for reliability testing.

[0136] The processor 720 is used to provide computing and control capabilities and support the operation of the entire computer device 700.

[0137] The internal memory 740 provides an environment for the operation of the computer program 732 in the non-volatile storage medium 730. When the computer program 732 is executed by the processor 720, the processor 720 can execute a high-speed signal timing deviation method applied to reliability testing.

[0138] The network interface 750 is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will appreciate that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the present application scheme, and does not constitute a limitation on the computer device 700 to which the present application scheme is applied. The specific computer device 700 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements. The processor 720 is used to run the program code stored in the memory to implement the high-speed signal timing deviation method applied to reliability testing.

[0139] Those skilled in the art will understand that Figure 3 The embodiments of the computer device shown in the figure do not constitute a limitation on the specific composition of the computer device. In other embodiments, the computer device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently. For example, in some embodiments, the computer device may only include a memory and a processor. In such embodiments, the structure and function of the memory and the processor are the same as those of the embodiment of the present invention. Figure 3 The embodiments shown are consistent and will not be described again here.

[0140] It should be understood that in the embodiment of the present application, the processor 720 may be a central processing unit (CPU), and the processor 720 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0141] In another embodiment of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium may be a non-volatile computer-readable storage medium. The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the high-speed signal timing deviation method for reliability testing disclosed in an embodiment of the present invention is implemented.

[0142] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the above-described equipment, devices and units can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. Those of ordinary skill in the art can appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0143] In the several embodiments provided by the present invention, it should be understood that the disclosed equipment, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. Units with the same function may also be combined into one unit. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, or may be electrical, mechanical or other forms of connection.

[0144] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0145] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0146] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), disk or optical disk and other media that can store program codes.

[0147] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A high-speed signal timing deviation method for reliability testing, characterized in that: include: Find out the effective capture time interval of each bit DQ signal during read and write operations; Calculate the midpoint time of each bit DQ signal and align it with DQS as the best capture time point; Starting from the best capture time point, shift left or right by a set step length to perform different degrees of time deviation; Perform left-pull or right-pull operation tests for reading and writing under different temperature conditions and record the test results; According to the test results, find out the limit boundary that causes test failure; Determine whether the current design margin is sufficient based on the limit boundary. If not, adjust the currently set drive parameters.

2. The high-speed signal timing deviation method for reliability testing according to claim 1 is characterized in that: The step of finding out the effective capture time interval of each bit DQ signal during the read and write operations includes: Perform initial alignment training on DQS and DQ signals; In the initial alignment training, the time point at which the high or low level of each bit DQ signal is captured is recorded; Record the delay time point when each bit DQ signal starts to be captured at a high level or a low level; Record the delay time point at which the high level or low level cutoff of each bit DQ signal is captured; The effective capture time interval is calculated according to the start capture delay time point and the end capture delay time point.

3. The high-speed signal timing deviation method for reliability testing according to claim 2 is characterized in that: The effective capture time interval is calculated according to the start capture delay time point and the end capture delay time point, and the calculation formula is as follows: Δtx=tx2-tx1; Wherein, tx2 represents the delay time point from which the capture is terminated, and tx1 represents the delay time point from which the capture is initiated.

4. The high-speed signal timing deviation method for reliability testing according to claim 1, characterized in that: The midpoint time of each bit DQ signal is calculated and aligned with DQS as the optimal capture time point. The calculation formula is as follows: Where tx1 represents the delay time point of the start of capture, and Δtx represents the effective capture time interval.

5. The high-speed signal timing deviation method for reliability testing according to claim 1, characterized in that: Starting from the optimal capture time point, the set step length is shifted to the left or right to perform different degrees of time shifting, including: Set the time deviation step length; Starting from the optimal capture time point, the time is shifted to the left and right by the time shift step size.

6. The high-speed signal timing deviation method for reliability testing according to claim 1, characterized in that: The test of reading and writing left-pull bias or right-pull bias operation is performed under different temperature conditions, and the test results are recorded, including: Setting a temperature range, wherein the temperature range includes low temperature, normal temperature and high temperature; In low temperature, normal temperature and high temperature environments, read and write offsets are performed to the left and right according to the set time deviation step, and the results are recorded.

7. The high-speed signal timing deviation method for reliability testing according to claim 1, characterized in that: The step of judging whether the current design margin is sufficient according to the limit boundary, and if not sufficient, adjusting the currently set driving parameters, includes: Compare limit boundaries to current design margins; If the limit boundary is greater than the current design margin, the current design margin is determined to be insufficient.

8. A high-speed signal timing deviation device for reliability testing, characterized in that: include: A search unit, used to find out the effective capture time interval of each bit DQ signal during the read and write operations; A first calculation unit is used to calculate the midpoint time of each bit DQ signal and align it with DQS as the best capture time point; The time deviation unit is used to shift the set step length to the left or right from the optimal capture time point to perform different degrees of time deviation; Temperature shock test unit, used to perform read and write left-pull bias or right-pull bias operation tests under different temperature conditions and record the test results; A screening unit is used to find the limit boundary causing test failure according to the test results; The determination unit is used to determine whether the current design margin is sufficient according to the limit boundary, and if not, adjust the currently set driving parameters.

9. A computer device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the high-speed signal timing deviation method for reliability testing as claimed in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor, the processor executes the high-speed signal timing deviation method for reliability testing as described in any one of claims 1 to 7.

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