Novel zirconium-based deep groove structure energy storage capacitor and preparation method thereof

Abstract

The invention discloses a novel zirconium-based deep groove structure energy storage capacitor and a preparation method thereof. The energy storage capacitor comprises a deep groove structure silicon substrate, a SiO2 insulating layer, a bottom electrode, an anti-ferroelectric layer and a top electrode which are sequentially stacked from bottom to top, the preparation method comprises the following steps: cleaning a planar silicon wafer; etching the surface of the cleaned silicon substrate to obtain a deep groove structure silicon substrate; oxidizing a layer of SiO2 on the surface of the silicon substrate with the deep groove structure as an insulating layer; growing a bottom electrode on the surface of the SiO2 insulating layer; preparing an anti-ferroelectric layer on the bottom electrode, wherein the anti-ferroelectric layer is of a ZrO2 / Al2O3 multi-layer stacked structure or a ZrO2 / TiO2 multi-layer stacked structure; preparing a top electrode on the anti-ferroelectric layer; and annealing the obtained device to obtain the energy storage capacitor with the zirconium-based deep groove structure. According to the invention, the anti-ferroelectric layer with a multi-layer stacked structure is adopted, and the novel energy storage device with a deep groove structure is combined, so that the performance in the aspect of electric energy storage is better.

Description

Technical Field

[0001] The present invention belongs to the technical field of memory devices, and in particular relates to a novel zirconium-based deep-groove structure energy storage capacitor and a preparation method thereof. Background Art

[0002] In the current energy storage technology, compared with energy storage devices such as electrochemical capacitors, fuel cells, and lithium-ion batteries, dielectric capacitors have the advantages of high power density and the ability to quickly achieve charging and discharging. They have broad application prospects in high-power power systems and microelectronic devices. However, their low energy density limits their practical applications. Several types of dielectric materials that have been studied include polymers, ceramics, and glass. Due to their large deposition thickness (micrometers or greater), they are not suitable for nanoscale devices. Compared with various dielectric materials, the new antiferroelectric material (ZrO2) has the advantages of special double hysteresis loops, high polarization intensity and breakdown strength, low energy loss, small deposition thickness, simple composition, and compatibility with CMOS processes. It is expected to become an ideal dielectric energy storage material; and the mature atomic layer deposition (ALD) preparation technology makes the antiferroelectric film have good conformality during the growth process, which provides feasibility for its integration in three-dimensional deep groove nanostructures.

[0003] In the prior art, a paper entitled “Improved energy storage performance of PbZrO3antiferroelectric thin films crystallized by microwave radiation” discloses an antiferroelectric thin film prepared by a sol-gel method. A NiO-PbZrO3 composite thin film is deposited on a SiO2 / Si substrate with a LaNiO3 buffer layer by a sol-gel method to prepare an antiferroelectric capacitor with a structure of Si / SiO2 / LaNiO3 / PbZrO3 / NiO / PbZrO3. However, due to the characteristics of traditional perovskite materials, the dielectric layer has energy storage properties only when the thickness is at the level of hundreds of nanometers, which cannot match the inevitable trend of continuous miniaturization of device size. At the same time, the preparation process of perovskite materials is complicated and the temperature is high, which is not compatible with integrated circuit technology (CMOS technology). In addition, the Pb element contained in PbZrO3 will volatilize under high temperature conditions, which has potential harm to human body and environment, so that the energy storage density of the prepared capacitor is low, which is only 19.6 J / cm 3 .

[0004] In the prior art, the name is "Stress-Induced Crystallization of Thin Hf 1-X Zr XThe paper "O2 Films: The Origin of Enhanced Energy Density with Minimized Energy Loss for Lead-Free Electrostatic Energy Storage Applications" discloses an antiferroelectric film prepared by atomic layer deposition. A 10nm thick ZrO2 is prepared by atomic layer deposition to prepare an antiferroelectric capacitor with a structure of Si / SiO2 / TiN / ZrO2 / TiN. However, due to the use of a single ZrO2 film as the antiferroelectric layer and a planar silicon substrate, the energy storage density is low, only 37.6J / cm 3 , thus affecting the practical application of capacitors. Summary of the invention

[0005] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a novel zirconium-based deep trench structure energy storage capacitor and a preparation method thereof. Firstly, by using a silicon substrate with a deep trench structure, the effective area of ​​the capacitor is increased, which has the effect of increasing the energy storage density of the capacitor; secondly, by using an antiferroelectric layer with a stacked structure, not only the leakage current of the capacitor can be reduced and the breakdown field strength can be increased, but also the service life of the antiferroelectric layer during the repeated charging and discharging process of the capacitor can be effectively extended. It has the characteristics of high energy storage density and energy storage efficiency, environmental friendliness, and suitability for matching with existing large-scale production processes.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A novel zirconium-based deep trench structure energy storage capacitor comprises a deep trench structure silicon substrate 1, a SiO2 insulating layer 2, a bottom electrode 3, an antiferroelectric layer 4 and a top electrode 5 which are stacked in sequence from bottom to top.

[0008] The bottom electrode 3 and the top electrode 5 are each made of at least one of TaN, Au, TiN, W, Mo, Pt, Pd, Al and Ru.

[0009] The deep groove structure silicon substrate 1 is a deep groove structure with an aspect ratio of (1 to 100): 1, and is located at the bottom layer of the capacitor; the SiO2 insulating layer 2 is a passivation layer attached to the surface of the deep groove structure silicon substrate 1, has a thickness of 50-300nm, and is located between the deep groove structure silicon substrate 1 and the bottom electrode 3; the bottom electrode 3 has a thickness of 10nm to 200nm, and is located between the SiO2 insulating layer 2 and the antiferroelectric layer 4; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure or a ZrO2 / TiO2 multilayer stacking structure, and the thickness of the antiferroelectric layer 4 is 6 to 50nm, wherein the thickness of ZrO2 is 5 to 47nm, and the thickness of Al2O3 or TiO2 is 1 to 3nm, and is located between the bottom electrode 3 and the top electrode 5; the top electrode 5 is located on the antiferroelectric layer 4, and the thickness of the top electrode 5 is 10nm to 200nm, and is the top layer of the capacitor.

[0010] A method for preparing a novel zirconium-based deep trench structure energy storage capacitor comprises the following steps:

[0011] Step 1, cleaning the substrate: ultrasonically cleaning the planar silicon wafer in acetone, ethanol and deionized water for 5 to 15 minutes respectively to remove surface organic matter; then repeatedly cleaning in a mixed solution of hydrofluoric acid: aqueous solution = 1: (25 to 75) by volume to remove surface inorganic impurities to obtain a cleaned silicon substrate;

[0012] Step 2, etching the deep groove structure silicon substrate 1: spin-coating a layer of photoresist on the surface of the silicon substrate cleaned in step 1, patterning the photoresist, and using the photoresist as a mask to etch the silicon substrate, with the etching depth-to-width ratio being (1-100):1, to obtain the deep groove structure silicon substrate 1;

[0013] Step 3, growing SiO2 insulating layer 2: using thermal oxidation method to oxidize a layer of SiO2 as an insulating layer on the surface of the deep groove structure silicon substrate 1 obtained in step 2, the oxidant is H2O and O2, the H2O and O2 are in any proportion, the thermal oxidation time is 0.5 to 2 hours, and the thickness of the insulating layer is 50-300nm;

[0014] Step 4, growing a bottom electrode 3: growing a bottom electrode 3 on the surface of the SiO2 insulating layer 2 formed in step 3;

[0015] Step 5, growing an antiferroelectric layer 4: preparing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4;

[0016] Step 6, preparing a top electrode 5: preparing a top electrode 5 on the antiferroelectric layer 4 formed in step 5;

[0017] Step 7, annealing: anneal the device obtained in step 6 at 350-450° C. and N 2 or H 2 for 0.5 minute to 60 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

[0018] The bottom electrode 3 in step 4 and the top electrode 5 in step 6 are both prepared by one of the following methods: electron beam evaporation, chemical vapor deposition, ion beam sputtering, atomic layer deposition, magnetron sputtering, and pulsed laser deposition.

[0019] The step 5 grows the antiferroelectric layer 4, specifically by an atomic layer deposition method, the steps are:

[0020] Using TDMAZr (Zr[N(CH3)2]4), TMA (Al(CH3)3) and H2O as Zr, Al and oxygen sources respectively, an antiferroelectric layer 4 is deposited on the bottom electrode 3 generated in step 4 by atomic layer deposition; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3, and the thickness of the antiferroelectric layer 4 is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of Al2O3 is 1 to 3 nm;

[0021] Among them, ZrO2 / Al2O3 in atomic layer deposition can be replaced by ZrO2 / TiO2. The specific method is: using Zr[N(CH3)2]4, Ti[N(CH3)2]4 and H2O as Zr, Ti and oxygen sources respectively, by atomic layer deposition, an antiferroelectric layer 4 of a ZrO2 / TiO2 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of TiO2 is deposited on the bottom electrode 3 generated in step 4, and the thickness of the antiferroelectric layer 4 is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of TiO2 is 1 to 3 nm.

[0022] The step 5 grows the antiferroelectric layer 4, specifically by pulsed laser deposition, the steps are:

[0023] A pulsed laser deposition method is used to alternately deposit ZrO2 / TiO2 thin films, and an antiferroelectric layer 4 is deposited on the bottom electrode 3 generated in step 4; the antiferroelectric layer 4 is a ZrO2 / TiO2 multilayer stacked structure formed by alternately stacking multiple layers of ZrO2 and multiple layers of TiO2, and the thickness of the antiferroelectric layer 4 is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; and the thickness of TiO2 is 1 to 3 nm;

[0024] Among them, ZrO2 / TiO2 in the pulse laser deposition method can be replaced by ZrO2 / Al2O3. The specific method is: using the pulse laser deposition method, alternately depositing ZrO2 / Al2O3 films, and depositing an antiferroelectric layer 4 of a ZrO2 / Al2O3 multilayer stacked structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3 on the bottom electrode 3 generated in step 4. The thickness of the antiferroelectric layer 4 is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of Al2O3 is 1 to 3 nm.

[0025] The step 5 grows the antiferroelectric layer 4, specifically by magnetron sputtering, the steps are:

[0026] Growing an antiferroelectric layer 4: in an oxygen and argon environment, using solid Al and solid Zr as targets, depositing a ZrO2 / Al2O3 thin film, forming an antiferroelectric layer 4 of a ZrO2 / Al2O3 multilayer stacking structure in which multiple layers of ZrO2 and multiple layers of Al2O3 are alternately stacked on the bottom electrode 3 generated in step 4, wherein the thickness of the antiferroelectric layer 4 is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of Al2O3 is 1 to 3 nm;

[0027] Among them, ZrO2 / Al2O3 prepared by magnetron sputtering can be replaced by ZrO2 / TiO2, and solid Ti and solid Zr are used as targets to deposit ZrO2 / TiO2 thin film, and an antiferroelectric layer 4 of a ZrO2 / TiO2 multilayer stacked structure consisting of multiple layers of ZrO2 and multiple layers of TiO2 alternately stacked is formed on the bottom electrode 3 generated in step 4. The thickness of the antiferroelectric layer 4 is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of TiO2 is 1 to 3 nm.

[0028] The ZrO2 in the ZrO2 / Al2O3 multilayer stacking structure or the ZrO2 / TiO2 multilayer stacking structure can be doped with Ti, Si, or Ti and Si elements.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) The present invention can generate more interfaces in the multilayer film by introducing Al2O3 film or TiO2 film on the antiferroelectric layer 4. The interface layer can enhance the antiferroelectric phase of the antiferroelectric layer 4, thereby achieving a joint improvement in energy storage density and energy storage efficiency.

[0031] (2) The ZrO2 / Al2O3 multilayer stacking structure or ZrO2 / TiO2 multilayer stacking structure prepared by the present invention can not only reduce the leakage current of the capacitor and increase the breakdown field strength, but also effectively extend the service life of the antiferroelectric layer during the repeated charging and discharging process of the capacitor.

[0032] (3) The deep groove structure silicon substrate 1 prepared by the present invention increases the effective area of ​​the capacitor. Compared with the two-dimensional planar capacitor, the surface capacitance is greatly increased, further optimizing the energy storage density of the capacitor.

[0033] (4) The present invention combines a deep groove structure silicon substrate 1 with an antiferroelectric layer 4 of a ZrO2 / Al2O3 multilayer stacking structure or a ZrO2 / TiO2 multilayer stacking structure, which can not only reduce the leakage current of the capacitor and increase the breakdown field strength, but also effectively extend the service life of the antiferroelectric layer during the repeated charging and discharging process of the capacitor; secondly, introducing an Al2O3 film or a TiO2 film on the antiferroelectric layer can produce more interfaces in the multilayer film, and the interface layer can enhance the antiferroelectric phase of the antiferroelectric layer, thereby achieving a joint improvement in energy storage density and energy storage efficiency.

[0034] (5) The present invention uses a new ZrO2 material combined with Al2O3 or TiO2 material, which is environmentally friendly.

[0035] (6) The present invention adopts the atomic layer deposition process (ALD), which is compatible with the existing integrated circuit process (CMOS process) and is suitable for large-scale industrial production.

[0036] In summary, the present invention combines the antiferroelectric layer 4 of the ZrO2 / Al2O3 multilayer stacking structure or the ZrO2 / TiO2 multilayer stacking structure with the deep groove structure silicon substrate 1, so that the capacitor has the advantages of high energy storage density and efficiency and high breakdown field strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is an etching diagram of the deep trench structure silicon substrate 1 of the present invention.

[0038] Figure 2 This is a growth diagram of the SiO2 insulating layer 2 on the deep trench structure silicon substrate 1 of the present invention.

[0039] Figure 3 It is the growth diagram of the bottom electrode 3 of the present invention.

[0040] Figure 4 This is the growth diagram of the antiferroelectric layer 4 of the present invention.

[0041] Figure 5 It is the growth diagram of the top electrode 5 of the present invention.

[0042] Among them, 1. deep trench structure silicon substrate; 2. SiO2 insulating layer; 3. bottom electrode; 4. antiferroelectric layer; 5. top electrode. DETAILED DESCRIPTION

[0043] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0044] The present invention provides a novel zirconium-based deep trench structure energy storage capacitor, comprising a deep trench structure silicon substrate 1, a SiO2 insulating layer 2, a bottom electrode 3, an antiferroelectric layer 4 and a top electrode 5 which are sequentially prepared from bottom to top.

[0045] The deep groove structure silicon substrate 1 is a deep groove structure with an aspect ratio of (1 to 100): 1, which can increase the effective area of ​​the antiferroelectric capacitor and is located at the bottom layer of the capacitor; the SiO2 insulating layer 2 is a passivation layer attached to the surface of the deep groove structure silicon substrate 1, with a thickness of 50-300nm, which can reduce the leakage current of the capacitor and is located between the deep groove structure silicon substrate 1 and the bottom electrode 3; the bottom electrode 3 has a thickness of 10nm to 200nm and is located between the SiO2 insulating layer 2 and the antiferroelectric layer 4; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure or a ZrO2 / TiO2 multilayer stacking structure, which can further increase the thickness of the antiferroelectric layer 4 by 6 to 50nm, wherein the thickness of ZrO2 is 5 to 47nm, and the thickness of Al2O3 or TiO2 is 1 to 3nm, which increases the energy storage density of the capacitor and is located between the bottom electrode 3 and the top electrode 5; the top electrode 5 is located on the antiferroelectric layer 4, and the thickness of the top electrode 5 is 10nm to 200nm, which is the top layer of the capacitor.

[0046] The constituent materials of the bottom electrode 3 and the top electrode 5 are at least one of TaN, Au, TiN, W, Mo, Pt, Pd, Al and Ru. For example, with TiN as the bottom electrode, the top electrode can be one of TiN / W, TiN / Pt, Al / Au or TiN / Ru / Au.

[0047] The present invention also provides a method for preparing a novel zirconium-based deep groove structure energy storage capacitor, comprising the following steps:

[0048] Step 1, cleaning the substrate: ultrasonically cleaning the planar silicon wafer in acetone, ethanol and deionized water for 5 to 15 minutes respectively to remove surface organic matter; then repeatedly cleaning it three to five times in a mixed solution of hydrofluoric acid: aqueous solution = 1: (25 to 75) by volume to remove surface inorganic impurities to obtain a cleaned silicon substrate;

[0049] like Figure 1 As shown, step 2, etching the deep groove structure silicon substrate 1: spin-coating a layer of photoresist on the surface of the silicon substrate cleaned in step 1, patterning the photoresist, and using it as a mask to etch the silicon substrate, the etching depth-to-width ratio is (1-100):1, and the deep groove structure silicon substrate 1 is obtained;

[0050] like Figure 2 As shown, step 3, growing SiO2 insulating layer 2: using thermal oxidation method to oxidize a layer of SiO2 as an insulating layer on the surface of the deep groove structure silicon substrate 1 obtained in step 2, the oxidant is H2O and O2, H2O and O2 are in any proportion, the thermal oxidation time is 0.5 to 2 hours, and the thickness of the insulating layer is 50-300nm;

[0051] like Figure 3As shown, step 4, growing the bottom electrode 3: growing the bottom electrode 3 on the surface of the SiO2 insulating layer 2 generated in step 3; the specific method is: in a nitrogen and argon environment, using solid Ta as a target material, 1×10 -7 ~1.5×10 -7 Under a pressure of pa, a TaN bottom electrode is grown on the surface of the SiO2 insulating layer 2 generated in step 3, and the thickness of the TaN bottom electrode is 10nm to 200nm;

[0052] like Figure 4 As shown, step 5, growing an antiferroelectric layer 4: preparing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4; the specific method is detailed in the following 5 embodiments;

[0053] like Figure 5 As shown, step 6, preparing the top electrode 5: preparing the top electrode 5 on the antiferroelectric layer 4 generated in step 5; the specific method is: in a nitrogen and argon environment, using solid Ta as a target material, 1×10 -7 ~1.5×10 -7 Under a pressure of pa, a TaN top electrode is grown on the surface of the SiO2 insulating layer 2 generated in step 3, and the thickness of the TaN top electrode is 10nm to 200nm;

[0054] Step 7, annealing: anneal the device obtained in step 6 at 350-450° C. and N 2 or H 2 for 0.5 minute to 60 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

[0055] Example 1

[0056] A novel zirconium-based deep trench structure energy storage capacitor comprises a deep trench structure silicon substrate 1, a SiO2 insulating layer 2, a bottom electrode 3, an antiferroelectric layer 4 and a top electrode 5 which are stacked in sequence from bottom to top.

[0057] The bottom electrode 3 is made of TaN, and the top electrode 5 is made of Au.

[0058] The deep groove structure silicon substrate 1 is a deep groove structure with an aspect ratio of 1:1, and is located at the bottom layer of the capacitor; the SiO2 insulating layer 2 is a passivation layer attached to the surface of the deep groove structure silicon substrate 1, has a thickness of 50nm, and is located between the deep groove structure silicon substrate 1 and the bottom electrode 3; the bottom electrode 3 has a thickness of 50nm, and is located between the SiO2 insulating layer 2 and the antiferroelectric layer 4; the antiferroelectric layer 4 is a ZrO2 / TiO2 multilayer stacking structure, and the thickness of the antiferroelectric layer 4 is 6nm, wherein the thickness of ZrO2 is 5nm, and the thickness of TiO2 is 1nm, and is located between the bottom electrode 3 and the top electrode 5; the top electrode 5 is located on the antiferroelectric layer 4, and the thickness of the top electrode 5 is 50nm, which is the top layer of the capacitor.

[0059] A method for preparing a novel zirconium-based deep trench structure energy storage capacitor comprises the following steps:

[0060] Step 1, cleaning the substrate: ultrasonically clean the planar silicon wafer in acetone, ethanol and deionized water for 5 minutes respectively to remove surface organic matter; then repeatedly clean it three times in a mixed solution of hydrofluoric acid: aqueous solution = 1:25 by volume to remove surface inorganic impurities, thereby obtaining a cleaned silicon substrate;

[0061] Step 2, etching the deep groove structure silicon substrate 1: spin-coat a layer of photoresist on the surface of the silicon substrate cleaned in step 1, then expose for 3 seconds, use this as a mask, and perform alternating reactive ion etching on the silicon substrate until the etching depth-to-width ratio is 1:1, thereby obtaining the deep groove structure silicon substrate 1;

[0062] Step 3, growing SiO2 insulating layer 2: adopting thermal oxidation method, oxidants are H2O and O2, O2 flow rate is 50L / min, H2O flow rate is 100L / min, thermal oxidation is performed for 0.5h, and a layer of SiO2 is oxidized on the surface of the deep groove structure silicon substrate 1 obtained in step 2 as an insulating layer, and the thickness of the insulating layer is 50nm;

[0063] Step 4, growing bottom electrode 3: In a nitrogen and argon environment, solid Ta is used as the target material, 1×10 -7 Under a pressure of pa, a TaN bottom electrode is grown on the surface of the SiO2 insulating layer 2 formed in step 3, and the thickness of the TaN bottom electrode is 50nm;

[0064] Step 5, growing an antiferroelectric layer 4: adopting a pulsed laser deposition method, using TDMAZr (Zr [N (CH3) 2] 4), Ti [N (CH3) 2)] 4 and H2O as Zr, Ti and oxygen sources respectively, alternately depositing ZrO2 / TiO2 thin films, and depositing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4; the antiferroelectric layer 4 is a ZrO2 / TiO2 multilayer stacked structure formed by alternating multiple layers of ZrO2 and multiple layers of TiO2, and the thickness of the antiferroelectric layer is 6nm; wherein the thickness of ZrO2 is 5nm, and the thickness of TiO2 is 1nm;

[0065] Step 6, preparing the top electrode 5: using a gold thin film as a target material and an air sputtering atmosphere, depositing an Au thin film as the top electrode 5 on the antiferroelectric layer 4 generated in step 5, the thickness of the top electrode 5 being 50 nm;

[0066] Step 7, annealing: anneal the device obtained in step 6 at 350° C. and N 2 for 30 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

[0067] This embodiment adopts a ZrO2 / TiO2 multilayer stacked structure as an antiferroelectric layer, combined with a deep trench structure silicon substrate 1, to prepare a capacitor with a structure of TaN / ZrO2 / TiO2 / ZrO2 / TiO2 / Au. The addition of the TiO2 layer will produce compressive strain in the ZrO2 layer, reduce the hysteresis effect, and thus improve the energy storage effect of the capacitor.

[0068] Example 2

[0069] A novel zirconium-based deep trench structure energy storage capacitor comprises a deep trench structure silicon substrate 1, a SiO2 insulating layer 2, a bottom electrode 3, an antiferroelectric layer 4 and a top electrode 5 which are stacked in sequence from bottom to top.

[0070] The bottom electrode 3 is made of TiN, and the top electrode 5 is made of W.

[0071] The deep groove structure silicon substrate 1 is a deep groove structure with an aspect ratio of 10:1, and is located at the bottom layer of the capacitor; the SiO2 insulating layer 2 is a passivation layer attached to the surface of the deep groove structure silicon substrate 1, has a thickness of 100nm, and is located between the deep groove structure silicon substrate 1 and the bottom electrode 3; the bottom electrode 3 has a thickness of 100nm, and is located between the SiO2 insulating layer 2 and the antiferroelectric layer 4; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure, and the thickness of the antiferroelectric layer 4 is 10nm, wherein the thickness of ZrO2 is 9nm, and the thickness of Al2O3 is 1nm, and is located between the bottom electrode 3 and the top electrode 5; the top electrode 5 is located on the antiferroelectric layer 4, and the thickness of the top electrode 5 is 100nm, which is the top layer of the capacitor.

[0072] A method for preparing a novel zirconium-based deep trench structure energy storage capacitor comprises the following steps:

[0073] Step 1, cleaning the substrate: ultrasonically clean the planar silicon wafer in acetone, ethanol and deionized water for 10 minutes respectively to remove surface organic matter; then repeatedly clean it four times in a mixed solution of hydrofluoric acid: aqueous solution = 1:50 by volume to remove surface inorganic impurities, thereby obtaining a cleaned silicon substrate;

[0074] Step 2, etching the deep groove structure silicon substrate 1: spin-coat a layer of photoresist on the surface of the silicon substrate cleaned in step 1, and then expose for 3 seconds, using this as a mask, and perform alternating reactive ion etching on the silicon substrate until the etching depth-to-width ratio is 10:1, thereby obtaining the deep groove structure silicon substrate 1;

[0075] Step 3, growing SiO2 insulating layer 2: using thermal oxidation method to oxidize a layer of SiO2 as an insulating layer on the surface of the deep groove structure silicon substrate 1 obtained in step 2, the oxidant is H2O and O2, the O2 flow rate is 50L / min, the H2O flow rate is 100L / min, the thermal oxidation time is 1h, and the thickness of the insulating layer is 100nm;

[0076] Step 4, growing bottom electrode 3: In a nitrogen and argon environment, solid Ti is used as the target material, 1.25×10 -7 Under a pressure of pa, a TiN bottom electrode is grown on the surface of the SiO2 insulating layer 2 formed in step 3, and the thickness of the TiN bottom electrode is 100 nm;

[0077] Step 5, growing an antiferroelectric layer 4: using TDMAZr (Zr[N(CH3)2]4), TMA (Al(CH3)3) and H2O as Zr, Al and oxygen sources respectively, depositing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4 by atomic layer deposition; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3, and the thickness of the antiferroelectric layer 4 is 10nm, wherein the thickness of ZrO2 is 9nm; the thickness of Al2O3 is 1nm;

[0078] Step 6, preparing the top electrode 5: using a shadow mask to evaporate a W thin film as the top electrode 5 on the antiferroelectric layer 4 generated in step 5 by electron beam, the thickness of the top electrode 5 is 100 nm;

[0079] Step 7, annealing: anneal the device obtained in step 6 at 400° C. and N 2 for 30 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

[0080] Compared with Example 1, this Example 2 adopts a ZrO2 / Al2O3 multilayer stacked structure 4 as the antiferroelectric layer 4, TiN as the bottom electrode 3, and metal W as the top electrode 5. The addition of the Al2O3 layer can further improve the breakdown voltage of the capacitor, thereby improving the performance of the capacitor.

[0081] Example 3

[0082] A novel zirconium-based deep trench structure energy storage capacitor comprises a deep trench structure silicon substrate 1, a SiO2 insulating layer 2, a bottom electrode 3, an antiferroelectric layer 4 and a top electrode 5 which are stacked in sequence from bottom to top.

[0083] The bottom electrode 3 and the top electrode 5 are both made of Pt.

[0084] The deep groove structure silicon substrate 1 is a deep groove structure with an aspect ratio of 50:1, and is located at the bottom layer of the capacitor; the SiO2 insulating layer 2 is a passivation layer attached to the surface of the deep groove structure silicon substrate 1, has a thickness of 300nm, and is located between the deep groove structure silicon substrate 1 and the bottom electrode 3; the bottom electrode 3 has a thickness of 200nm, and is located between the SiO2 insulating layer 2 and the antiferroelectric layer 4; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure, and the thickness of the antiferroelectric layer 4 is 20nm, wherein the thickness of ZrO2 is 18nm, and the thickness of Al2O3 is 2nm, and is located between the bottom electrode 3 and the top electrode 5; the top electrode 5 is located on the antiferroelectric layer 4, and the thickness of the top electrode 5 is 200nm, which is the top layer of the capacitor.

[0085] A method for preparing a novel zirconium-based deep trench structure energy storage capacitor comprises the following steps:

[0086] Step 1, cleaning the substrate: ultrasonically clean the planar silicon wafer in acetone, ethanol and deionized water for 10 minutes respectively to remove surface organic matter; then repeatedly clean it five times in a mixed solution of hydrofluoric acid: aqueous solution = 1:75 by volume to remove surface inorganic impurities, thereby obtaining a cleaned silicon substrate;

[0087] Step 2, etching the deep groove structure silicon substrate 1: spin-coat a layer of photoresist on the surface of the silicon substrate cleaned in step 1, then expose for 3 seconds, use this as a mask, and perform alternating reactive ion etching on the silicon substrate until the etching depth-to-width ratio is 50:1, thereby obtaining the deep groove structure silicon substrate 1;

[0088] Step 3, growing SiO2 insulating layer 2: using thermal oxidation method to oxidize a layer of SiO2 as an insulating layer on the surface of the deep groove structure silicon substrate 1 obtained in step 2, the oxidant is H2O and O2, the O2 flow rate is 50L / min, the H2O flow rate is 100L / min, the thermal oxidation time is 2h, and the insulating layer thickness is 300nm;

[0089] Step 4, growing the bottom electrode 3: using a platinum thin sheet as a target material and an air sputtering atmosphere, a Pt thin film is deposited on the surface of the SiO2 insulating layer 2 generated in step 3 as a bottom electrode, and the thickness of the bottom electrode 3 is 200 nm;

[0090] Step 5, growing an antiferroelectric layer 4: using TDMAZr (Zr[N(CH3)2]4), TMA (Al(CH3)3) and H2O as Zr, Al and oxygen sources respectively, depositing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4 by atomic layer deposition; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3, and the thickness of the antiferroelectric layer 4 is 20nm, wherein the thickness of ZrO2 is 18nm, and the thickness of Al2O3 is 2nm.

[0091] Step 6, preparing the top electrode 5: using a platinum thin sheet as a target material and an air sputtering atmosphere, a Pt thin film is deposited on the antiferroelectric layer 4 generated in step 5 as the top electrode 5, and the thickness of the top electrode 5 is 200 nm;

[0092] Step 7, annealing: anneal the device obtained in step 6 at 450° C. and H 2 for 60 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

[0093] This embodiment uses a ZrO2 / Al2O3 multilayer stacked structure as the antiferroelectric layer 4, and uses metal Pt as the bottom electrode 3 and the top electrode 5. Compared with Example 2, the depth-to-width ratio of the deep groove structure silicon substrate 1 is further increased, so that the effective area of ​​the capacitor is increased, thereby increasing the energy storage density of the capacitor.

[0094] Example 4

[0095] A novel zirconium-based deep trench structure energy storage capacitor comprises a deep trench structure silicon substrate 1, a SiO2 insulating layer 2, a bottom electrode 3, an antiferroelectric layer 4 and a top electrode 5 which are stacked in sequence from bottom to top.

[0096] The bottom electrode 3 is made of TiN, and the top electrode 5 is made of Al.

[0097] The deep groove structure silicon substrate 1 is a deep groove structure with an aspect ratio of 75:1, and is located at the bottom layer of the capacitor; the SiO2 insulating layer 2 is a passivation layer attached to the surface of the deep groove structure silicon substrate 1, with a thickness of 250nm, and is located between the deep groove structure silicon substrate 1 and the bottom electrode 3; the bottom electrode 3 has a thickness of 200nm, and is located between the SiO2 insulating layer 2 and the antiferroelectric layer 4; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure, and the thickness of the antiferroelectric layer 4 is 30nm, wherein the thickness of ZrO2 is 28nm, and the thickness of Al2O3 is 2nm, and is located between the bottom electrode 3 and the top electrode 5; the top electrode 5 is located on the antiferroelectric layer 4, and the thickness of the top electrode 5 is 150nm, which is the top layer of the capacitor.

[0098] A method for preparing a novel zirconium-based deep trench structure energy storage capacitor comprises the following steps:

[0099] Step 1, cleaning the substrate: ultrasonically clean the planar silicon wafer in acetone, ethanol and deionized water for 15 minutes respectively to remove surface organic matter; then repeatedly clean it three times in a mixed solution of hydrofluoric acid: aqueous solution = 1:50 by volume to remove surface inorganic impurities, thereby obtaining a cleaned silicon substrate;

[0100] Step 2, etching the deep groove structure silicon substrate 1: spin-coat a layer of photoresist on the surface of the silicon substrate cleaned in step 1, and then expose for 3 seconds, using this as a mask, and perform alternating reactive ion etching on the silicon substrate until the etching depth-to-width ratio is 75:1, thereby obtaining the deep groove structure silicon substrate 1;

[0101] Step 3, growing SiO2 insulating layer 2: using thermal oxidation method to oxidize a layer of SiO2 as an insulating layer on the surface of the deep groove structure silicon substrate 1 obtained in step 2, the oxidant is H2O and O2, the O2 flow rate is 50L / min, the H2O flow rate is 100L / min, the thermal oxidation time is 0.5h, and the insulating layer thickness is 250nm;

[0102] Step 4, growing bottom electrode 3: In a nitrogen and argon environment, solid Ti is used as the target material, 1.5×10 -7 Under a pressure of pa, a TiN bottom electrode is grown on the surface of the SiO2 insulating layer 2 formed in step 3, and the thickness of the TiN bottom electrode is 200nm;

[0103] Step 5, growing an antiferroelectric layer: using TDMAZr (Zr[N(CH3)2]4), TMA (Al(CH3)3) and H2O as Zr, Al and oxygen sources respectively, depositing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4 by atomic layer deposition; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3, and the thickness of the antiferroelectric layer 4 is 30nm, wherein the thickness of ZrO2 is 28nm, and the thickness of Al2O3 is 2nm;

[0104] Step 6, preparing the top electrode 5: using an aluminum sheet as a target material and the sputtering atmosphere as air, depositing an Al thin film as the top electrode 5 on the antiferroelectric layer 4 generated in step 5, the thickness of the top electrode 5 being 150 nm;

[0105] Step 7, annealing: anneal the device obtained in step 6 at 420° C. and N 2 for 50 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

[0106] This embodiment uses a ZrO2 / Al2O3 multilayer stacked structure as the antiferroelectric layer 4, TiN as the bottom electrode 3, and metal Al as the top electrode 5 to prepare an antiferroelectric capacitor with a structure of TiN / ZrO2 / Al2O3 / ZrO2 / Al2O3 / Al.

[0107] Example 5

[0108] A novel zirconium-based deep trench structure energy storage capacitor comprises a deep trench structure silicon substrate 1, a SiO2 insulating layer 2, a bottom electrode 3, an antiferroelectric layer 4 and a top electrode 5 which are stacked in sequence from bottom to top.

[0109] The bottom electrode 3 is made of TaN, and the top electrode 5 is made of Au.

[0110] The deep groove structure silicon substrate 1 is a deep groove structure with an aspect ratio of 100:1, and is located at the bottom layer of the capacitor; the SiO2 insulating layer 2 is a passivation layer attached to the surface of the deep groove structure silicon substrate 1, has a thickness of 300nm, and is located between the deep groove structure silicon substrate 1 and the bottom electrode 3; the bottom electrode 3 has a thickness of 200nm, and is located between the SiO2 insulating layer 2 and the antiferroelectric layer 4; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure, and the thickness of the antiferroelectric layer 4 is 50nm, wherein the thickness of ZrO2 is 47nm, and the thickness of Al2O3 is 3nm, and is located between the bottom electrode 3 and the top electrode 5; the top electrode 5 is located on the antiferroelectric layer 4, and the thickness of the top electrode 5 is 200nm, which is the top layer of the capacitor.

[0111] A method for preparing a novel zirconium-based deep trench structure energy storage capacitor comprises the following steps:

[0112] Step 1, cleaning the substrate: ultrasonically cleaning the planar silicon wafer in acetone, ethanol and deionized water for 15 minutes respectively to remove surface organic matter; then repeatedly cleaning it in a mixed solution of hydrofluoric acid: aqueous solution = 1:75 by volume for five times to remove surface inorganic impurities, thereby obtaining a cleaned silicon substrate;

[0113] Step 2, etching the deep groove structure silicon substrate 1: spin-coat a layer of photoresist on the surface of the silicon substrate cleaned in step 1, and then expose it for 3 seconds, using this as a mask to perform alternating reactive ion etching on the silicon substrate until the etching depth-to-width ratio is 100:1, thereby obtaining the deep groove structure silicon substrate 1;

[0114] Step 3, growing SiO2 insulating layer 2: using thermal oxidation method to oxidize a layer of SiO2 as an insulating layer on the surface of the deep groove structure silicon substrate 1 obtained in step 2, the oxidant is H2O and O2, the O2 flow rate is 50L / min, the H2O flow rate is 100L / min, the thermal oxidation time is 2h, and the insulating layer thickness is 300nm;

[0115] Step 4, growing the bottom electrode 3: in a nitrogen and argon environment, using solid Ta as the target, 1.5×10 -7 Under a pressure of 1.5 pa, a TaN bottom electrode is grown on the surface of the SiO2 insulating layer 2 formed in step 3, and the thickness of the TaN bottom electrode is 200 nm;

[0116] Step 5, growing an antiferroelectric layer 4: using TDMAZr (Zr[N(CH3)2]4), TMA (Al(CH3)3) and H2O as Zr, Al and oxygen sources respectively, depositing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4 by atomic layer deposition; the antiferroelectric layer 4 is a ZrO2 / Al2O3 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3, and the thickness of the antiferroelectric layer 4 is 50nm, wherein the thickness of ZrO2 is 47nm, and the thickness of Al2O3 is 3nm;

[0117] Step 6, preparing the top electrode 5: using a gold thin film as a target material and the sputtering atmosphere as air, sputtering an Au thin film on the antiferroelectric layer 4 generated in step 5 as the top electrode 5, the thickness of the top electrode 5 is 200 nm;

[0118] Step 7, annealing: anneal the device obtained in step 6 at 450° C. and N 2 for 60 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

[0119] This embodiment uses a ZrO2 / Al2O3 multilayer stacked structure as the antiferroelectric layer 4, TaN as the bottom electrode 3, and metal Pd as the top electrode 5. Compared with the above embodiments, the etching depth-to-width ratio of the deep trench structure silicon substrate 1 in this embodiment is the largest, which is 100:1, so that the sidewall area of ​​the capacitor is greatly increased, thereby maximizing the energy storage density of this embodiment; and the bandgap width of Al2O3 is relatively large, which further increases the breakdown voltage of the capacitor.

[0120] The antiferroelectric layer in the existing technical solution adopts a single ZrO2 layer, and the substrate mostly adopts a planar silicon structure. There is a large room for improvement in the above-mentioned energy storage density, breakdown field strength, etc.

[0121] First, due to the characteristics of traditional perovskite materials, the dielectric layer has energy storage properties only when the thickness is at the level of hundreds of nanometers, which cannot match the inevitable trend of continuous miniaturization of device size. The present invention adopts a stacked structure of zirconium oxide (ZrO2) and Al2O3 (or TiO2), and the antiferroelectric layer 4 has good antiferroelectric properties when the thickness is less than ten nanometers.

[0122] Second, the preparation process of perovskite materials is complicated and the temperature is high, which is not compatible with the integrated circuit process (CMOS process). The present invention uses a stacked material of antiferroelectric materials - ZrO2 and Al2O3 (or TiO2), which can be prepared using the mainstream preparation technology of gate insulation layer on the CMOS process line - atomic layer deposition (ALD);

[0123] Third, the Pb element contained in PbZrO3 will volatilize under high temperature conditions, which may have potential harm to the human body and the environment; the present invention adopts a stack of zirconium-based antiferroelectric materials ZrO2 and Al2O3 (or TiO2), which is a green and pollution-free material.

[0124] The key points and protection points of the present invention are:

[0125] (1) using a ZrO2 / Al2O3 multilayer stacking structure or a ZrO2 / TiO2 multilayer stacking structure as the antiferroelectric layer 4;

[0126] (2) The substrate used is a silicon deep trench structure.

[0127] The technical problems to be solved by the present invention are:

[0128] With the trend of miniaturization and on-chip integration of energy storage devices, dielectric capacitors have attracted people's attention with their advantages such as high power density and ultra-short charging time. Traditional dielectric materials including ceramics, polymers, glass and perovskite materials have been used in energy storage devices, but due to the limitations of the material's own characteristics, there are many disadvantages. First, traditional dielectric materials can only maintain their energy storage characteristics within a larger thickness range, which cannot match the trend of device size miniaturization. The present invention is based on the stacking of new zirconium-based antiferroelectric materials and Al2O3 (or TiO2), and has excellent energy storage performance at the nanometer level (~10nm); second, the preparation process is complicated, the temperature is high, and it is not compatible with the CMOS process. The present invention adopts a mature atomic layer deposition (ALD) process to prepare, which provides a guarantee for its application in advanced CMOS process nodes; third, since most traditional perovskite materials contain lead, which may cause potential harm to the human body and the environment, the present invention does not contain heavy metals and other toxic elements that may cause harm to the human body and the environment.

[0129] On the other hand, the existing antiferroelectric capacitors generally have the problem of relatively low energy storage density (ESD). The present invention adopts a deep-trench structure energy storage capacitor, which can increase the effective area of ​​the capacitor. At the same time, it combines a new zirconium-based antiferroelectric material, namely zirconium oxide ZrO2, so that the device exhibits excellent energy storage characteristics.

[0130] The application prospects of the present invention include:

[0131] (1) Medical field: The present invention can be integrated into medical equipment as an important power storage element in the medical equipment to store the required electrical energy. For example, magnetic resonance imaging (MRI) technology requires a large number of energy storage capacitors to support the generation of magnetic fields. The capacitors can store enough charge and release it to the magnetic resonance equipment to generate a strong magnetic field.

[0132] (2) Aviation: The present invention can be integrated into aerospace equipment to maintain the stable operation of the equipment. For example, energy storage capacitors can provide necessary energy for radars, electronic jammers and other equipment on aircraft; they can also be used together with inductors to eliminate electromagnetic interference and make the operation of electronic equipment more stable;

[0133] (3) Consumer electronic products: For portable electronic products such as mobile phones and tablet computers, the present invention has the advantages of small size, high reliability, fast charging and discharging speed, etc., and can better support the low-power operation state of the equipment.

Claims

1. A novel zirconium-based deep trench structure energy storage capacitor, characterized in that: The invention comprises a deep groove structure silicon substrate (1), a SiO2 insulating layer (2), a bottom electrode (3), an antiferroelectric layer (4) and a top electrode (5) which are stacked in sequence from bottom to top.

2. A novel zirconium-based deep trench structure energy storage capacitor according to claim 1, characterized in that: The bottom electrode (3) and the top electrode (5) are both made of at least one of TaN, Au, TiN, W, Mo, Pt, Pd, Al and Ru.

3. The novel zirconium-based deep trench structure energy storage capacitor according to claim 1 is characterized in that: The deep groove structure silicon substrate (1) is a deep groove structure with a depth-to-width ratio of (1-100):1, and is located at the bottom layer of the capacitor; the SiO2 insulating layer (2) is a passivation layer attached to the surface of the deep groove structure silicon substrate (1), has a thickness of 50-300nm, and is located between the deep groove structure silicon substrate (1) and the bottom electrode (3); the bottom electrode (3) has a thickness of 10nm-200nm, and is located between the SiO2 insulating layer (2) and the antiferroelectric layer (4); the antiferroelectric layer (4 ) is a ZrO2 / Al2O3 multilayer stacking structure or a ZrO2 / TiO2 multilayer stacking structure, the thickness of the antiferroelectric layer (4) is 6 to 50nm, wherein the thickness of ZrO2 is 5 to 47nm, the thickness of Al2O3 or TiO2 is 1 to 3nm, and it is located between the bottom electrode (3) and the top electrode (5); the top electrode (5) is located on the antiferroelectric layer (4), the thickness of the top electrode (5) is 10nm to 200nm, and it is the top layer of the capacitor.

4. A method for preparing a novel zirconium-based deep-groove structure energy storage capacitor, characterized in that: The following steps are involved: Step 1, cleaning the substrate: ultrasonically clean the planar silicon wafer in acetone, ethanol and deionized water for 5 to 15 minutes to remove surface organic matter; Repeatedly washing in a mixed solution of hydrofluoric acid: aqueous solution = 1: (25-75) according to a volume ratio to remove inorganic impurities on the surface, thereby obtaining a cleaned silicon substrate; Step 2, etching the deep groove structure silicon substrate (1): spin-coating a layer of photoresist on the surface of the silicon substrate cleaned in step 1, patterning the photoresist, and using the photoresist as a mask to etch the silicon substrate, with the etching depth-to-width ratio being (1-100):1, to obtain the deep groove structure silicon substrate (1); Step 3, growing a SiO2 insulating layer (2): using a thermal oxidation method to oxidize a layer of SiO2 as an insulating layer on the surface of the deep trench structure silicon substrate (1) obtained in step 2, the oxidant is H2O and O2, the H2O and O2 are in any ratio, the thermal oxidation time is 0.5 to 2 hours, and the thickness of the insulating layer is 50-300nm; Step 4, growing a bottom electrode (3): growing a bottom electrode (3) on the surface of the SiO2 insulating layer (2) generated in step 3; Step 5, growing an antiferroelectric layer (4): preparing an antiferroelectric layer (4) on the bottom electrode (3) generated in step 4; Step 6, preparing a top electrode (5): preparing a top electrode (5) on the antiferroelectric layer (4) formed in step 5; Step 7, annealing: anneal the device obtained in step 6 at 350-450° C. and N 2 or H 2 for 0.5 minute to 60 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

5. The method for preparing a novel zirconium-based deep trench structure energy storage capacitor according to claim 4, characterized in that: The bottom electrode (3) in step 4 and the top electrode (5) in step 6 are both prepared by one of the following methods: electron beam evaporation, chemical vapor deposition, ion beam sputtering, atomic layer deposition, magnetron sputtering, and pulsed laser deposition.

6. The method for preparing a novel zirconium-based deep trench structure energy storage capacitor according to claim 4, characterized in that: The step 5 grows the antiferroelectric layer (4), specifically by an atomic layer deposition method, the steps are: Using TDMAZr (Zr[N(CH3)2]4), TMA (Al(CH3)3) and H2O as Zr, Al and oxygen sources respectively, an antiferroelectric layer (4) is deposited on the bottom electrode (3) generated in step 4 by atomic layer deposition; the antiferroelectric layer (4) is a ZrO2 / Al2O3 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3, and the thickness of the antiferroelectric layer (4) is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of Al2O3 is 1 to 3 nm; Among them, ZrO2 / Al2O3 in atomic layer deposition can be replaced by ZrO2 / TiO2. The specific method is: using Zr[N(CH3)2]4, Ti[N(CH3)2]4 and H2O as Zr, Ti and oxygen sources respectively, by atomic layer deposition, an antiferroelectric layer (4) of a ZrO2 / TiO2 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of TiO2 is deposited on the bottom electrode (3) generated in step 4, and the thickness of the antiferroelectric layer (4) is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of TiO2 is 1 to 3 nm.

7. The method for preparing a novel zirconium-based deep trench structure energy storage capacitor according to claim 4, characterized in that: The step 5 grows the antiferroelectric layer (4), specifically by pulsed laser deposition method, the steps are: A pulsed laser deposition method is used to alternately deposit ZrO2 / TiO2 thin films, and an antiferroelectric layer (4) is deposited on the bottom electrode (3) generated in step 4; the antiferroelectric layer (4) is a ZrO2 / TiO2 multilayer stacked structure formed by alternately stacking multiple layers of ZrO2 and multiple layers of TiO2, and the thickness of the antiferroelectric layer (4) is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; and the thickness of TiO2 is 1 to 3 nm; Among them, ZrO2 / TiO2 in the pulse laser deposition method can be replaced by ZrO2 / Al2O3. The specific method is: using the pulse laser deposition method, alternately depositing ZrO2 / Al2O3 films, and depositing an antiferroelectric layer (4) of a ZrO2 / Al2O3 multilayer stacked structure formed by alternating multiple layers of ZrO2 and multiple layers of Al2O3 on the bottom electrode (3) generated in step 4, wherein the thickness of the antiferroelectric layer (4) is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of Al2O3 is 1 to 3 nm.

8. The method for preparing a novel zirconium-based deep trench structure energy storage capacitor according to claim 4, characterized in that: The step 5 grows the antiferroelectric layer (4), specifically by magnetron sputtering, the steps are: In an oxygen and argon environment, using solid Al and solid Zr as target materials, a ZrO2 / Al2O3 thin film is deposited to form an antiferroelectric layer (4) of a ZrO2 / Al2O3 multilayer stack structure in which multiple layers of ZrO2 and multiple layers of Al2O3 are alternately stacked on the bottom electrode (3) generated in step 4, wherein the thickness of the antiferroelectric layer (4) is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; and the thickness of Al2O3 is 1 to 3 nm; Among them, ZrO2 / Al2O3 prepared by magnetron sputtering can be replaced by ZrO2 / TiO2, and solid Ti and solid Zr are used as targets to deposit ZrO2 / TiO2 thin films, and an antiferroelectric layer (4) of a ZrO2 / TiO2 multilayer stacking structure in which multiple layers of ZrO2 and multiple layers of TiO2 are alternately stacked is formed on the bottom electrode (3) generated in step 4. The thickness of the antiferroelectric layer (4) is 6 to 50 nm, wherein the thickness of ZrO2 is 5 to 47 nm; the thickness of TiO2 is 1 to 3 nm.

9. A method for preparing a novel zirconium-based deep trench structure energy storage capacitor according to claim 6, 7 or 8, characterized in that: The ZrO2 in the ZrO2 / Al2O3 multilayer stacking structure or the ZrO2 / TiO2 multilayer stacking structure can be doped with Ti, Si, or Ti and Si elements.

10. The method for preparing a novel zirconium-based deep trench structure energy storage capacitor according to claim 4, characterized in that: The novel zirconium-based deep trench structure energy storage capacitor comprises a deep trench structure silicon substrate (1), a SiO2 insulating layer (2), a bottom electrode (3), an antiferroelectric layer (4) and a top electrode (5) stacked in sequence from bottom to top; the bottom electrode (3) and the top electrode (5) are made of TaN and Au respectively; the deep trench structure silicon substrate (1) is a deep trench structure with a depth-to-width ratio of 1:1 and is located at the bottom layer of the capacitor; the SiO2 insulating layer (2) is a passivation layer attached to the surface of the deep trench structure silicon substrate (1) and has a thickness of 50 nm and is located at the bottom of the deep trench structure silicon substrate (1). ) and a bottom electrode (3); the bottom electrode (3) has a thickness of 50 nm and is located between the SiO2 insulating layer (2) and the antiferroelectric layer (4); the antiferroelectric layer (4) is a ZrO2 / TiO2 multilayer stacked structure, the thickness of the antiferroelectric layer (4) is 6 nm, wherein the thickness of ZrO2 is 5 nm, the thickness of TiO2 is 1 nm, and the antiferroelectric layer (4) is located between the bottom electrode (3) and the top electrode (5); the top electrode (5) is located on the antiferroelectric layer (4), the thickness of the top electrode (5) is 50 nm, and it is the top layer of the capacitor; the preparation method thereof comprises the following steps: Step 1, cleaning the substrate: ultrasonically clean the planar silicon wafer in acetone, ethanol and deionized water for 5 minutes respectively to remove surface organic matter; then repeatedly clean it three times in a mixed solution of hydrofluoric acid: aqueous solution = 1:25 by volume to remove surface inorganic impurities, thereby obtaining a cleaned silicon substrate; Step 2, etching the deep groove structure silicon substrate 1: spin-coat a layer of photoresist on the surface of the silicon substrate cleaned in step 1, then expose for 3 seconds, use this as a mask, and perform alternating reactive ion etching on the silicon substrate until the etching depth-to-width ratio is 1:1, thereby obtaining the deep groove structure silicon substrate 1; Step 3, growing SiO2 insulating layer 2: adopting thermal oxidation method, oxidants are H2O and O2, O2 flow rate is 50L / min, H2O flow rate is 100L / min, thermal oxidation is performed for 0.5h, and a layer of SiO2 is oxidized on the surface of the deep groove structure silicon substrate 1 obtained in step 2 as an insulating layer, and the thickness of the insulating layer is 50nm; Step 4, growing bottom electrode 3: In a nitrogen and argon environment, solid Ta is used as the target material, 1×10 -7 Under a pressure of pa, a TaN bottom electrode is grown on the surface of the SiO2 insulating layer 2 formed in step 3, and the thickness of the TaN bottom electrode is 50nm; Step 5, growing an antiferroelectric layer 4: adopting an atomic layer deposition method, using TDMAZr (Zr [N (CH3) 2] 4), Ti [N (CH3) 2)] 4 and H2O as Zr, Ti and oxygen sources respectively, alternately depositing ZrO2 / TiO2 thin films, and depositing an antiferroelectric layer 4 on the bottom electrode 3 generated in step 4; the antiferroelectric layer 4 is a ZrO2 / TiO2 multilayer stacking structure formed by alternating multiple layers of ZrO2 and multiple layers of TiO2, and the thickness of the antiferroelectric layer is 6nm; wherein the thickness of ZrO2 is 5nm, and the thickness of TiO2 is 1nm; Step 6, preparing the top electrode 5: using a gold thin film as a target material and an air sputtering atmosphere, depositing an Au thin film as the top electrode 5 on the antiferroelectric layer 4 generated in step 5, the thickness of the top electrode 5 being 50 nm; Step 7, annealing: anneal the device obtained in step 6 at 350° C. and N 2 for 30 minutes to obtain a zirconium-based deep trench structure energy storage capacitor.

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