Method for reducing random cracks in III-nitride semiconductor bond wafers

Abstract

The present disclosure provides a method for reducing random cracks in a III-nitride semiconductor bonded wafer, comprising: obtaining a III-nitride semiconductor wafer and a first substrate, with a second substrate disposed on one side of the III-nitride semiconductor wafer; dividing the III-nitride semiconductor wafer into a plurality of III-nitride semiconductor wafer microregions to obtain a divided III-nitride semiconductor layer; bonding the divided III-nitride semiconductor layer to the first substrate to obtain a processed III-nitride semiconductor bonded wafer; and removing the second substrate from the processed III-nitride semiconductor bonded wafer to obtain a III-nitride semiconductor bonded wafer. The present disclosure divides and then bonds the III-nitride semiconductor wafer, thereby reducing random cracks in the III-nitride semiconductor bonded wafer and improving the performance of the III-nitride semiconductor bonded wafer.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor materials and devices, and in particular to a method for reducing random cracks in a III-nitride semiconductor bonding wafer and a III-nitride semiconductor bonding wafer. Background Art

[0002] Group III nitride semiconductors are a new type of semiconductor material that has received considerable international attention in recent years. Their superior properties, including continuously variable direct band gaps, excellent physical and chemical stability, high saturated electron mobility, high breakdown field strength, and high thermal conductivity, make them an optimal material for short-wavelength semiconductor optoelectronic devices and high-frequency, high-voltage, high-temperature, and high-power electronic devices.

[0003] Currently, adhesives are commonly used to bond III-nitride semiconductors to substrates. However, stress release after bonding, coupled with thermal stress introduced by the large thermal expansion difference between the adhesive and the III-nitride semiconductor, can lead to the formation of random microcracks in thin III-nitride semiconductor layers. These microcracks can hinder carrier transport, create leakage paths, degrade III-nitride semiconductor device performance, and limit device fabrication process size. Summary of the Invention

[0004] In view of the above problems, embodiments of the present disclosure provide a method for reducing random cracks in a Group III nitride semiconductor bonding wafer and a Group III nitride semiconductor bonding wafer.

[0005] One aspect of the present disclosure provides a method for reducing random cracks in a III-nitride semiconductor bonding wafer, comprising: obtaining a III-nitride semiconductor wafer and a first substrate, with a second substrate provided on one side of the III-nitride semiconductor wafer; segmenting the III-nitride semiconductor wafer to divide the III-nitride semiconductor wafer into a plurality of III-nitride semiconductor wafer micro-regions to obtain a segmented III-nitride semiconductor layer; bonding the segmented III-nitride semiconductor layer to the first substrate to obtain a III-nitride semiconductor bonding wafer to be processed; and removing the second substrate from the III-nitride semiconductor bonding wafer to obtain a III-nitride semiconductor bonding wafer.

[0006] According to an embodiment of the present disclosure, obtaining a Group III nitride semiconductor wafer and a first substrate includes: obtaining a Group III nitride semiconductor wafer having a thickness of less than or equal to 1 μm.

[0007] According to an embodiment of the present disclosure, the III-nitride semiconductor wafer includes a GaN wafer, an AlN wafer, an InGaN wafer, and an AlGaN wafer.

[0008] According to an embodiment of the present disclosure, dividing the III-nitride semiconductor wafer includes: opening a plurality of grooves along a first direction that penetrate the III-nitride semiconductor wafer on a side of the III-nitride semiconductor wafer away from the second substrate to obtain a divided III-nitride semiconductor layer, wherein the first direction is the overlapping direction of the second substrate and the III-nitride semiconductor wafer.

[0009] According to an embodiment of the present disclosure, the groove extends along at least one of the second direction, the third direction and the fourth direction, and the second direction, the third direction and the fourth direction intersect with each other; the size of the micro-region of the III-nitride semiconductor wafer is determined by the extension direction of the groove, the width of the groove and the spacing between two adjacent parallel grooves; the shape of the micro-region includes a rectangle, a triangle, a parallelogram and a hexagon.

[0010] According to an embodiment of the present disclosure, the extending direction of the groove is aligned with the direction of the III-nitride semiconductor wafer. The crystal directions are approximately parallel, and the term "approximately parallel" means that the angle between the two directions is less than or equal to 5°.

[0011] According to an embodiment of the present disclosure, the depth of the groove is greater than or equal to the thickness of the III-nitride semiconductor wafer; the width of the groove is 10 nm to 1 mm; the multiple grooves are parallel to each other, and the spacing between adjacent grooves is 10 nm to 5 mm; the extension length of the groove is 10 nm to 300 mm.

[0012] According to an embodiment of the present disclosure, a groove penetrating the III-nitride semiconductor wafer is formed on a side of the III-nitride semiconductor wafer away from the second substrate to obtain a segmented III-nitride semiconductor layer, including: performing photolithography on a side of the III-nitride semiconductor wafer away from the second substrate to obtain a mask corresponding to the groove; and dry-etching the III-nitride semiconductor wafer based on the mask to obtain the segmented III-nitride semiconductor layer.

[0013] According to an embodiment of the present disclosure, bonding the segmented III-nitride semiconductor layer to the first substrate includes: applying glue between the segmented III-nitride semiconductor layer and the first substrate, and performing glue spreading on the segmented III-nitride semiconductor layer and the first substrate after the glue is spread by a glue spreader, wherein the rotation speed of the glue spreader is 500 r / min to 5000 r / min.

[0014] Another aspect of the present disclosure provides a Group III nitride semiconductor bonding wafer, which is manufactured using the method for reducing random cracks in a Group III nitride semiconductor bonding wafer according to any embodiment of the present disclosure.

[0015] According to the embodiments of the present disclosure, by dividing the III-nitride semiconductor wafer, the thermal stress generated by the III-nitride semiconductor wafer during the bonding process can be effectively released, so that the thermal stress accumulated in each micro-region on the divided III-nitride semiconductor wafer is not sufficient to cause the III-nitride semiconductor in the micro-region to disconnect, thereby reducing or even avoiding the generation of random microcracks in the III-nitride semiconductor bonding wafer, and improving the performance and practical utilization value of the III-nitride semiconductor bonding wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 Schematically showing the effect of a method for bonding a Group III nitride semiconductor wafer according to the related art;

[0018] Figure 2 A flowchart schematically illustrates the steps of a method for reducing random cracks in a Group III nitride semiconductor bonding wafer according to an embodiment of the present disclosure;

[0019] Figure 3 A diagram schematically illustrates structural changes corresponding to a method for reducing random cracks in a Group III nitride semiconductor bonding wafer according to an embodiment of the present disclosure;

[0020] Figure 4 Schematically shows the size and shape of a micro-region of a Group III nitride semiconductor wafer according to an embodiment of the present disclosure;

[0021] Figure 5 The effect diagram of adopting different groove opening methods according to the comparative examples related to the present disclosure is schematically shown.

[0022] [Description of Reference Numerals]

[0023] 101-crack; 102-microcrack; 301-III-nitride semiconductor wafer; 3011-III-nitride semiconductor layer; 3012-III-nitride semiconductor wafer microregion; 3013-groove; 302-first substrate; 303-second substrate; 304-III-nitride semiconductor bonding wafer to be processed; 305-III-nitride semiconductor bonding wafer. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0025] It should be noted that in the drawings or descriptions of the specification, similar or identical parts use the same figure numbers. The technical features in the various embodiments exemplified in the specification can be freely combined to form new solutions without conflict. In addition, each claim can be used as an embodiment alone or the technical features in each claim can be combined as a new embodiment. In the drawings, the shape or thickness of the embodiment can be expanded and simplified or conveniently indicated. Furthermore, the elements or implementations not shown or described in the drawings are forms known to ordinary technicians in the relevant technical field. In addition, although this article may provide demonstrations of parameters containing specific values, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint.

[0026] Unless there are technical obstacles or contradictions, the above-mentioned various embodiments of the present disclosure can be freely combined to form additional embodiments, and these additional embodiments are all within the protection scope of the present disclosure.

[0027] Although the present disclosure is described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to illustrate preferred embodiments of the present disclosure and are not to be construed as limiting the present disclosure. The dimensional ratios in the drawings are merely illustrative and are not to be construed as limiting the present disclosure.

[0028] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

[0029] Figure 1 The diagram schematically shows the effect of a method for bonding group III nitride semiconductor wafers according to the related art.

[0030] When bonding III-nitride semiconductor wafers, due to the stress release after bonding and the thermal stress introduced by the large thermal expansion difference between the glue used in bonding and the III-nitride semiconductor, the combined effect of the two can easily form random microcracks on thinner III-nitride semiconductor bonding wafers. Figure 1 As shown, Figure 1 (a) is a 2 cm × 2 cm III-nitride semiconductor bonded wafer with many cracks visible to the naked eye. Observed under a microscope, Figure 1As shown in (b), in addition to visible cracks 101, this bonded sample also exhibits numerous random microcracks 102. These random microcracks can hinder carrier transport, create leakage paths, degrade GaN device performance, and limit device process size. This demonstrates that the related art presents a microcrack formation problem when bonding III-nitride semiconductor wafers, and these random microcracks negatively impact the performance of bonded III-nitride semiconductor wafers.

[0031] Figure 2 The flowchart schematically shows the steps of a method for reducing random cracks in a III-nitride semiconductor bonding wafer according to an embodiment of the present disclosure. Figure 3 The diagram schematically shows the structural changes corresponding to the method for reducing random cracks in a III-nitride semiconductor bonding wafer according to an embodiment of the present disclosure.

[0032] According to the embodiments of the present disclosure, Figure 2 and Figure 3 As shown, the present disclosure provides a method for reducing random cracks in a III-nitride semiconductor bond wafer, for example, including operations S210 to S240.

[0033] In operation S210 , a III-nitride semiconductor wafer 301 and a first substrate 302 are obtained, and a second substrate 303 is provided on one side of the III-nitride semiconductor wafer 301 .

[0034] In some embodiments, the obtained III-nitride semiconductor wafer 301 can be of any shape, such as a square, polygon, or more specifically, a wafer. The obtained first substrate 302 is typically a single crystal silicon wafer or an epitaxial silicon wafer with a device layer, or a glass substrate. The second substrate 303 is typically made of sapphire or silicon; in addition, the second substrate 303 can also be made of the same material as the III-nitride semiconductor wafer 301, serving as an epitaxial substrate for the III-nitride semiconductor wafer 301. More specifically, a body layer of a certain thickness on a III-nitride single crystal wafer can be regarded as the III-nitride semiconductor wafer 301, and the remaining portion except the body layer can be regarded as the second substrate 303.

[0035] It is understandable that the first substrate 302 and the second substrate 303 are selected according to specific application scenarios.

[0036] In operation S220 , the III-nitride semiconductor wafer 301 is segmented to divide the III-nitride semiconductor wafer 301 into a plurality of III-nitride semiconductor wafer micro-regions 3012 to obtain segmented III-nitride semiconductor layers 3011 .

[0037] In some embodiments, the obtained III-nitride semiconductor wafer 301 is first segmented, for example, using a photolithography process combined with a dry etching process. This segmentation operation divides the surface of the III-nitride semiconductor wafer 301 into a plurality of III-nitride semiconductor wafer micro-regions 3012. A single III-nitride semiconductor wafer micro-region 3012 can have a variety of shapes, and the size of a single III-nitride semiconductor wafer micro-region 3012 can also be segmented into different sizes as needed. This results in a segmented III-nitride semiconductor layer 3011 composed of the plurality of III-nitride semiconductor wafer micro-regions 3012. This III-nitride semiconductor layer 3011 is subsequently bonded to the first substrate 302. Using the segmented III-nitride semiconductor layer 3011 for bonding can reduce the number of random cracks generated in the III-nitride semiconductor wafer micro-regions 3012 during the bonding process.

[0038] In operation S230 , the divided III-nitride semiconductor layer 3011 is bonded to the first substrate 302 to obtain a to-be-processed III-nitride semiconductor bonded wafer 304 .

[0039] In some embodiments, to increase the adhesion strength between the glue and the Group III nitride semiconductor wafer 301 and the first substrate 302, an adhesion promoter may be applied to the surfaces of the segmented Group III nitride semiconductor layer 3011 and the first substrate 302. After the adhesion promoter is baked, the glue is spread between the segmented Group III nitride semiconductor layer 3011 and the first substrate 302, and the glue is then thermally cured.

[0040] For example, after the glue is applied, the separated III-nitride semiconductor layer 3011 and the first substrate 302 are placed on a hot plate at 115°C, kept at this temperature for 2 minutes, and then heated to 150°C at a heating rate of 3°C / min, and then kept at this temperature for 10 minutes to thermally cure the glue.

[0041] Optionally, the heat curing temperature in the embodiment of the present disclosure can be adjusted accordingly between 80° C. and 150° C. as needed; the heat curing time in the embodiment of the present disclosure can be adjusted accordingly between 1 min and 30 mins as needed.

[0042] In addition, the temperature can be gradually increased or decreased as needed to achieve thermal curing. The purpose of thermal curing is to remove part of the solvent in the glue to solidify the glue layer and prepare for subsequent bonding.

[0043] After the glue is thermally cured, the separated III-nitride semiconductor layer 3011 and the first substrate 302, coated with glue, are aligned and placed in a bonding machine for bonding. The bonding temperature is set, for example, to 300°C, the bonding machine pressure is set, for example, to 2000 N, and the bonding time is set, for example, to 60 minutes, to obtain a processed III-nitride semiconductor bonded wafer 304. After bonding, the III-nitride semiconductor layer 3011 should remain on the first substrate 302. The term "processed" in the processed III-nitride semiconductor bonded wafer 304 refers to the need to remove the second substrate 303 attached to the bonded wafer.

[0044] Optionally, the bonding temperature in the embodiment of the present disclosure can be adjusted between 200°C and 350°C as needed; the bonding machine pressure in the embodiment of the present disclosure can be adjusted between 1000 N and 5000 N as needed; the bonding time in the embodiment of the present disclosure can be adjusted between 30 mins and 180 mins as needed.

[0045] In some embodiments, before bonding the divided III-nitride semiconductor layer 3011 to the first substrate 302 , a cleaning step is further included to prevent contaminants on the bonding surface from affecting the bonding strength.

[0046] For example, a solution of sulfuric acid: hydrogen peroxide (H2O2) in a ratio of 4:1 is used to clean the separated Group III nitride semiconductor layer 3011 and the first substrate 302. The solution is prepared in the appropriate proportions and heated to 130°C. The separated Group III nitride semiconductor layer 3011 and the first substrate 302 are then placed in the solution for 30 minutes. After cleaning for 30 minutes, the separated Group III nitride semiconductor layer 3011 and the first substrate 302 are removed and rinsed 20 times with deionized water. The mixture is then blown dry using a nitrogen gun.

[0047] In operation S240 , the second substrate 303 in the to-be-processed III-nitride semiconductor bonded wafer 304 is removed to obtain a III-nitride semiconductor bonded wafer 305 .

[0048] In some embodiments, for example, the second substrate 303 is mechanically thinned by mechanical grinding, and a second substrate with a thickness of 30 to 50 μm is retained after grinding and thinning. Then, dry etching or wet etching with a high selectivity is used to remove the remaining second substrate 303 to obtain a III-nitride semiconductor bonding wafer 305.

[0049] As an optional embodiment, when a second substrate made of the same material as the III-nitride semiconductor wafer is used, light ion implantation can be performed on the second substrate 303 before bonding. The light ions can be hydrogen ions and / or helium ions, and the implantation dose is generally selected from 2 e 16 cm -2 to 2 e 17 cm -2 After the bonding is completed, the hydrogen ions and / or helium ions are heat treated to form a bubble layer cake for ripening and cross-linking, and finally the second substrate 303 is peeled off to obtain the III-nitride semiconductor bonding sheet 305.

[0050] It should be noted that, at this time, the III-nitride semiconductor bonding wafer 305 may further include a buffer layer of the second substrate 303 , and the buffer layer can be removed by dry etching to expose the complete III-nitride semiconductor layer 3011 .

[0051] The III-nitride semiconductor bonding wafer 305 may be in any shape, such as a square or a polygon, and more particularly, may be a wafer.

[0052] By dividing and bonding the III-nitride semiconductor wafers through the above-mentioned operations, the thermal stress generated by the III-nitride semiconductor wafers during the bonding process can be effectively released, so that the thermal stress accumulated in each micro-region on the divided III-nitride semiconductor wafer is not sufficient to disconnect the III-nitride semiconductor in the micro-region, thereby reducing or even avoiding the generation of random microcracks in the III-nitride semiconductor bonding wafer, thereby improving the performance and practical utilization value of the III-nitride semiconductor bonding wafer.

[0053] According to an embodiment of the present disclosure, obtaining the III-nitride semiconductor wafer 301 and the first substrate 302 includes: obtaining the III-nitride semiconductor wafer 301 having a thickness less than or equal to 1 μm.

[0054] For Group III nitride semiconductor wafers 301 with a thickness of 1 μm or less, random microcracks are easily formed on their surfaces during the bonding process. However, the method of the disclosed embodiment can reduce random microcracks on the Group III nitride semiconductor bonding wafer and is therefore suitable for bonding Group III nitride semiconductor wafers 301 with a thickness of 1 μm or less.

[0055] In some embodiments, a Group III nitride semiconductor wafer layer with a thickness of 1 μm or less on a Group III nitride semiconductor single wafer can be used as the Group III nitride semiconductor wafer 301. Alternatively, a Group III nitride semiconductor epitaxial layer with a thickness of 1 μm or less on a Group III nitride semiconductor wafer epitaxial wafer can be used as the Group III nitride semiconductor wafer 301. The portion of the Group III nitride semiconductor single wafer excluding the Group III nitride semiconductor layer after segmentation serves as the second substrate 303. The Group III nitride semiconductor epitaxial wafer typically uses sapphire, silicon, or silicon carbide as the second substrate 303. More specifically, the second substrate 303 can be made of the same material as the Group III nitride semiconductor wafer, forming a homogeneous epitaxial wafer.

[0056] The obtained III-nitride semiconductor wafer 301 with a thickness of less than or equal to 1 μm is more likely to generate cracks during the bonding process compared to other III-nitride semiconductor wafers 301 with a thicker thickness. Bonding them using the method in the embodiment of the present disclosure can significantly reduce the generation of random cracks in the thinner III-nitride semiconductor wafer 301 during the bonding process.

[0057] According to an embodiment of the present disclosure, the III-nitride semiconductor wafer 301 includes, for example, a GaN wafer, an AlN wafer, an InGaN wafer, and an AlGaN wafer. GaN, AlN, InGaN, and AlGaN have the same crystal structure, and their crystals are perpendicular to the It is more fragile in the direction of the crystal direction, so it is easy to crack under the action of tensile stress, forming During the thermal bonding process, due to the thermal mismatch between the III-nitride semiconductor wafer 301 and the glue, a large number of random microcracks are likely to appear in the bonding layer after bonding.

[0058] The method in the embodiment of the present disclosure can reduce random cracks generated during the bonding process of different types of III-nitride semiconductor wafers 301 .

[0059] According to an embodiment of the present disclosure, dividing the III-nitride semiconductor wafer 301 includes, for example: opening a plurality of grooves along a first direction that penetrate the III-nitride semiconductor wafer on a side of the III-nitride semiconductor wafer away from the second substrate to obtain a divided III-nitride semiconductor layer, where the first direction is the overlapping direction of the second substrate and the III-nitride semiconductor wafer.

[0060] In some embodiments, photoresist is first applied to the surface of the III-nitride semiconductor wafer 301, and then the photoresist is photolithographically processed to distribute the designed grooves 3013 onto the photoresist, and then photolithographic development is performed to remove the photoresist corresponding to the grooves. The developed photoresist layer is then hardened, and then the hardened photoresist is used as a mask to perform dry etching along the overlapping direction of the second substrate and the III-nitride semiconductor wafer to remove the epitaxial layer and buffer layer corresponding to the grooves, so as to segment the III-nitride semiconductor wafer 301, thereby obtaining a plurality of grooves 3013 penetrating the III-nitride semiconductor wafer 301 and the segmented III-nitride semiconductor layer 3011.

[0061] By providing a plurality of grooves penetrating the III-nitride semiconductor wafer 301, the surface of the III-nitride semiconductor wafer 301 is divided into the III-nitride semiconductor layer 3011. Compared to the III-nitride semiconductor wafer 301, the III-nitride semiconductor layer 3011 separated by the grooves 3013 can release more thermal stress during bonding, thereby reducing the generation of random cracks in the III-nitride semiconductor layer 3011.

[0062] According to an embodiment of the present disclosure, the groove 3013 extends along at least one of the second direction, the third direction and the fourth direction; the size of the III-nitride semiconductor wafer micro-region 3012 is determined by the extension direction of the groove 3013, the width of the groove 3013 and the spacing between two adjacent parallel grooves 3013; the shape of the micro-region includes a rectangle, a triangle, a parallelogram and a hexagon.

[0063] The III-nitride semiconductor wafer 301 has an in-plane There are 6 crystal directions, which correspond to the perpendicular lines of each side of a regular hexagon in the plane. They can be divided into three groups, with two crystal directions in each group collinear and opposite to each other.

[0064] In some embodiments, the three extending directions of the groove 3013 correspond to, for example, the three extending directions of the III-nitride semiconductor wafer 301 and the three extending directions of the groove 3013. The three sets of crystal orientations. The size of a single III-nitride semiconductor micro-region 3012 can be determined by the direction in which the grooves 3013 extend, the width of the grooves 3013, and the spacing between two adjacent parallel grooves 3013. The shape of a single III-nitride semiconductor micro-region 3012 can also be determined by selecting the number of directions in which the grooves 3013 extend.

[0065] It should be noted that the III-nitride semiconductor wafer micro-regions 3012 refer to the individual III-nitride semiconductor units separated by the grooves 3013 on the surface of the III-nitride semiconductor wafer 301 after the III-nitride semiconductor wafer 301 is divided.

[0066] Figure 4 The diagram schematically shows the size and shape of a micro-region of a Group III nitride semiconductor wafer according to an embodiment of the present disclosure. Figure 4 a~f correspond to the following Examples A~F respectively.

[0067] Example A

[0068] For example, Figure 4 As shown, the grooves are arranged as a set of grooves roughly parallel to the III-nitride semiconductor sheet. The parallel lines of the crystal direction are rectangular, and the space between two adjacent parallel lines is a rectangular III-nitride semiconductor wafer micro-region. The groove width is 5 μm, the distance between two adjacent parallel lines is 100 μm, and the groove extension length is 4 cm. The size of the obtained single III-nitride semiconductor wafer micro-region 3012 is 4x10 -2 cm 2 .

[0069] Example B

[0070] For example, Figure 4 As shown, the grooves are arranged as a set of grooves roughly parallel to the III-nitride semiconductor sheet. The parallel lines of the crystal direction are rectangular, and the space between two adjacent parallel lines is a rectangular III-nitride semiconductor wafer micro-region. The groove width is 10 μm, the distance between two adjacent parallel lines is 90 μm, and the groove extension length is 4 cm. The size of the obtained single III-nitride semiconductor wafer micro-region 3012 is 3.6x10 -2 cm 2 .

[0071] It can be seen from Examples A and B that the size of a single III-nitride semiconductor micro-region 3012 can be determined by controlling the extension direction and width of the groove 3013 and the distance between two adjacent parallel grooves 3013 .

[0072] Example C

[0073] For example, Figure 4 As shown, the grooves are arranged as a group of grooves substantially parallel to the III-nitride semiconductor wafer 301. The parallel lines are parallel to the crystal direction, and between two adjacent parallel lines is a rectangular III-nitride semiconductor wafer micro-region 3012. The width of the groove is 10 μm, the distance between two adjacent parallel lines is 200 μm, and the groove extends for 2 cm.

[0074] Example D

[0075] For example, Figure 4 As shown, the grooves are arranged in two groups, both of which are roughly parallel to the III-nitride semiconductor wafer 301. The two sets of parallel lines have an angle of 60° between them, and divide the III-nitride semiconductor wafer 301 into periodic parallelogram-shaped III-nitride semiconductor wafer micro-regions 3012. The width of the groove is 10 μm. In the two sets of parallel lines, the distance between two adjacent parallel lines is 500 μm. Therefore, the III-nitride semiconductor wafer micro-regions 3012 in this embodiment are diamond-shaped, and the extension length of the groove is 1.2 cm.

[0076] Example E

[0077] For example, Figure 4 As shown, the grooves are arranged to be substantially parallel to the III-nitride semiconductor wafer 301. The line segments in the three directions of the crystal orientation have an angle of 60° between the non-parallel line groups, the width of the groove is 10 μm, and the length of the line segment is 500 μm. These three line segments can divide the III-nitride semiconductor wafer 301 into periodic hexagonal III-nitride semiconductor wafer micro-regions 3012.

[0078] Example F

[0079] For example, Figure 4 As shown, the grooves 3013 are arranged to be substantially parallel to the edges of the III-nitride semiconductor wafer 301. Three groups of parallel lines in the crystal direction are formed, and the angle between the three groups of parallel lines is 60°. The third group of parallel lines passes through the intersection of the first and second groups of parallel lines. The three groups of parallel lines divide the III-nitride semiconductor wafer 301 into periodic triangular III-nitride semiconductor wafer micro-regions 3012. The width of the groove is 10 μm. In the three groups of parallel lines, the distance between two adjacent parallel lines is 500 μm. Therefore, the III-nitride semiconductor wafer micro-regions 3012 in this embodiment can be equilateral triangles of uniform size, and the extension length of the groove is 1.2 cm.

[0080] It can be seen from Examples C to F that the shape of the micro-region 3012 of a single III-nitride semiconductor wafer can be determined by controlling the number of extension directions of the groove 3013 . Figure 4 Microscopic photographs of the GaN bonding wafers of Examples A to F are provided, which clearly show that in each of the above embodiments, no random microcracks are generated in the III-nitride semiconductor wafer micro-region 3012 of the III-nitride semiconductor wafer 301 .

[0081] It is understandable that the width of the groove, the spacing between adjacent grooves and the extension length of the groove in the embodiment of the present disclosure are not limited to the dimensions in the above embodiment and can be adjusted accordingly as needed.

[0082] By adjusting the extension direction of the groove 3013, the width of the groove 3013 and the distance between two adjacent parallel grooves 3013 in this embodiment, the size and shape of the III-nitride semiconductor wafer micro-region 3012 can be designed to minimize the generation of random cracks.

[0083] According to an embodiment of the present disclosure, the extending direction of the groove 3013 is aligned with the direction of the III-nitride semiconductor wafer 301. The crystal directions are approximately parallel, and the term "approximately parallel" means that the angle between the two directions is less than or equal to 5°.

[0084] In the above embodiments A to F, the extending direction of the groove 3013 is aligned with the direction of the III-nitride semiconductor wafer 301. The above-mentioned approximately parallel means that the extension direction of the groove 3013 can be parallel to the crystal direction of the III-nitride semiconductor wafer 301. The crystal direction is at a certain angle, which is less than 5°, and more preferably, less than 2°. The smaller the angle between the crystal directions, the closer the groove 3013 is to the III-nitride semiconductor wafer 301. The closer the crystal directions are, the more conducive it is to stress release.

[0085] In order to highlight the unique effect of the disclosed method on the groove extension direction, the following comparative examples with different extension directions are used for further explanation.

[0086] Figure 5 The effect diagram of adopting different groove opening methods according to the comparative examples related to the present disclosure is schematically shown.

[0087] Figure 5 Wherein a~b correspond to the above embodiment C to form comparative example A, c corresponds to the above embodiment C to form comparative example B, and d corresponds to the above embodiment F to form comparative example C.

[0088] Comparative Example A

[0089] For example, Figure 5 As shown, the grooves are arranged as a group of grooves perpendicular to the III-nitride semiconductor bonding sheet. Parallel lines of crystal orientation, a and b are the effect diagrams of different regions, where the white arrows point to the III-nitride semiconductor bonding wafers respectively The groove width is 10 μm, and the distance between adjacent parallel lines is 200 μm. As can be seen in Figures a and b, although the number of random cracks has been reduced to some extent, a large number of random cracks are still distributed within the rectangular III-nitride semiconductor wafer microregion.

[0090] Comparative Example B

[0091] For example, Figure 5 As shown, the groove is set as a group of III-nitride semiconductor bonding pieces Parallel lines with a 30° crystal orientation angle, with the white arrow pointing to the III-nitride semiconductor bond pad In one direction of the crystal orientation, the groove width is 10 μm, and the distance between two adjacent parallel lines is 200 μm. As can be seen from Figure c, in this embodiment, a large number of random cracks are distributed in the rectangular III-nitride semiconductor wafer micro-region.

[0092] Comparative Example C

[0093] For example, Figure 5 As shown, d is a hole parallel to the III-nitride semiconductor bonding sheet. Images of the edges of the grooves in the crystal orientation, where the white arrows point to the III-nitride semiconductor bond wafers. It can be clearly seen that no random cracks are generated in the area where grooves are opened, while a certain amount of random cracks appear in the area without grooves.

[0094] It can be seen from the above embodiments that along the III-nitride semiconductor wafer There is no crack in the area where the groove 3033 is opened in the crystal direction, and there is no crack along the III-nitride semiconductor bonding sheet. There are still a lot of cracks in the area where the grooves 3033 are opened and the area where the grooves are not opened. The method of opening grooves in the crystal direction can effectively reduce the generation of random cracks on the III-nitride semiconductor bonding wafer 305 during the subsequent bonding process, while the effect of opening grooves along other directions in removing random cracks is not obvious or even has no effect.

[0095] According to an embodiment of the present disclosure, the depth of the groove is greater than or equal to the thickness of the III-nitride semiconductor wafer 301; the width of the groove is 10 nm to 1 mm; the multiple grooves are parallel to each other, and the spacing between adjacent grooves is 10 nm to 5 mm; the extension length of the groove is 10 nm to 300 mm.

[0096] In some embodiments, the depth of the groove may be greater than the thickness of the III-nitride semiconductor wafer 301 , but should be less than the thickness of the entire III-nitride semiconductor wafer 301 and the second substrate 303 .

[0097] For example, a groove with a depth of 500.5 μm is opened on a III-nitride semiconductor wafer provided with a second substrate 303 with a thickness of 500 μm (the thickness of the III-nitride semiconductor wafer is 0.8 μm).

[0098] It is understandable that the depth of the groove 3013 can be selected according to actual needs, but the depth of the groove 3013 should be less than or equal to the overall thickness of the III-nitride semiconductor wafer 301 and the second substrate 303 .

[0099] In some embodiments, the width of the groove, the spacing between adjacent grooves, and the extension length of the groove can all be selected as needed.

[0100] For example, to produce a micro circular III-nitride semiconductor bonding wafer with a diameter of 100 nm, the width of the groove can be set to 10 nm, the spacing between adjacent grooves can be set to 10 nm, and the extension length of the groove can be set to 100 nm.

[0101] For another example, a III-nitride semiconductor bonding wafer is made using a square III-nitride semiconductor wafer with a length of 1 cm and a width of 1 cm. The width of the groove can be set to 0.5 mm, the spacing between adjacent grooves can be set to 1 mm, and the extension length of the groove can be set to 1 cm.

[0102] For another example, if a whole 12-inch wafer is used to make a III-nitride semiconductor bonding wafer, the width of the groove can be set to 1 mm, the spacing between adjacent grooves can be set to 5 mm, and the extension length of the groove can be set to 300 mm.

[0103] It is understandable that the width of the groove, the spacing between adjacent grooves and the extension length of the groove in the embodiment of the present disclosure are not limited to the dimensions in the above embodiment and can be adjusted accordingly as needed.

[0104] For example, the width of the groove can be 1 μm, 5 μm, 10 μm, etc.; the spacing between adjacent grooves can be 10 μm, 100 μm, 200 μm, 500 μm, etc.; the extended length of the groove can be 500 μm, 2 cm, 5 cm, etc.

[0105] By adjusting the extension direction of the groove 3013, the width of the groove 3013, and the spacing between two adjacent parallel grooves 3013 in this embodiment, multiple grooves 3013 of different sizes can be opened on the III-nitride semiconductor wafer 301 to meet the different requirements of the grooves 3013 of different pairs of III-nitride semiconductor wafers 301, thereby reducing the generation of random cracks during the subsequent bonding process.

[0106] According to an embodiment of the present disclosure, a groove penetrating the III-nitride semiconductor wafer is formed on a side of the III-nitride semiconductor wafer away from the second substrate to obtain the segmented III-nitride semiconductor layer, comprising: performing photolithography on a side of the III-nitride semiconductor wafer away from the second substrate to obtain a mask corresponding to the groove; and dry-etching the III-nitride semiconductor wafer based on the mask to obtain the segmented III-nitride semiconductor layer.

[0107] In this embodiment, the groove 3033 can be opened by a method of photolithography combined with dry etching. The purpose of the above-mentioned photolithography process is to provide an etching mask for dry etching of the III-nitride semiconductor wafer.

[0108] The III-nitride semiconductor wafer 301 used in this embodiment is a GaN-on-silicon epitaxial wafer, comprising, from the second substrate 303 upwards, a 780 μm Si substrate, a 200 nm AlN buffer layer, and a 500 nm GaN epitaxial layer. The first substrate 302 is, for example, a 525 μm thermally oxidized silicon wafer, comprising a 525 μm silicon wafer and 500 nm of thermally oxidized SiO2 on each side.

[0109] In this embodiment, the grooves may be formed by a method of photolithography combined with dry etching, and the detailed steps are as follows:

[0110] First, the silicon-based GaN epitaxial wafer is coated with a tackifier, usually by vapor coating in an oven. After the tackifier coating is completed, a photoresist is spread using a spreader, for example, the spreader speed is 3000 r / min and the spreader time is 60s. Then, photolithography development is performed to remove the photoresist corresponding to the groove. During photolithography, it is necessary to keep the linear openings corresponding to the grooves on the photolithography mask aligned with the silicon-based GaN epitaxial wafer. The crystal directions are placed as parallel as possible.

[0111] Then, the GaN epitaxial wafer on silicon after photolithography development is placed on a hot plate at, for example, 95° C., and heated to 150° C. at a heating rate of 3° C. / min, and then kept at this temperature for 30 minutes to harden the film.

[0112] Finally, using the hardened photoresist as a mask, the silicon-based GaN epitaxial wafer with the hardened photoresist is dry-etched to remove the 500 nm GaN epitaxial layer and the 200 nm AlN buffer layer at the position corresponding to the groove 3013.

[0113] In some embodiments, when a thicker III-nitride semiconductor layer 3011 is desired, SiO2, Si3N4, Al2O3, or the like can be used as a mask layer. In this case, a mask layer of SiO2, Si3N4, Al2O3, or the like is first deposited to an appropriate thickness on the bonding surface 3031 of the III-nitride semiconductor wafer 301. The appropriate thickness is determined by the thickness of the III-nitride semiconductor wafer 301 and the etching rate ratio. The mask layer thickness should ensure that the mask layer remains after etching of the III-nitride semiconductor layer 3011 is complete.

[0114] Then, a photoresist is coated on the mask layer and a photolithography process is performed. The photoresist is used as a mask for etching the deposited SiO2, Si3N4 or Al2O3 layer, and the pattern corresponding to the groove 3013 is transferred to the SiO2, Si3N4 or Al2O3 layer, that is, a groove corresponding to the required groove 3013 is etched on the SiO2, Si3N4 or Al2O3 layer.

[0115] Finally, the photoresist on the SiO2, Si3N4 or Al2O3 layer is removed, and the III-nitride semiconductor wafer 301 covered with the mask layer is dry-etched using the SiO2, Si3N4 or Al2O3 layer as an etching mask to obtain a groove 3013.

[0116] By combining the photolithography process with the dry etching process in the embodiment of the present disclosure, it is possible to ensure accurate replication of the pattern of the groove 3013 , thereby improving the accuracy and reliability of the fabricated III-nitride semiconductor device.

[0117] According to an embodiment of the present disclosure, bonding the segmented III-nitride semiconductor layer 3011 to the first substrate 302 includes: applying glue between the segmented III-nitride semiconductor layer 3011 and the first substrate 302; and performing glue spreading on the segmented III-nitride semiconductor layer 3011 and the first substrate 302 after the glue is spread by a glue spreader, and the rotation speed of the glue spreader is 500 r / min to 5000 r / min.

[0118] For example, the separated group III nitride semiconductor layer 3011 can be bonded using the following glues: benzocyclobutene (BCB), SU-8, PDMS, and polymethyl methacrylate (PMMA).

[0119] In some embodiments, for example, BCB glue is used as the polymer. BCB glue has very strong chemical bonds, is resistant to various acids and solvents, can withstand temperatures above 200 degrees, and is suitable for permanent bonding.

[0120] In some embodiments, the glue spreading operation can be completed using a glue spreading machine. The speed of the glue spreading machine can be selected according to the thickness of the required glue layer. The faster the speed, the thicker the glue layer can be obtained.

[0121] However, some applications require a layer thickness as low as tens of nanometers. Simply increasing the spin coater speed is insufficient to achieve this thickness. In such cases, solvent can be added to the glue before spin coating to dilute it. The appropriate dilution ratio is selected based on the desired thickness. The solvent used is generally the same as the original solvent.

[0122] The method in the embodiment of the present disclosure can control the thickness of the adhesive layer during the bonding process. During operation, the optimal adhesive layer thickness can be selected according to actual needs, thereby minimizing the generation of random cracks in the III-nitride semiconductor wafer 301 during the bonding process.

[0123] Another aspect of the present disclosure provides a Group III nitride semiconductor bonding wafer, which is manufactured using the method for reducing random cracks in a Group III nitride semiconductor bonding wafer according to any embodiment of the present disclosure.

[0124] In some embodiments, the III-nitride semiconductor bonding wafer produced by the method of reducing random cracks in the III-nitride semiconductor bonding wafer disclosed herein has fewer cracks and higher performance than the III-nitride semiconductor bonding wafer produced by the prior art. For example, it can be used to prepare high-temperature, high-frequency, and high-power devices, and is widely used in satellite communications, radar warning, lighting displays and other fields.

[0125] For example, a GaN bonding wafer produced using the disclosed method for reducing random cracks in a III-nitride semiconductor bonding wafer is used to prepare high-temperature, high-power GaN devices by utilizing its advantages such as high thermal conductivity and high saturated electron drift velocity.

[0126] The details not included in the product embodiment section are similar to those in the method embodiment section. Please refer to the method embodiment section and will not be repeated here.

[0127] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in an exemplary order and are not intended to be limited to a specific order or hierarchy.

[0128] It should also be noted that directional terms such as "upper," "lower," "front," "back," "left," and "right" mentioned in the embodiments are merely references to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations that may cause confusion in understanding this disclosure will be omitted. Furthermore, the shapes, sizes, and positional relationships of the components in the drawings do not reflect their actual sizes, proportions, or actual positional relationships.

[0129] In the foregoing detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that embodiments of the claimed subject matter require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the disclosure comprises less than all features of any individual disclosed embodiment. The appended claims are therefore hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the disclosure.

[0130] In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. With respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", as explained in terms of "including" used as a transitional word in the claims. Any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

[0131] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for reducing random cracks in a Group III nitride semiconductor bonding wafer, characterized in that: include: Obtaining a Group III nitride semiconductor wafer and a first substrate, wherein a second substrate is disposed on one side of the Group III nitride semiconductor wafer; Slicing the Group III nitride semiconductor wafer to divide the Group III nitride semiconductor wafer into a plurality of Group III nitride semiconductor wafer micro-regions to obtain a segmented Group III nitride semiconductor layer; Bonding the divided III-nitride semiconductor layer to the first substrate to obtain a III-nitride semiconductor bonded wafer to be processed; removing the second substrate from the to-be-processed Group III nitride semiconductor bonding wafer to obtain a Group III nitride semiconductor bonding wafer; Wherein, dividing the III-nitride semiconductor wafer comprises: A plurality of grooves are formed on a side of the III-nitride semiconductor wafer away from the second substrate, and are passed through the III-nitride semiconductor wafer along a first direction to obtain the divided III-nitride semiconductor layer, wherein the first direction is a superimposed direction of the second substrate and the III-nitride semiconductor wafer; The groove extends along at least one of the second direction, the third direction, and the fourth direction, and the extending direction of the groove is parallel to the direction of the Group III nitride semiconductor wafer. The crystal directions are approximately parallel, and the term "approximately parallel" means that the angle between the two directions is less than or equal to 5°.

2. The method according to claim 1, characterized in that The obtaining of the Group III nitride semiconductor wafer and the first substrate comprises: The III-nitride semiconductor wafer having a thickness of less than or equal to 1 μm is obtained.

3. The method according to claim 1, characterized in that The III-nitride semiconductor wafer includes: a GaN wafer, an AlN wafer, an InGaN wafer or an AlGaN wafer.

4. The method according to claim 1, wherein The size of the micro-region of the III-nitride semiconductor sheet is determined by the extension direction of the groove, the width of the groove and the distance between two adjacent parallel grooves; The shape of the micro-domain includes rectangle, triangle, parallelogram or hexagon.

5. The method according to claim 1, wherein The depth of the groove is greater than or equal to the thickness of the III-nitride semiconductor wafer; The width of the groove is 10 nm to 1 mm; The plurality of grooves are parallel to each other, and the spacing between adjacent grooves is 10 nm to 5 mm; The groove has an extension length of 10 nm to 300 mm.

6. The method according to claim 1, characterized in that The step of forming a groove penetrating the Group III nitride semiconductor wafer on a side of the Group III nitride semiconductor wafer away from the second substrate to obtain the divided Group III nitride semiconductor layer comprises: performing photolithography on a side of the III-nitride semiconductor wafer away from the second substrate to obtain a mask corresponding to the groove; The III-nitride semiconductor wafer is dry-etched based on the mask to obtain the divided III-nitride semiconductor layer.

7. The method according to claim 1, characterized in that The bonding the divided group III nitride semiconductor layer to the first substrate comprises: applying glue between the divided group III nitride semiconductor layer and the first substrate; The group III nitride semiconductor layer after being divided and coated with the glue and the first substrate are subjected to glue-coating by a glue-coating machine, wherein the rotation speed of the glue-coating machine is 500 r / min to 5000 r / min.

8. A group III nitride semiconductor bonding wafer, characterized in that: Prepared by the method according to any one of claims 1 to 7.

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