High conductivity transistor contact including gallium-rich layer

Abstract

The invention relates to a highly conductive transistor contact including a gallium-rich layer. In some embodiments, an apparatus may include a substrate having silicon. In addition, the device may include a first layer of a source or drain region of the p-type transistor, the first layer over the substrate, the first layer having boron, silicon, and germanium. The device may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Further, the device may include a third layer between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.

Description

Technical Field

[0001] The present disclosure relates to highly conductive transistor contacts including a gallium-rich layer. Background Art

[0002] Contact resistance (e.g., at the interface between the source material and the source contact metal and between the drain material and the drain contact metal) plays a key role in transistor applications. This resistance directly affects the performance of the transistor and determines the maximum clock frequency achievable in devices utilizing these transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A is a perspective view of an example planar field effect transistor (FET) including a gate, a source region, and a drain region.

[0004] Figure 1B is a cross-sectional view of a planar FET taken along the source contact region of the transistor.

[0005] Figure 2A is a perspective view of an example FinFET including a gate, a source region, a drain region, and a fin.

[0006] Figure 2B is a cross-sectional view of an example FinFET taken along the source region.

[0007] Figure 2C A cross section of a variation of a FinFET is shown in which the source contact metal is located only on a portion of the outer surface of the source semiconductor layer.

[0008] Figure 3A is a perspective view of a gate-all-around FET (GAAFET) including a gate, a source region, a drain region, and a semiconductor layer.

[0009] Figure 3B is a cross-sectional view of a GAAFET taken along the source contact region.

[0010] Figure 3C A cross-section of one form of GAAFET is shown, in which the width and thickness of the semiconductor layers are similar.

[0011] Figure 4A It is a perspective view of a stacked GAAFET.

[0012] Figure 4B is a cross-sectional view of an example stacked GAAFET taken along the source contact region.

[0013] Figure 4C A cross-section of one form of GAAFET is shown, in which the width and thickness of the semiconductor layers are similar.

[0014] Figure 5 A portion of an example integrated circuit is shown.

[0015] Figure 6 A portion of an example P-type metal oxide semiconductor (PMOS) source / drain region is shown.

[0016] Figure 7 Secondary ion mass spectrometry (SIMS) profiles of different source / drain compositions are shown.

[0017] Figure 8 An example method for forming a highly conductive p-type transistor contact comprising a gallium-rich layer adjacent to a boron-doped silicon germanium epitaxial film is shown.

[0018] Fig. 9 Schematic diagrams of cross-sectional views of example integrated circuit devices are provided.

[0019] Fig.10 is a top view of an example wafer and die that may be included in a microelectronic assembly.

[0020] Fig.11 is a cross-sectional side view of an example integrated circuit device.

[0021] Figures 12A-12D is a simplified perspective view of an example planar transistor, FinFET, gate-all-around transistor, and stacked gate-all-around transistor.

[0022] Fig.13 is a cross-sectional side view of an example integrated circuit device assembly.

[0023] Fig.14 is a block diagram of an example electrical device. DETAILED DESCRIPTION

[0024] As transistors scale to smaller sizes, maintaining a suitable contact resistivity for the source / drain (where “source / drain” may refer to either or both of the source or drain of a transistor) becomes a challenge. For example, less than 1E-09 ohm-cm may be desired. 2 The contact resistivity can be reduced to achieve proper operation. The contact resistivity can be reduced by reducing the Schottky barrier height (SBH) between the contact metal and the silicide formed on the edge of the source / drain material (for example, by increasing the germanium concentration in a portion of the source / drain to 60-80% in a source / drain comprising boron-doped silicon germanium (B:SiGe)). The silicide can be formed with boron-doped silicon germanium, where the boron is added during epitaxial deposition and / or using boron-11 implantation. The contact resistivity can also be reduced by increasing the electroactive boron concentration in a portion of the source / drain to 2E21 atoms / cm 3(e.g., by utilizing non-equilibrium low temperature B:SiGe epitaxial deposition) to reduce the contact resistivity. However, such techniques may not be sufficient to reduce the contact resistivity to a desired level (e.g., such techniques may only reduce the resistivity to ~1.5E-9 ohm-cm in some architectures). 2 ). Therefore, when a single active dopant (e.g., boron) is present at the source / drain silicide interface, the contact resistivity may be limited.

[0025] In various embodiments, the contact resistivity of the PMOS source / drain is reduced by adding a gallium-rich layer between the source / drain material (e.g., boron-doped silicon germanium) and the source / drain contact metal (e.g., at the silicide interface of the source / drain). In various embodiments of the present disclosure, the epitaxially grown B:SiGe of the source / drain is exposed in situ to a metal organic precursor containing gallium. For example, the precursor may include triethylgallium or trimethylgallium. In various embodiments, gallium may be present at 5E19 to 5E20 atoms / cm in the gallium-rich layer (e.g., at the top or other outer surface of the B:SiGe, such as within the first five nanometers of depth of the surface or within the first two monolayers of the layer). 3 The addition of gallium will increase the total carrier concentration (e.g., the total carrier concentration of boron and gallium atoms) at the contact surface of the source / drain (e.g., where the source / drain material is coupled to the contact metal), thereby reducing the contact resistivity (e.g., in some embodiments, to less than 1E-9 ohm-cm 2 ).

[0026] Figure 1A 1 is a perspective view of an example planar field effect transistor (FET) 100 including a gate 102, a source region 104, and a drain region 106. The planar FET 100 is formed on a substrate 116, which includes a surface 108, a bulk region 118, and an isolation region 114 that separates the source region 104 and the drain region 106 from other transistors. A gallium-rich layer 119 is located between the source region 104 and the source contact metal 117 ( Figure 1B The gallium-rich layer 121 is located between the drain region 106 and the drain contact metal (not shown). The planar FET 100 is planar because the source region 104 and the drain region 106 are planar relative to the surface 108 of the substrate 116. Figure 1B 1 is a cross-sectional view 140 of the planar FET 100 taken along the source contact region of the planar FET 100. The cross-sectional view 140 shows the source contact metal 117 located above the source region 104, with the gallium-rich layer 119 located between the source contact metal 117 and the source region 104. The source region 104 extends from the surface 108 of the substrate 116 to a depth 122 within the substrate 116.

[0027] Figure 2A is a perspective view of an example FinFET 220 including a gate 222 , a source region 235 , a drain region 237 , and a fin 230 . Figure 2B 2 is a cross-sectional view of an example FinFET 200 taken along a source region 235. The FinFET 220 is formed on a substrate 216, which includes a surface 208, a bulk region 218, and an isolation region 214 that separates a source region 235 and a drain region 237 from other transistors. The fin 230 extends from the surface 208 of the substrate 216 and extends along a length 231 from a first end 232 of the fin 230 to a second end 234 of the fin 230. The gate 222 controls the flow of current from a source portion 224 of the fin 230 to a drain portion 226 of the fin 230. The channel region of the FinFET 220 is formed by the portion of the fin 230 surrounded by the gate 222.

[0028] The source region 235 includes the source portion 224 of the fin 230 and the source semiconductor layer 225 ( Figure 2A 20 (not shown), the source semiconductor layer 225 is positioned adjacent to and surrounds at least a portion of the length 231 of the fin 230 (e.g., the source portion 224 of the fin 230). The source semiconductor layer 225 includes one or more outer surfaces 239 (surfaces of the source semiconductor layer 225 that are not positioned adjacent to the surface 208 of the substrate 216). The source contact metal 217 is located on at least a portion of the outer surface 239 along at least a portion of the length of the source semiconductor layer 225. The gallium-rich layer 219 is located between the source semiconductor layer 225 and the source contact metal 217. The length 231 of the fin 230 and the length of the source semiconductor layer 225 extend in the same direction parallel to the surface 208 of the substrate 216.

[0029] The drain region 237 includes the drain portion 226 of the fin 230 and a drain semiconductor layer (not shown) that is positioned adjacent to and surrounds at least a portion of the length 231 of the fin 230 (the drain portion of the fin 230). Similar to the source semiconductor layer, the drain semiconductor layer includes one or more outer surfaces that are not positioned adjacent to the surface 208 of the substrate 216. The drain contact layer ( Figure 2A The drain semiconductor layer 220 is not shown in the figure. The gallium-rich layer (not shown) is located on at least a portion of the outer surface of the drain semiconductor layer along at least a portion of the length of the drain semiconductor region. The gallium-rich layer (not shown) is located between the drain semiconductor layer and the drain contact metal. The length 231 of the fin 230 and the length of the drain semiconductor layer extend in the same direction parallel to the surface 208 of the substrate 216. The drain semiconductor layer, the drain contact metal, and the gallium-rich layer between the drain contact layer and the drain contact metal of the FinFET 220 are not located in the figure. Figure 2A-2C, but are similar to their shown source counterparts (source semiconductor layer 225, source contact metal 217, gallium-rich layer 219).

[0030] FinFET 220 is non-planar because fin 230 extends from surface 208 of substrate 216. Since gate 222 surrounds three sides of fin 230, FinFET 220 can be considered a tri-gate transistor. Figure 2A One fin is shown extending through the gate 222 , but in other embodiments, multiple fins may extend through the gate of the FinFET transistor.

[0031] Figure 2B 2 is a cross-sectional view of an example FinFET 200 taken along the source region 235. The cross section 240 shows the source contact metal 217 located around the source semiconductor layer 225, and the gallium-rich layer 219 is located between the source contact metal 217 and the source semiconductor layer 225. Figure 2B As shown, source contact metal 217 surrounds outer surface 239. In such an embodiment, the contact may be referred to as a wrap-around contact.

[0032] Figure 2C A cross section 250 of a variation of FinFET 220 is shown in which source contact metal 217 is located only over a portion of outer surfaces 239 of source semiconductor layer 225. In cross section 250, source contact metal 217 is located substantially over the upper outer surfaces (e.g., only two outer surfaces 239) of source semiconductor layer 225, and gallium-rich layer 219 is located only adjacent to the outer surfaces where source contact metal 217 is located. Figure 2C The extent of the gallium-rich layer 219 shown in is shown as being substantially aligned with the extent of the source contact metal 217, but in other embodiments, the gallium-rich layer 219 may extend further than the extent of the source contact metal 217 in the non-surround contact. For example, in some embodiments, Figure 2C The gallium-rich layer 219 may surround all outer surfaces 239 of the source semiconductor layer 225, such as Figure 2B shown.

[0033] Although the source semiconductor layer 225 is Figure 2B-2C In the embodiment shown in FIG. 1 , the source and drain semiconductor layers in the FinFET contact are shown to have a pentagonal cross-sectional shape, but the shapes of the source and drain semiconductor layers in the FinFET contact are not limited thereto. In other embodiments, the cross-sectional shapes of the source and drain semiconductor regions in the FinFET contact may have the same cross-sectional shape as FIG. Figure 2B-2C The shapes shown in the figure are different shapes.

[0034] Figure 3A3 is a perspective view of a gate-all-around FET (GAAFET) 340 including a gate 342, a source region 335, a drain region 337, and a semiconductor layer 330. The GAAFET 340 is formed on a substrate 316, which includes a surface 308, a bulk region 318, and an isolation region 314. The semiconductor layer 330 is located above and separated from the substrate 316 and is substantially parallel to the surface 308 of the substrate 316. The semiconductor layer 330 extends from a first end 332 of the semiconductor layer 330 to a second end 334 of the semiconductor layer. The gate 342 controls the flow of current through a channel region from a source portion 344 of the semiconductor layer 330 to a drain portion 346 of the semiconductor layer 330. The channel region is created by the gate 342 surrounding a portion of the semiconductor layer 330.

[0035] The source region 335 includes the source portion 344 of the semiconductor layer 330 and the source semiconductor layer 325 ( Figure 3A ), the source semiconductor layer 325 is positioned adjacent to and surrounds at least a portion of the length 331 of the semiconductor layer 330 (the source portion 344 of the semiconductor layer 300). Figure 3A The gallium-rich layer 319 (not shown) surrounds the source semiconductor layer 325 along at least a portion of the length of the source semiconductor layer 325. The gallium-rich layer 319 is located between the source semiconductor layer 325 and the source contact metal 317. The length 331 of the semiconductor layer 330 and the length of the source semiconductor layer 325 extend in the same direction parallel to the surface 308 of the substrate 316.

[0036] The drain region 337 includes a drain portion 346 of the semiconductor layer 330 and a drain semiconductor layer positioned adjacent to and surrounding at least a portion of the length 331 of the semiconductor layer 330 (the drain portion 346 of the semiconductor layer 300). The drain contact metal surrounds the drain semiconductor layer along at least a portion of the length of the drain semiconductor layer. The gallium-rich layer is located between the drain semiconductor layer and the drain contact metal. The drain semiconductor layer, the drain contact metal, and the gallium-rich layer between the drain semiconductor layer and the drain contact metal of the GAAFET 340 are not in contact with each other. Figures 3A-3C , but are similar to their shown source counterparts (source semiconductor layer 325, source contact metal 317, gallium-rich layer 319).

[0037] A source isolation region 338 is located between source contact metal 317 and substrate 316 to isolate source contact metal 317 from substrate 316, and a drain isolation region (not shown) is located between drain contact metal and substrate 316 to isolate drain contact metal from the substrate.

[0038] GAAFET 340 is non-planar because semiconductor layer 330 is located above and separated from substrate 316. Because gate 342 surrounds all four sides of semiconductor layer 330 along a portion of length 331 of semiconductor layer 330, GAAFET 340 is considered a gate-all-around transistor. Figure 3B is a cross-sectional view of a GAAFET 340 taken along the source contact region. Cross section 350 shows the gallium-rich layer 319 between the source contact metal 317 and the source semiconductor layer 325.

[0039] GAAFET 340 may alternatively be referred to as a nanowire or nanoribbon transistor, depending on the width 348 of semiconductor layer 330 extending through gate 342 relative to the thickness of semiconductor layer 330. Figure 3B The width 348 of the semiconductor layer 330 in FIG. 3 is greater than the thickness of the semiconductor layer 330 , so the GAAFET 340 can be called a nanowire transistor. Figure 3C A cross section 360 of one form of GAAFET 340 is shown, where the width and thickness of semiconductor layer 330 are similar. Thus, the form of GAAFET 340 having cross section 360 may be referred to as a nanowire transistor.

[0040] Although the source semiconductor layer 325 is Figure 3A-3B , but the shapes of the source and drain semiconductor layers in the GAAFET contact are not limited thereto. In other embodiments, the cross-sections of the source and drain region semiconductor layers in the GAAFET contact may have the same cross-sectional shape as Figure 3B-3C The shapes shown in the figure are different shapes.

[0041] Figure 4A is a perspective view of a stacked GAAFET 440. The stacked GAAFET 440 is similar to Figure 3A The stacked GAAFET 440 is formed on a substrate 416, which includes a surface 408, a bulk region 418, and an isolation region 414. The stacked GAAFET 440 includes a gate 462, a source region 435, and a drain region 437, and a plurality of semiconductor layers 430. Each semiconductor layer 430 is substantially parallel to the surface 408 of the substrate 416, and extends along a length 431 from a first end 432 of each semiconductor layer 430 to a second end 434 of each semiconductor layer 430. The semiconductor layers 430 are stacked vertically relative to the surface 408 of the substrate 416. The gate 442 controls the flow of current from a source portion 464 of the semiconductor layer 430 to a drain portion 466 of the semiconductor layer 430 through a plurality of channel regions. The channel region is formed by the gate 442 surrounding a portion of the semiconductor layer 430.

[0042] The source region 435 includes a source portion 464 of the semiconductor layer 430, and the source semiconductor layer 425 is positioned adjacent to and surrounds at least a portion of the length 431 of each semiconductor layer 430 (the source portion 464 of the semiconductor layer 430). The source contact metal 417 surrounds the source semiconductor layer 425 along at least a portion of the length of the source semiconductor layer 425. The gallium-rich layer 419 is located between the source semiconductor layer 425 and the source contact metal 417. The length 431 of the semiconductor layer 430 and the length of the source semiconductor layer 425 extend in the same direction parallel to the surface 408 of the substrate 416.

[0043] The drain region 437 includes a drain portion 466 of the semiconductor layer 430, and the drain semiconductor layer is positioned adjacent to and surrounds at least a portion of the length 431 of each semiconductor layer 430 (the drain portion 466 of the semiconductor layer 430). The drain contact metal surrounds the drain semiconductor layer along at least a portion of the length of the drain semiconductor layer. The gallium-rich layer is located between the drain semiconductor layer and the drain contact metal. The drain semiconductor layer, the drain contact metal, and the gallium-rich layer between the drain contact layer and the drain contact metal of the stacked GAAFET 440 are not Figure 4A 4, but similar to their source counterparts shown (source semiconductor layer 425, source contact metal 417, gallium-rich layer 419). The length 431 of semiconductor layer 430 and the length of the drain semiconductor layer extend in the same direction parallel to the surface 408 of substrate 416.

[0044] Figure 4B is a cross-sectional view of an example stacked GAAFET 440 taken along the source contact region. The cross section 450 shows the gallium-rich layer 419 between the source contact metal 417 and the source semiconductor layer 425. Figure 4C A cross section 460 of a form of GAAFET 440 is shown, where the width (eg, width 468) and thickness of semiconductor layer 430 are similar. Thus, the form of GAAFET 440 having cross section 460 may be referred to as a nanowire transistor.

[0045] Although the source semiconductor layer 425 is Figure 4B-4C , but the shapes of the source and drain semiconductor regions in the stacked GAAFET are not limited thereto. In other embodiments, the cross-sectional shapes of the source and drain semiconductor layers in the stacked GAAFET may have the same cross-sectional shapes as Figure 4B-4C The shapes shown in the figure are different shapes.

[0046] Figure 5A portion of an example integrated circuit 500 is shown. Integrated circuit 500 represents an alternative FinFET architecture and includes p-channel metal oxide semiconductor (PMOS) source / drain regions 502 and n-channel metal oxide semiconductor (NMOS) source / drain regions 504 on a substrate 512.

[0047] The various characteristics described below in conjunction with the source / drain semiconductor layer 506 and the gallium-rich layer 519 may apply to the other source / drain semiconductor layers and gallium-rich layers described above or to such layers in alternative architectures.

[0048] Source / drain region 502 includes source / drain semiconductor layer 506 coupled to sub-fins 508A and 508B. Sub-fins 508 may include the same material as the substrate (eg, semiconductor material such as silicon). Sub-fins 508 may be separated from each other by a dielectric such as isolation oxide 510.

[0049] The source / drain semiconductor layer 506 of the source / drain region 502 may be formed by depositing a source / drain material (e.g., boron-doped silicon germanium) (e.g., within a trench formed in an insulating oxide). In various embodiments, the source / drain semiconductor layer 506 may be epitaxially grown using any suitable deposition process (e.g., chemical vapor deposition).

[0050] In some embodiments, a thin additional layer (e.g., 10-20 nanometers thick) of boron-doped silicon germanium is then epitaxially deposited on the outer (e.g., top) surface of the source / drain semiconductor layer 506. In various embodiments, the boron is not provided by implantation, but is doped in situ. Thus, the source / drain semiconductor layer 506 can include B-11 and B-10 isotopes (epitaxially deposited Ge:B produces B-11 and B-10 isotopes, while germanium implanted with boron produces only B-11 isotopes and no appreciable B-10 isotopes). In various embodiments, the boron-doped silicon germanium can be deposited at a relatively low temperature, for example, in the range of 350 to 475 degrees Celsius (e.g., at approximately 375 degrees Celsius). This temperature can be lower than the temperature used to form the source / drain semiconductor layer 506.

[0051] This deposition may result in a large amount of electrically active boron (e.g., more than 2E21 atoms / cm2) at the surface of the source / drain region 502 that will interface with the source / drain contact metal. 3 ), thus resulting in a reduction in the Schottky barrier height. The amount of chemically added boron can be higher than the amount of electroactive boron (e.g., up to 3E21 atoms / cm 3), because it can include the total amount of boron incorporated into the silicon germanium lattice, including boron incorporated into substitutional lattice sites, interstitial sites, clustered, etc., while only boron present at substitutional sites of the silicon germanium lattice is electrically active.

[0052] In various embodiments, the thin layer (e.g., which corresponds to the gallium-rich layer 519) can have a higher germanium concentration (e.g., 60-80 atomic percent) than the source-drain semiconductor layer 506 (e.g., 45-55 atomic percent). The higher germanium concentration can reduce the SBH, resulting in a lower contact resistivity. The higher germanium concentration can also facilitate increasing the concentration of electrically active boron incorporated in the thin layer (an important property at the source / drain surface), thereby improving resistivity.

[0053] The formation of the thin layer may result in the formation of an interface between the thin layer and the source / drain semiconductor layer 506. The interface may include some trace contaminants (e.g., one or more of oxygen, carbon, fluorine, chlorine, or other contaminants). The interface may additionally or alternatively also include some interruptions in the lattice continuity.

[0054] In various embodiments, the thin layer can be grown with high selectivity. For example, the film of the thin layer is grown only on the source / drain semiconductor layer 506, and not on dielectric surfaces (e.g., including oxides, nitrides, oxynitrides, etc.), such as spacers, hard masks, isolation regions, etc. In order to achieve this selectivity, the precursor chemical can be different from the precursor chemical used to form the source / drain semiconductor layer 506. In various embodiments, germanium tetrachloride is used as a precursor during the formation of the thin layer, and / or (gas phase) hydrogen chloride is used as a precursor during the formation of the source / drain semiconductor layer 506. In some embodiments, the precursor (e.g., hydrogen chloride) for the source / drain semiconductor layer 506 will not be effective at the reduced temperature used during the formation of the thin layer. In various embodiments, different pressures can also be used to form the thin layer relative to the pressure used to form the source / drain semiconductor layer 506.

[0055] In some embodiments, gallium may be added as part of the growth of the thin layer to form gallium-rich layer 519 (e.g., a gas including gallium may be included in a flow of other materials applied during formation of the thin layer). In other embodiments, gallium may be applied in situ to the thin layer after the thin layer is formed to form gallium-rich layer 519.

[0056] In various embodiments, the newly formed thin layer is treated with a precursor including gallium (e.g., triethylgallium, trimethylgallium, or other gas including gallium) for a period of time (e.g., an amount of time between 10 seconds and 10 minutes, and in one embodiment about 2 minutes) to form a gallium-rich layer 519. Gallium can be applied, for example, at a temperature between 375 and 500 degrees Celsius. In one embodiment, gallium is applied at approximately 450 degrees Celsius. In various embodiments, gallium is applied using non-directional chemical vapor deposition (CVD) (or other suitable deposition techniques).

[0057] Application of the precursor results in the incorporation of gallium into the top few monolayers of the thin layer, thereby forming a gallium-rich layer 519. For example, gallium may be included in the top monolayer or the top two monolayers, and the monolayers of the source / drain region 502 below the top two monolayers may not include an appreciable amount of gallium (or at least the monolayers below the top two monolayers may include much less gallium than within the top two monolayers). For example, any monolayer below the top two monolayers may include less than 5 atomic percent gallium, and in some embodiments less than 1 atomic percent. In some embodiments, the top two monolayers may include gallium in an atomic percent range of 5%-20%, with the atomic percent of gallium dropping to about 1% or less after exceeding 5 nanometers from the surface. In various embodiments, the atomic percent of gallium in the thin layer may be less than 5%, less than 3%, or less than 1% after passing the first two monolayers of the gallium-rich layer. In various embodiments, gallium may be incorporated into substitutional sites of the silicon or silicon germanium lattice, thereby rendering it electrically active.

[0058] In some embodiments, the application of gallium is graded so that the gallium concentration is highest at the outer surface of the gallium-rich layer 519. This can be achieved by starting the flow of the gallium precursor at a relatively low level and increasing the flow over time as the gallium is applied.

[0059] In various embodiments, the gallium-rich layer 519 may have a resistivity (eg, 0.15-0.25 milliohm-cm) that is lower than the resistivity of the source / drain semiconductor layer 506 (eg, 3 to 0.5 milliohm-cm).

[0060] In various embodiments, gallium is deposited only over the source / drain of PMOS devices and not over the source / drain of NMOS devices of integrated circuit 500. For example, the NMOS region may be covered with a hard mask / dielectric layer before depositing gallium.

[0061] Drain / source contact metal (not shown) can be formed above gallium-rich layer 519. In some embodiments, one or more intermediate contact materials can be formed between gallium-rich layer 519 and drain / source contact metal. The intermediate contact material can include one or more conductive materials, such as titanium, nickel, or platinum. In various embodiments, the intermediate contact material can interact with the silicon of drain / source semiconductor layer 506 to form a silicide (e.g., at the top surface). In one embodiment, titanium is deposited on gallium, resulting in the formation of titanium germanium silicide. In various embodiments, a thin metal nitride (e.g., titanium nitride) can also (or alternatively) be deposited as the intermediate contact material. A source / drain contact metal (e.g., tungsten, cobalt, copper, aluminum, ruthenium, alloys of any of these, or other conductive materials) can then be formed above the intermediate contact material.

[0062] Figure 6 A portion of an example PMOS source / drain region 600 is shown. The source / drain region 600 illustrates a FinFET architecture and includes a source / drain semiconductor layer 602 (e.g., including boron-doped silicon germanium), a gallium-rich layer 604, an intermediate contact layer 606 (e.g., including titanium), and a source / drain contact metal 608 (e.g., including tungsten).

[0063] Figure 7 Secondary ion mass spectroscopy (SIMS) profiles of different source / drain compositions are shown. Graph 700 shows the profile of an example source / drain with a selective in-situ boron-doped silicon germanium epitaxial film that is gallium-rich, while graph 750 shows the profile of an example source / drain with a boron-doped silicon germanium epitaxial film that is not gallium-rich.

[0064] Waveforms 702 and 752 show the corresponding concentration of boron, waveforms 704 and 754 show the corresponding concentration of germanium, and waveforms 706 and 756 show the corresponding concentration of gallium (all as a function of the depth of the epitaxy into the source / drain). As shown, the gallium concentration shown in the first graph 700 is significantly higher at various depths relative to the gallium shown in the second graph 750.

[0065] The embodiments described herein (e.g., utilizing a gallium-rich layer between the source contact metal and the source / drain semiconductor layer) can be used for many different types of transistors, including at least planar transistors, FinFETs, GAAFETs, trench FETs, stacked complementary metal oxide semiconductor (CMOS) transistors, complementary FETs (C-FETs), nanowires / ribbons, stacked nanowires / ribbons, tunnel FETs, or other suitable transistors including source / drain. Any suitable embodiments described herein can also be used for transistors in which the entire source / drain is deposited during a trench contact (TCN) etch (gate-first or gate-last process flow), transistors in which the back-end contacts are formed from the back side of the wafer through vias, and transistors formed on the back side of the wafer.

[0066] Any suitable channel material may be used in a transistor implementing any of the various embodiments described above. For example, the channel material may include silicon, strained silicon, relaxed or strained silicon germanium, silicon germanium tin, germanium tin, or a III-V material.

[0067] In addition, any suitable characteristics of a specific component (e.g., gallium-rich layer, source / drain region, source / drain semiconductor layer, source / drain contact metal, etc.) described with respect to one embodiment of the embodiments herein may also be applicable to other embodiments described herein. As just one example, the method of forming gallium-rich layer 519 or other characteristics of gallium-rich layer 519 may be applied to other gallium-rich layers (e.g., 119, 219, 319, 419, etc.) described herein.

[0068] Figure 8 An example method for forming a highly conductive p-type transistor contact comprising a gallium-rich layer adjacent to a boron-doped silicon germanium epitaxial film is shown.

[0069] At 802, a first layer including boron, silicon, and germanium is formed. The first layer is located above a substrate. For example, the first layer can be formed on the substrate (eg, on a surface of the substrate and / or on a fin extending from the substrate).

[0070] At 804, a second layer is formed positioned adjacent to the first layer. The second layer includes gallium.

[0071] At 806 , a third layer including metal is formed on the second layer.

[0072] although Figure 8 An example block diagram of process 800 is shown, but in some implementations, process 800 may include Figure 8 The blocks shown in the process 800 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those shown in the process 800. Additionally or alternatively, two or more of the blocks in the process 800 may be performed in parallel.

[0073] Fig. 9 A schematic diagram of a cross-sectional view of an example integrated circuit device (eg, chip) 900 according to some embodiments of the present disclosure is provided. The IC device 900 may include one or more transistors including a gallium-rich layer as described herein.

[0074] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0075] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on a wafer. BEOL may include contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed.

[0076] The embodiments described herein may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such approaches may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such approaches may also be applicable to FEOL processing.

[0077] like Fig. 9As shown, the IC device 900 may include a front side 930, which includes a FEOL portion 910, which includes various logic layers, circuits, and devices for driving and controlling the logic IC. These circuits and devices can be configured for any number of functions, such as logic or computing transistors, input / output (I / O) transistors, access or switching transistors, and / or radio frequency (RF) transistors, to name a few examples. According to some embodiments, in addition to these devices and circuits, the FEOL portion 910 may include, for example, one or more other layers or structures associated with semiconductor devices and circuits. For example, the FEOL portion 910 may also include a substrate and one or more dielectric layers surrounding active and / or conductive portions of the device and circuit. The FEOL portion may also include one or more conductive contacts that provide electrical contact to transistor elements (such as gate structures, drain regions, or source regions). The FEOL portion may also include local interconnects (e.g., vias or lines) that connect contacts to interconnect features within the BEOL portion 920.

[0078] Front side 930 of IC device 900 also includes BEOL portion 920 including various metal interconnect layers (eg, metal 9 to metal n, where n is any suitable integer). The various metal layers of BEOL portion 920 may be used to interconnect various inputs and outputs of FEOL portion 910.

[0079] Generally speaking, each of the metal layers of the BEOL portion 920 (e.g., Fig. 9 Each of the layers M1-Mn shown in ) may include a via portion and a trench / interconnect portion. Typically, the trench portion of the metal layer is above the via portion, but in other embodiments, the trench portion may be disposed below the via portion of any given metal layer of the BEOL portion 920. The trench portion of the metal layer may be configured to transmit signals and power along metal lines (sometimes also referred to as "trench"s) extending in the xy plane (e.g., in the x or y direction), while the via portion of the metal layer may be configured to transmit signals and power to, for example, any adjacent metal layer above or below through metal vias extending in the z direction. Thus, the vias connect metal structures (e.g., metal lines or vias) from one metal layer to metal structures of an adjacent metal layer. Although referred to as "metal" layers, the various layers of the BEOL portion 920 (e.g., Fig. 9The layers M1-Mn shown in the figure may include certain patterns of conductive metal (e.g., copper (Cu) or aluminum (Al), or a metal alloy) formed in an insulating medium such as an interlayer dielectric (ILD), or more generally, a pattern of conductive material. The insulating medium may include any suitable ILD material, such as silicon oxide, silicon nitride, aluminum oxide, and / or silicon oxynitride. In various embodiments, any one or more of these layers may additionally include active devices (e.g., transistors, diodes) and / or passive devices (e.g., capacitors, resistors, inductors).

[0080] The IC device 900 may also include a back side 940. For example, the back side 940 may be formed on a side of the wafer opposite the front side 930. In various embodiments, the back side 940 may include any suitable elements to assist in the operation of the IC device 900. For example, the back side 940 may include various metal layers to deliver power to the logic units of the FEOL portion 910. In some embodiments, transistors or other circuit elements may be formed on the back side 940 of the IC device 900.

[0081] Fig.10 1 is a top view of wafer 1000 and die 1002, wherein each die may include one or more transistors including a gallium-rich layer as described herein. Wafer 1000 may be composed of semiconductor material and may include one or more die 1002 having integrated circuit structures formed on a surface of wafer 1000. Each die 1002 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is completed, wafer 1000 may undergo a singulation process in which die 1002 are separated from one another to provide discrete "chips" of an integrated circuit product. Die 1002 may include one or more transistor support circuit devices to transmit electrical signals to transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1000 or die 1002 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1002. For example, a memory array formed of multiple memory devices may be formed on a processor unit (e.g., Fig.14The processor unit 1402) or other logic units configured to store information in a memory device or execute instructions stored in a memory array are on the same die 1002. Various of the microelectronic assemblies disclosed herein can be manufactured using die-to-wafer assembly techniques, in which some dies are attached to a wafer 1000 including other dies, and the wafer 1000 is subsequently singulated.

[0082] Fig.11 1 is a cross-sectional side view of an integrated circuit device 1100 that may include one or more transistors including a gallium-rich layer as described herein. The one or more integrated circuit devices 1100 may include one or more die 1002 ( Fig.10 ). The integrated circuit device 1100 may be formed on a die substrate 1102 (eg, Fig.10 1000) and may include a die (e.g., Fig.10 The die substrate 1102 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 1102 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1102 may be formed using an alternative material that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Groups II-VI, III-V, or IV may also be used to form the die substrate 1102. Although several examples of materials that may form the die substrate 1102 are described herein, any material that may serve as the basis for the integrated circuit device 1100 may be used. The die substrate 1102 may be a singulated die (e.g., Fig.10 of a die 1002) or a wafer (e.g., Fig.10 A portion of wafer 1000).

[0083] The integrated circuit device 1100 may include one or more device layers 1104 disposed on a die substrate 1102. The device layer 1104 may include features of one or more transistors 1140 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1102. The transistor 1140 may include, for example, one or more source and / or drain (S / D) regions 1120, a gate 1122 for controlling the flow of current between the S / D regions 1120, and one or more S / D contacts 1124 for transmitting electrical signals to / from the S / D regions 1120. The transistor 1140 may include additional features that are not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1140 is not limited to Fig.11The types and configurations shown in the figure and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as dual-gate transistors or tri-gate transistors, and wrap-around or full-ring gate transistors, such as nanoribbon, nanosheet, or nanowire transistors. Figures 12A-12D Examples of non-planar transistors are described.

[0084] The transistor 1140 may include a gate 1122 formed of at least two layers (a gate dielectric and a gate electrode). The gate dielectric may include one or more layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0085] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, and lead zinc niobate. In some embodiments, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0086] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1140 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of or include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0087] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0088] In some embodiments, when a cross section of the transistor 1140 is observed along the source-channel-drain direction, the gate electrode may be composed of or include a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1102 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1102 and does not include a sidewall portion substantially perpendicular to the top surface of the die substrate 1102. In other embodiments, the gate electrode may be composed of or include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of or include one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0089] In some embodiments, a pair of sidewall spacers sandwiching the gate stack may be formed on opposite sides of the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and typically include deposition and etching process steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0090] The S / D region 1120 may be formed within the die substrate 1102 adjacent to the gate 1122 of each transistor 1140. For example, the S / D region 1120 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the die substrate 1102 to form the S / D region 1120. An annealing process to activate the dopants and diffuse them further into the die substrate 1102 may follow the ion implantation process. In the latter process, the die substrate 1102 may first be etched to form a recess at the location of the S / D region 1120. An epitaxial deposition process may then be performed to fill the recess with the material used to fabricate the S / D region 1120. In some embodiments, the S / D region 1120 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1120 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further embodiments, the S / D region 1120 may be formed using one or more layers of metal and / or metal alloy.

[0091] By providing one or more interconnect layers (in Fig.11 1100) to and / or from devices (e.g., transistors 1140) of device layer 1104. For example, conductive features (e.g., gates 1122 and S / D contacts 1124) of device layer 1104 can be electrically coupled to interconnect structures 1128 of interconnect layers 1106-1110. One or more interconnect layers 1106-1110 can form a metallization stack (also referred to as an "ILD stack") 1119 of the integrated circuit device 1100.

[0092] Interconnect structures 1128 (eg, lines) may be arranged within interconnect layers 1106-1110 to transmit electrical signals according to a variety of designs; in particular, the arrangement is not limited to Fig.11 The specific configuration of the interconnect structure 1128 is shown in FIG. Fig.11 A particular number of interconnect layers 1106 - 1110 are shown in FIG. 1 , but embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than shown.

[0093] In some embodiments, the interconnect structure 1128 may include wires 1128a and / or vias 1128b filled with a conductive material such as a metal. The wires 1128a may be arranged to transmit electrical signals in the direction of a plane substantially parallel to the surface of the die substrate 1102 on which the device layer 1104 is formed. For example, the wires 1128a may transmit electrical signals in the direction of an in-page and / or in the direction of a cross-page. The vias 1128b may be arranged to transmit electrical signals in the direction of a plane substantially perpendicular to the surface of the die substrate 1102 on which the device layer 1104 is formed. In some embodiments, the vias 1128b may electrically couple the wires 1128a of different interconnect layers 1106-1110 together.

[0094] The interconnect layers 1106-1110 may include a dielectric material 1126 disposed between interconnect structures 1128, such as Fig.111106-1110. In some embodiments, the dielectric material 1126 disposed between the interconnect structures 1128 in different ones of the interconnect layers 1106-1110 may have different compositions; in other embodiments, the composition of the dielectric material 1126 between different interconnect layers 1106-1110 may be the same. The device layer 1104 may also include a dielectric material 1126 disposed between the transistor 1140 and the bottom layer of the metallization stack. The dielectric material 1126 included in the device layer 1104 may have a different composition than the dielectric material 1126 included in the interconnect layers 1106-1110; in other embodiments, the composition of the dielectric material 1126 in the device layer 1104 may be the same as the dielectric material 1126 included in any one of the interconnect layers 1106-1110.

[0095] A first interconnect layer 1106 (referred to as metal 1 or "M1") can be formed directly on the device layer 1104. In some embodiments, the first interconnect layer 1106 can include lines 1128a and / or vias 1128b, as shown. The lines 1128a of the first interconnect layer 1106 can be coupled to contacts (e.g., S / D contacts 1124) of the device layer 1104. The vias 1128b of the first interconnect layer 1106 can be coupled to the lines 1128a of the second interconnect layer 1108.

[0096] The second interconnect layer 1108 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1106. In some embodiments, the second interconnect layer 1108 may include vias 1128b to couple the interconnect structures 1128 of the second interconnect layer 1108 with the lines 1128a of the third interconnect layer 1110. Although the lines 1128a and the vias 1128b are structurally depicted with lines within the respective interconnect layers for clarity, in some embodiments, the lines 1128a and the vias 1128b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0097] A third interconnect layer 1110 (referred to as metal 11 or "M3") (and additional interconnect layers, as desired) may be formed successively on the second interconnect layer 1108 according to similar techniques and configurations as described in connection with the second interconnect layer 1108 or the first interconnect layer 1106. In some embodiments, interconnect layers that are "higher" (e.g., farther from the device layer 1104) in the metallization stack 1119 in the integrated circuit device 1100 may be thicker than interconnect layers lower in the metallization stack 1119, wherein the lines 1128a and vias 1128b in the higher interconnect layers are thicker than the lines and vias in the lower interconnect layers.

[0098] The integrated circuit device 1100 may include a solder resist material 1134 (eg, polyimide or a similar material) and one or more conductive contacts 1136 formed on the interconnect layers 1106-1110. Fig.11 , the conductive contacts 1136 are shown as being in the form of bonding pads. The conductive contacts 1136 can be electrically coupled to the interconnect structure 1128 and configured to transmit electrical signals of the transistor(s) 1140 to an external device. For example, a solder joint can be formed on one or more of the conductive contacts 1136 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit device 1100 to another component (e.g., a printed circuit board). The integrated circuit device 1100 may include additional or alternative structures for transmitting electrical signals from the interconnect layers 1106-1110; for example, the conductive contacts 1136 may include other similar features (e.g., pillars) that transmit electrical signals to external components.

[0099] In some embodiments where the integrated circuit device 1100 is a double-sided die, the integrated circuit device 1100 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1104. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 1106-1110 to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1104 and additional conductive contacts (not shown) on the side of the integrated circuit device 1100 opposite the conductive contacts 1136.

[0100] In other embodiments where the integrated circuit device 1100 is a double-sided die, the integrated circuit device 1100 may include one or more through silicon vias (TSVs) through the die substrate 1102; these TSVs may contact the device layer(s) 1104 and may provide a conductive path between the device layer(s) 1104 and additional conductive contacts (not shown) on the side of the integrated circuit device 1100 opposite the conductive contacts 1136. In some embodiments, the TSVs extending through the substrate may be used to transmit power and ground signals from the conductive contacts on the side of the integrated circuit device 1100 opposite the conductive contacts 1136 to the transistor 1140 and any other components integrated into the integrated circuit device (e.g., die) 1100, and the metallization stack 1119 may be used to transmit I / O signals from the conductive contacts 1136 to the transistor 1140 and any other components integrated into the integrated circuit device (e.g., die) 1100.

[0101] Multiple integrated circuit devices 1100 may be stacked, wherein one or more TSVs in each stacked device provide a connection between one of the devices and any other device in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies may be stacked on top of a base integrated circuit die, and the TSVs in the HBM die may provide a connection between each HBM and the base integrated circuit die. The conductive contacts may provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts may be fine pitch solder bumps (microbumps).

[0102] Figures 12A-12D is a simplified perspective view of an example planar transistor, FinFET, gate-all-around transistor, and stacked gate-all-around transistor.

[0103] Figures 12A-12D The transistor is shown formed on a substrate 1216 having a surface 1208. Isolation regions 1214 separate the source and drain regions of the transistor from other transistors and from a bulk region 1218 of the substrate 1216.

[0104] Fig. 12A is a perspective view of an example planar transistor 1200 including a gate 1202 that controls current flow between a source region 1204 and a drain region 1206. The transistor 1200 is planar because the source region 1204 and the drain region 1206 are planar relative to a substrate surface 1208.

[0105] Fig. 12B is a perspective view of an example FinFET transistor 1220 that includes a gate 1222 that controls current flow between a source region 1224 and a drain region 1226. Transistor 1220 is non-planar because source region 1224 and drain region 1226 include a "fin" that extends upward from substrate surface 1228. Because gate 1222 surrounds three sides of the semiconductor fin that extends from source region 1224 to drain region 1226, transistor 1220 can be considered a tri-gate transistor. Fig. 12B One S / D fin is shown extending through the gate 1222 , but multiple S / D fins may extend through the gate of the FinFET transistor.

[0106] Fig. 12C is a perspective view of a gate-all-around (GAA) transistor 1240 including a gate 1242 that controls current flow between a source region 1244 and a drain region 1246. The transistor 1240 is non-planar because the source region 1244 and the drain region 1246 are elevated from the substrate surface 1228.

[0107] Fig.12D12 is a perspective view of a GAA transistor 1260 including a gate 1262 that controls current flow between multiple elevated source regions 1264 and multiple elevated drain regions 1266. Transistor 1260 is a stacked GAA transistor because the gate controls current flow between multiple elevated S / D regions stacked on top of each other. Transistors 1240 and 1260 are considered full-all-around transistors because the gate surrounds all sides of the semiconductor portion extending from the source region to the drain region. Transistors 1240 and 1260 may be alternatively referred to as nanowire, nanosheet, or nanoribbon transistors depending on the width of the semiconductor portion extending through the gate (e.g., widths 1248 and 1268 of transistors 1240 and 1260, respectively).

[0108] Fig.13 1 is a cross-sectional side view of an integrated circuit device assembly 1300 that may include one or more transistors including a gallium-rich layer as described herein. The integrated circuit device assembly 1300 includes a plurality of components disposed on a circuit board 1302 (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly 1300 includes components disposed on a first side 1340 of the circuit board 1302 and an opposite second side 1342 of the circuit board 1302; typically, the components may be disposed on one or both sides 1340 and 1342.

[0109] In some embodiments, circuit board 1302 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 1302 (optionally in combination with other metal layers). In other embodiments, circuit board 1302 may be a non-PCB substrate. Fig.13 The integrated circuit device assembly 1300 shown in FIG. 1 includes a package structure on an interposer 1336 coupled to a first side 1340 of a circuit board 1302 via a coupling component 1316. The coupling component 1316 can electrically and mechanically couple the package structure on the interposer 1336 to the circuit board 1302 and can include solder balls (e.g., Fig.13 as shown), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesives, bottom fill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0110] The package-on-interposer structure 1336 may include an integrated circuit component 1320 coupled to the interposer 1304 via a coupling component 1318. The coupling component 1318 may take any suitable form for the application, such as those discussed above with reference to the coupling component 1316. Fig.13 A single integrated circuit component 1320 is shown in FIG. 1 , but multiple integrated circuit components may be coupled to interposer 1304 ; indeed, additional interposers may be coupled to interposer 1304 . Interposer 1304 may provide an intermediate substrate for bridging circuit board 1302 and integrated circuit components 1320 .

[0111] Integrated circuit component 1320 may be a packaged or unpackaged integrated circuit product including one or more integrated circuit dies (eg, die 1002, 1003, 1004, 1005, 1006, 1007, 1008, 1009, 1100, 1101, 1102, 1103, 1104, 1105, 1106, 1107 Fig.11 The integrated circuit device 1100 of the packaged integrated circuit component 1100) and / or one or more other suitable components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a packaging substrate, wherein the integrated circuit die and the packaging substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1320, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 1304. The integrated circuit component 1320 may include one or more computing system components, such as one or more processor units (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller. In some embodiments, the integrated circuit component 1320 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0112] In embodiments where integrated circuit component 1320 includes multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0113] In addition to including one or more processor units, the integrated circuit component 1320 may include additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separated from the integrated circuit die including the processor unit. These separate integrated circuit dies may be referred to as "chiplets". In an embodiment where the integrated circuit component includes multiple integrated circuit dies, the interconnection between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as an embedded multi-die interconnect bridge (EMIB)), or a combination thereof.

[0114] Typically, interposer 1304 can extend the connections to a wider pitch or reroute the connections to different connections. For example, interposer 1304 can couple integrated circuit component 1320 to a set of ball grid array (BGA) conductive contacts of coupling component 1316 for coupling to circuit board 1302. Fig.13 In the illustrated embodiment, integrated circuit component 1320 and circuit board 1302 are attached to opposite sides of interposer 1304; in other embodiments, integrated circuit component 1320 and circuit board 1302 may be attached to the same side of interposer 1304. In some embodiments, three or more components may be interconnected through interposer 1304.

[0115] In some embodiments, the interposer 1304 may be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1304 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the interposer 1304 may be formed of alternating rigid or flexible materials, which may include the same materials as those described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-holes 1310-1 (which extend from the first side 1350 of the interposer 1304 to the second side 1354 of the interposer 1304), blind vias 1310-2 (which extend from the first side 1350 or the second side 1354 of the interposer 1304 to the internal metal layer) and buried vias 1310-3 (which connect the internal metal layer).

[0116] In some embodiments, the interposer 1304 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, the interposer 1304 including the silicon interposer may also include one or more routing layers to route connections on the first side of the interposer 1304 to the opposite second side of the interposer 1304.

[0117] The interposer 1304 may further include embedded devices 1314, including both passive and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 1304. The package structure on the interposer 1336 may take the form of any package structure on the interposer known in the art.

[0118] The integrated circuit device assembly 1300 may include an integrated circuit component 1324 coupled to the first side 1340 of the circuit board 1302 via a coupling component 1322. The coupling component 1322 may take the form of any of the embodiments discussed above with reference to the coupling component 1316, and the integrated circuit component 1324 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1320.

[0119] Fig.13 The integrated circuit device assembly 1300 shown in the figure includes a package-on-package structure 1334 coupled to the second side 1342 of the circuit board 1302 by a coupling component 1328. The package stack structure 1334 may include an integrated circuit component 1326 and an integrated circuit component 1332 coupled together by a coupling component 1330, so that the integrated circuit component 1326 is disposed between the circuit board 1302 and the integrated circuit component 1332. The coupling components 1328 and 1330 may take the form of any embodiment of the coupling component 1316 described above, and the integrated circuit components 1326 and 1332 may take the form of any embodiment of the integrated circuit component 1320 described above. The package stack structure 1334 may be configured according to any package stack structure known in the art.

[0120] Fig.1414 is a block diagram of an example electrical device 1400 that may include one or more transistors including a gallium-rich layer as described herein. For example, any suitable component in the components of electrical device 1400 may include one or more of integrated circuit die 1002, integrated circuit device 1100, integrated circuit device assembly 1300, integrated circuit component 1320, or other components disclosed herein. Fig.14 1400, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 1400 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured on individual system-on-chip (SoC) dies.

[0121] Additionally, in various embodiments, the electrical device 1400 may not include Fig.14 , but the electrical device 1400 may include interface circuitry for coupling to one or more of the components. For example, the electrical device 1400 may not include the display device 1406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which the display device 1406 may be coupled. In another set of examples, the electrical device 1400 may not include the audio input device 1424 or the audio output device 1408, but may include audio input or output device interface circuitry (e.g., connector and supporting circuitry) to which the audio input device 1424 or the audio output device 1408 may be coupled.

[0122] The electrical device 1400 may include one or more processor units 1402 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1402 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (specialized processors that execute encryption algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. In this way, the processor unit may be referred to as an XPU (or xPU).

[0123] The electrical device 1400 may include a memory 1404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1404 may include memory located on the same integrated circuit die as the processor unit 1402. The memory may be used as a cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0124] In some embodiments, the electrical device 1400 may include one or more processor units 1402 that are heterogeneous or asymmetric with another processor unit 1402 in the electrical device 1400. Various differences may exist between the processing units 1402 in the system in terms of a range of merit metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as being asymmetric and heterogeneous among the processor units 1402 in the electrical device 1400.

[0125] In some embodiments, the electrical device 1400 may include a communication component 1412 (e.g., one or more communication components). For example, the communication component 1412 may manage wireless communications for transmitting data to and from the electrical device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may communicate data through a non-solid medium using modulated electromagnetic radiation. The term "wireless" does not mean that the associated devices do not include any wires, although in some embodiments they may not.

[0126] The communication component 1412 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 revision), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed IEEE 802.16 standard conformance and interoperability testing. The communication component 1412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1412 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher generations. In other embodiments, the communication component 1412 can operate according to other wireless protocols. The electrical device 1400 may include an antenna 1422 to facilitate wireless communication and / or receive other wireless communications (e.g., amplitude modulation (AM) or frequency modulation (FM) radio transmissions).

[0127] In some embodiments, the communication component 1412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet). As described above, the communication component 1412 can include multiple communication components. For example, the first communication component 1412 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication component 1412 can be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication component 1412 can be dedicated to wireless communications, and the second communication component 1412 can be dedicated to wired communications.

[0128] The electrical device 1400 may include a battery / power supply circuit arrangement 1414. The battery / power supply circuit arrangement 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit arrangements for coupling components of the electrical device 1400 to an energy source separate from the electrical device 1400 (e.g., AC line power).

[0129] The electrical device 1400 may include a display device 1406 (or corresponding interface circuitry, as described above). The display device 1406 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0130] The electrical device 1400 may include an audio output device 1408 (or corresponding interface circuitry, as described above). The audio output device 1408 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0131] The electrical device 1400 may include an audio input device 1424 (or a corresponding interface circuit arrangement, as described above). The audio input device 1424 may include any embedded or wired or wirelessly connected device that produces a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 1400 may include a global navigation satellite system (GNSS) device 1418 (or a corresponding interface circuit arrangement, as described above), such as a global positioning system (GPS) device. The GNSS device 1418 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1400 based on information received from one or more GNSS satellites, as is known in the art.

[0132] The electrical device 1400 may include another output device 1410 (or corresponding interface circuitry, as described above). Examples of other output devices 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0133] The electrical device 1400 may include another input device 1420 (or corresponding interface circuitry, as described above). Examples of other input devices 1420 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereo camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmogram) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0134] The electrical device 1400 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart home appliance, a consumer electronic product or device, a manufacturing device). In some embodiments, the electrical device 1400 may be any other electronic device that processes data. In some embodiments, the electrical device 1400 may include multiple discrete physical components. Given the range of devices that the electrical device 1400 may be as indicated in various embodiments, in some embodiments, the electrical device 1400 may be referred to as a computing device or a computing system.

[0135] Throughout the specification, multiple instances can be implemented as parts, operations or structures described as single instances. Although the individual operations of one or more methods are shown and described as separate operations, one or more of the individual operations can be performed simultaneously, and do not need to perform the operations in the order shown. The structure and function presented as separate parts in the example configuration can be implemented as a combined structure or parts. Similarly, the structure and function presented as a single part can be implemented as separate parts. These and other changes, modifications, additions and improvements fall within the scope of this paper theme.

[0136] It should also be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not intended to imply that the objects described in this manner must be in a given sequence in time, space, order, or in any other way. For example, without departing from the scope of this example embodiment, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact. The first contact and the second contact are both contacts, but they are not the same contact.

[0137] As used in the description of the example embodiments and the accompanying examples, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. For example, the phrase "A and / or B" means (A), (B), or (A and B), while the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0138] As used throughout this specification and the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed items.

[0139] It will be further understood that when used in this specification, the terms "comprises" and / or "comprising" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. In addition, the terms "comprises," "including," "having," etc. as used with respect to the embodiments of the present disclosure are synonymous.

[0140] This description may use the phrases "in an embodiment," "according to some embodiments," "according to an embodiment," or "in an embodiment," which may each refer to one or more of the same or different embodiments.

[0141] As used herein, the term "module" means a part of or including an ASIC, electronic circuit, system on chip, processor (shared, dedicated or group), solid-state device, memory (shared, dedicated or group) that executes one or more software or firmware programs, combinatorial logic circuits, and / or other suitable components that provide the described functionality.

[0142] As used herein, in some examples, "conductive" may refer to the property of a material having an electrical conductivity greater than or equal to 107 Siemens per meter (S / m) at 20 degrees C. Examples of such materials include Cu, Ag, Al, Au, W, Zn, and Ni.

[0143] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal.

[0144] Throughout the specification and claims, the term "connected" means a direct connection, such as an electrical, mechanical or magnetic connection between connected elements without any intermediate devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between connected elements or an indirect connection through one or more passive or active intermediate devices.

[0145] This description may use perspective-based descriptions, such as top / bottom, inside / outside, over / under, etc. Such descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0146] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the context of materials, a material or layer above or below another material or layer may be in direct contact or may have one or more intermediate materials or layers. Additionally, a material between two materials or layers may be in direct contact with both materials / layers or may have one or more intermediate materials / layers. In contrast, a first material or layer "on" a second material or layer means that at least a portion of the first material or layer is in direct physical contact with at least a portion of the second material / layer. Similar distinctions are made in the context of component assemblies.

[0147] As used herein, "A is adjacent to B" means that at least a portion of A is in direct physical contact with at least a portion of B.

[0148] As used herein, “A is near B” may mean that A is adjacent to B or A is otherwise close to B.

[0149] Unless otherwise indicated in the specific context of use, the term "predominantly" means more than 50% or more than half. For example, a composition that is primarily a first component means that more than half of the composition (e.g., by volume) is the first component (e.g., >50 atomic %). The term "predominantly" means the most or largest portion. For example, a composition that is primarily a first component means that the composition has more of the first component (e.g., by volume) than any other component. A composition that is primarily a first and a second component means that the composition has more of the first and second components than any other component. The term "substantially" means that only accidental variations exist. For example, a composition that is primarily a first component means that the composition may also include <1% of any other component. A composition that is primarily a first and a second component means that the composition may also include <1% of any component that replaces the first or second component.

[0150] The terms "substantially," "close," "approximately," "near," and "about" generally mean within + / - 10% of a target value (unless otherwise indicated).

[0151] Unless otherwise indicated in the explicit context in which it is used, the terms "substantially equal", "approximately equal" or "approximately equal" mean that there is no variation beyond chance between the two things so described. In the art, such variation typically does not exceed + / -10% of a predetermined target value.

[0152] In the corresponding drawings of the embodiments, signals, electric current, electrical bias or magnetic or electrical polarity can be represented by lines. Some lines can be thicker, to indicate more component signal paths, and / or have arrows at one or more ends, to indicate the main information flow direction. Such indication is not intended to be restrictive. On the contrary, these lines are used in combination with one or more exemplary embodiments to facilitate easier understanding of circuits or logic units. Any represented signal, polarity, electric current, voltage, etc. as indicated by design needs or preferences can actually include one or more signals that can travel in either direction, and can be realized with the signal scheme of any suitable type.

[0153] The materials described herein are shown in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to other elements. In addition, where deemed appropriate, reference numerals are repeated between the drawings to indicate corresponding or similar elements.

[0154] Although the accompanying drawings may illustrate embodiments in which structures are substantially aligned with Cartesian axes (e.g., device structures having substantially vertical sidewalls), both positive and negative (reentrant) tilted feature sidewalls often occur in practice. For example, manufacturing non-idealities may cause one or more structural features to have tilted sidewalls. Therefore, the properties shown are idealized only for the purpose of clearly describing the significant features. It should be understood that when any of the structures described herein is examined using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images, the schematic illustrations may not reflect real-world process limitations that may cause the features to appear less than "ideal." In such images of real structures, possible processing defects may also be visible, such as imperfectly straight edges of material, tapered vias or other openings, unintentional rounding or thickness variations of corners of different material layers, occasional screw dislocations, edge dislocations, or combined dislocations within a crystal region, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device manufacturing.

[0155] Example 1 includes a device comprising: a substrate comprising silicon; a first layer of a source or drain region of a p-type transistor, the first layer being located above the substrate, the first layer comprising boron, silicon, and germanium; a second layer coupled to the source or drain region, the second layer comprising a metal contact for the source or drain region; and a third layer located between the first layer and the second layer, the third layer comprising at least one single layer comprising gallium, wherein the third layer is adjacent to the first layer.

[0156] Example 2 includes the subject matter of Example 1, and wherein the first layer comprises epitaxially grown boron-doped silicon germanium, and the third layer comprises epitaxially grown boron-doped silicon germanium having a higher concentration of germanium than the first layer.

[0157] Example 3 includes the subject matter of Examples 1-2, wherein the third layer has a thickness between 10-20 nanometers.

[0158] Example 4 includes the subject matter of any of Examples 1-3, further comprising a fourth layer between the second layer and the third layer, the fourth layer comprising at least one of titanium, nickel, or platinum.

[0159] Example 5 includes the subject matter of any of Examples 1-4, wherein the second layer includes at least one of cobalt or tungsten.

[0160] Example 6 includes the subject matter of any of Examples 1-5, wherein the gallium concentration in the top two monolayers of the third layer is between 5E19 and 5E20 atoms / cm 3 within the range.

[0161] Example 7 includes the subject matter of any of Examples 1-6, wherein the first layer includes B-11 and B-10 isotopes of boron.

[0162] Example 8 includes the subject matter of any of Examples 1-7, wherein the apparatus is an integrated circuit component.

[0163] Example 9 includes the subject matter of any of Examples 1-8, wherein the apparatus further comprises a printed circuit board; and a first integrated circuit component attached to the printed circuit board, the first integrated circuit component comprising the substrate, the first layer, the second layer, and the third layer.

[0164] Example 10 includes the subject matter of Example 9, wherein the apparatus further comprises one or more second integrated circuit components attached to the printed circuit board.

[0165] Example 11 includes a device comprising: a substrate comprising silicon; a first layer positioned adjacent to the substrate, the first layer comprising boron, silicon, and germanium; a second layer positioned adjacent to the first layer, the second layer comprising gallium; and a third layer positioned adjacent to the second layer, the third layer comprising a metal.

[0166] Example 12 includes the subject matter of Example 11, and wherein the concentration of gallium in the second layer is between 5E19 and 5E20 atoms / cm 3 within the range.

[0167] Example 13 includes the subject matter of any of Examples 11-12, wherein the first layer comprises epitaxially grown boron-doped silicon germanium, and the second layer comprises epitaxially grown boron-doped silicon germanium having a higher concentration of germanium than the first layer.

[0168] Example 14 includes the subject matter of any of Examples 11-13, the device of claim 11, wherein the atomic percentage of gallium in a portion of the second layer below the top two monolayers of the second layer is less than five percent.

[0169] Example 15 includes the subject matter of any of Examples 11-14, wherein the third layer comprises at least one of titanium, nickel, platinum, cobalt, or tungsten.

[0170] Example 16 includes the subject matter of any of Examples 11-15, wherein the third layer comprises at least one of titanium, nickel, or platinum.

[0171] Example 17 includes the subject matter of any of Examples 11-16, further comprising a fourth layer adjacent to the third layer, wherein the third layer includes at least one of cobalt or tungsten.

[0172] Example 18 includes the subject matter of any of Examples 11-17, wherein the first layer includes B-11 and B-10 isotopes of boron.

[0173] Example 19 includes the subject matter of any of Examples 11-18, wherein the apparatus is an integrated circuit component.

[0174] Example 20 includes the subject matter of any of Examples 11-19, wherein the apparatus further comprises a printed circuit board; and a first integrated circuit component attached to the printed circuit board, the first integrated circuit component comprising the substrate, the first layer, the second layer, and the third layer.

[0175] Example 21 includes the subject matter of any of Examples 11-20, and wherein the apparatus further comprises one or more second integrated circuit components attached to the printed circuit board.

[0176] Example 22 includes a method comprising: forming a first layer including boron, silicon, and germanium, the first layer being located above a substrate; forming a second layer positioned adjacent to the first layer, the second layer including gallium; and forming a third layer including a metal, the third layer being located on the second layer.

[0177] Example 23 includes the subject matter of Example 22, and wherein forming the second layer comprises applying triethylgallium on the first layer.

[0178] Example 24 includes the subject matter of any of Examples 22-23, wherein forming the second layer comprises applying trimethylgallium to the first layer.

[0179] Example 25 includes the subject matter of any of Examples 22-24, wherein forming the second layer comprises applying a precursor comprising gallium to the first layer at a temperature between 375 and 500 degrees Celsius.

[0180] Example 26 includes the subject matter of any of Examples 22-25, wherein the gallium concentration in the portion of the second layer is between 5E19 and 5E20 atoms / cm 3 within the range.

[0181] Example 27 includes the subject matter of any of Examples 22-26, wherein the first layer comprises epitaxially grown boron-doped silicon germanium.

[0182] Example 28 includes the subject matter of any of Examples 22-27, wherein gallium is present substantially only in two adjacent monolayers of the second layer.

[0183] Example 29 includes the subject matter of any of Examples 22-28, further comprising forming a fourth layer on the third layer, the fourth layer comprising the second metal.

[0184] Example 30 includes the subject matter of any of Examples 22-29, and wherein the second metal comprises at least one of cobalt or tungsten.

[0185] Example 31 includes the subject matter of any of Examples 22-30, wherein the third layer comprises at least one of titanium, nickel, or platinum.

[0186] Example 32 includes the subject matter of any of Examples 22-31, wherein the first layer includes B-11 and B-10 isotopes of boron.

[0187] For purposes of explanation, the foregoing description has been described with reference to specific example embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the possible example embodiments to the precise forms disclosed. In light of the above teachings, many modifications and variations are possible. The example embodiments are selected and described in order to best explain the principles involved and their practical applications, thereby enabling others skilled in the art to best utilize the various example embodiments with various modifications suitable for the particular use contemplated.

Claims

1. A device comprising: a substrate comprising silicon; a first layer of a source or drain region of a p-type transistor, the first layer being located above the substrate, the first layer comprising boron, silicon and germanium; a second layer coupled to the source or drain region, the second layer comprising a metal contact for the source or drain region; as well as A third layer is located between the first layer and the second layer, the third layer including at least one single layer including gallium, wherein the third layer is adjacent to the first layer.

2. The device according to claim 1, wherein: The first layer includes epitaxially grown boron-doped silicon germanium, and the third layer includes epitaxially grown boron-doped silicon germanium having a higher germanium concentration than the first layer.

3. The device according to claim 1, wherein: The thickness of the third layer is between 10 and 20 nanometers. 4 . The device of claim 1 , further comprising a fourth layer between the second layer and the third layer, the fourth layer comprising at least one of titanium, nickel, or platinum.

5. The device according to claim 1, wherein: The second layer includes at least one of cobalt or tungsten.

6. The device according to claim 1, wherein: The gallium concentration in the top two monolayers of the third layer is between 5E19 and 5E20 atoms / cm 3 within the range.

7. The device according to claim 1, wherein: The first layer includes B-11 and B-10 isotopes of boron.

8. The device according to claim 1, wherein: The device is an integrated circuit component.

9. The device according to any one of claims 1 to 8, wherein: The device also includes: Printed circuit boards; and A first integrated circuit component is attached to the printed circuit board, the first integrated circuit component comprising the substrate, the first layer, the second layer, and the third layer.

10. The device according to claim 9, wherein: The apparatus also includes one or more second integrated circuit components attached to the printed circuit board.

11. An apparatus comprising: a substrate comprising silicon; a first layer positioned adjacent to the substrate, the first layer comprising boron, silicon, and germanium; a second layer positioned adjacent to the first layer, the second layer comprising gallium; and A third layer is positioned adjacent to the second layer, the third layer comprising a metal.

12. The device according to claim 11, wherein The concentration of gallium in the second layer is between 5E19 and 5E20 atoms / cm 3 within the range.

13. The device according to claim 11, wherein: The first layer includes epitaxially grown boron-doped silicon germanium, and the second layer includes epitaxially grown boron-doped silicon germanium having a higher germanium concentration than the first layer.

14. The device according to claim 11, wherein: The atomic percentage of gallium in a portion of the second layer below the top two monolayers of the second layer is less than five percent.

15. The device according to any one of claims 11 to 14, wherein: The third layer includes at least one of titanium, nickel, platinum, cobalt or tungsten.

16. A method comprising: forming a first layer including boron, silicon, and germanium, the first layer being located above a substrate; forming a second layer positioned adjacent to the first layer, the second layer comprising gallium; and A third layer including metal is formed, the third layer being located on the second layer.

17. The method according to claim 16, wherein: Forming the second layer includes applying triethylgallium on the first layer.

18. The method according to claim 16, wherein: Forming the second layer includes applying trimethylgallium to the first layer.

19. The method according to claim 16, wherein: Forming the second layer includes applying a precursor including gallium to the first layer at a temperature between 375 and 500 degrees Celsius.

20. The method according to claim 16, wherein: The gallium concentration in a portion of the second layer is between 5E19 and 5E20 atoms / cm 3 within the range.

21. The method according to claim 16, wherein: The first layer includes epitaxially grown boron-doped silicon germanium.

22. The method according to claim 16, wherein: Gallium is present substantially only in two adjacent monolayers of the second layer.

23. The method of any one of claims 16-22, further comprising forming a fourth layer on the third layer, the fourth layer comprising a second metal.

24. The method according to claim 23, wherein: The second metal includes at least one of cobalt or tungsten.

25. The method according to any one of claims 16 to 22, wherein: The third layer includes at least one of titanium, nickel or platinum.

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