GOI test structure

Abstract

The GOI test structure comprises a substrate which comprises an active region; the gate structure is located on the substrate of the active region and covers a partial region of the active region where the gate structure is located, the gate structure comprises a gate dielectric layer and a gate covering the gate dielectric layer, the gate structure is used as a first test end, and in the active region where the gate structure is located, a pickup end is arranged in the substrate exposed by the gate structure; and the pickup end is used as a second test end. The gate structure only covers a part of the substrate of the active region, that is, the gate structure exposes the residual substrate except the active region covered by the gate structure, so that corresponding test signals can be loaded on the top of the gate structure and the substrate of the active region exposed by the gate structure, and the integrity of the gate dielectric layer is tested. Since the gate structure and the pickup end are located in the same active region, the test current can flow in the substrate of the same active region without being influenced by the shallow trench isolation structure, thereby improving the reliability of the test result.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a GOI test structure. Background Art

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, miniaturization has become a development trend in the field of semiconductor technology. More and more devices need to be integrated on a unit area of ​​a wafer. In order to meet the above needs, the semiconductor structure has also changed accordingly.

[0003] Gate oxide integrity (GOI) testing is a very important test item in semiconductor testing. It can be used to predict the service life of semiconductor devices and plays a vital role in improving the performance of integrated circuits.

[0004] However, with the changes in semiconductor structures, the reliability of the GOI test structure in the prior art still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiment of the present invention is to provide a GOI test structure to improve the reliability of the GOI test structure.

[0006] To solve the above problems, the present invention provides a GOI test structure, comprising: a substrate, wherein the substrate comprises an active region; a gate structure, which is located on the substrate of the active region and covers a partial region of the active region where the gate structure is located, wherein the gate structure comprises a gate dielectric layer and a gate covering the gate dielectric layer, wherein the gate structure is used as a first test terminal, and in the active region where the gate structure is located, a pickup terminal is provided in the substrate exposed by the gate structure, and the pickup terminal is used as a second test terminal.

[0007] Optionally, the GOI test structure further includes: plugs, wherein the plugs include a first plug located on the gate structure and a second plug located on the pickup end, and the first plug and the second plug are both in plural numbers.

[0008] Optionally, the GOI test structure further includes: an interconnection layer located on top of the plug, the interconnection layer including a first interconnection layer electrically connected to the first plug, and a second interconnection layer electrically connected to the second plug, a plurality of the first plugs are electrically connected to the same first interconnection layer, and a plurality of the second plugs are electrically connected to the same second interconnection layer.

[0009] Optionally, the first interconnect layer and the second interconnect layer are located in the same layer and are separate from each other.

[0010] Optionally, the gate structure includes a first gate structure extending along a first direction, and a second gate structure extending along a second direction and connected to the first gate structure, the second gate structure is located on one side of the first gate structure, and the first direction and the second direction are different; the pickup end is located on a side of the first gate structure that is away from the second gate structure; or, the pickup end is located on a side of the first gate structure that is away from the second gate structure, and on both sides of the second gate structure.

[0011] Optionally, when the pickup end is located on a side of the first gate structure facing away from the second gate structure, the GOI test structure further includes: source and drain doping regions located in the substrate on both sides of the second gate structure.

[0012] Optionally, the shape of the gate structure includes: one or more of a T-shape, an L-shape and an H-shape.

[0013] Optionally, the width of the pickup end ranges from 0.3 microns to 1 micron.

[0014] Optionally, the substrate includes a bottom semiconductor layer, an insulating material layer and a top semiconductor layer stacked in sequence from bottom to top.

[0015] Optionally, the GOI test structure further includes: a shallow trench isolation structure located in the substrate between adjacent active areas, wherein the bottom of the shallow trench isolation structure is lower than the top of the insulating material layer, or is flush with the top of the insulating material layer.

[0016] Optionally, the active area where the gate structure is located is a block structure, the gate structure is also a block structure, and the active area corresponds to the gate structure one-to-one; or, the active area where the gate structure is located is a block structure, the gate structure includes a first gate structure extending along a first direction, and a plurality of second gate structures extending along a second direction and connected to the first gate structure, the first direction and the second direction are different; or, the active area is a strip structure and there are multiple strip structures, the gate structure is a block structure, and the gate structure spans across a plurality of the active areas.

[0017] Optionally, the GOI test structure is located in a scribe line area on a wafer.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0019] The GOI test structure provided in the embodiment of the present invention includes a gate structure located on the substrate of the active area (AA) and covering a part of the active area where the gate structure is located, the gate structure includes a gate dielectric layer and a gate covering the gate dielectric layer, the gate structure is used as a first test terminal, and in the active area where the gate structure is located, the substrate exposed by the gate structure has a pickup terminal, and the pickup terminal is used as a second test terminal. Because the gate structure only covers the substrate of a part of the active area, that is, the gate structure exposes the remaining substrate except the active area covered by it, it is possible to load a corresponding test signal on the top of the gate structure and the substrate of the active area exposed by the gate structure to test the integrity of the gate dielectric layer. Since the gate structure and the pickup terminal are located in the same active area, the test current can flow in the substrate of the same active area without being affected by the shallow trench isolation structure, thereby improving the reliability of the test result. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 to Figure 2 is a schematic diagram of the structure of a GOI test structure;

[0021] Figure 3 It is a schematic diagram of the structure of a substrate and a shallow trench isolation structure of a GOI test structure;

[0022] Figure 4 is a schematic diagram of a top view of a first embodiment of a GOI test structure of the present invention;

[0023] Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure at AA1;

[0024] Figure 6 1 is a schematic structural diagram of a substrate and a shallow trench isolation structure in an embodiment of a GOI test structure of the present invention;

[0025] Figure 7 is a structural schematic diagram of another embodiment of a gate structure in the GOI test structure of the first embodiment of the present invention;

[0026] Figure 8 is a structural schematic diagram of another embodiment of a gate structure in the GOI test structure of the first embodiment of the present invention;

[0027] Fig. 9 is a structural schematic diagram of yet another embodiment of a gate structure in the GOI test structure of the first embodiment of the present invention;

[0028] Fig.10 is a structural schematic diagram of a second embodiment of a GOI test structure of the present invention;

[0029] Fig.11is a structural schematic diagram of a third embodiment of a GOI test structure of the present invention;

[0030] Fig.12 It is a Weibull plot of the gate oxide layer integrity ramp voltage test of the GOI test structure of the present invention. DETAILED DESCRIPTION

[0031] At present, the reliability of the GOI test structure still needs to be improved. Now, combined with a GOI test structure, the reasons why the GOI test structure needs to be improved are analyzed.

[0032] Figure 1 to Figure 2 is a schematic diagram of a GOI test structure; wherein, Figure 1 It is a top view. Figure 2 for Figure 1 Cross-sectional view along AA1. Figure 3 The schematic diagram is a structural diagram of a substrate and a shallow trench isolation structure of a GOI test structure.

[0033] refer to Figure 1 to Figure 2 A GOI test structure comprises: a substrate 10, wherein a shallow trench isolation structure (STI) 15 is formed in the substrate 10, wherein the area between adjacent shallow trench isolation structures 15 is an active area i, and the number of the active areas i is at least two; a gate structure 20, covering the substrate 10 of one of the active areas i, wherein the gate structure 20 comprises a gate dielectric layer 21, and a gate 22 covering the gate dielectric layer 21; the gate structure 20 is used as a first test terminal (not marked), and the substrate 10 of another active area i not covered by the gate structure 20 is used as a second test terminal (not marked).

[0034] Continue to refer Figure 1 to Figure 2 , and combined with reference Figure 3 , it is found through research that, since the first test end and the second test end are located in different active regions i, the two active regions i are isolated by the shallow trench isolation structure 15. When the depth h of the shallow trench isolation structure 15 along the normal direction of the top surface of the substrate 10 is large, and the substrate 10 where the shallow trench isolation structure 15 is located is a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GOI) structure, that is, when the substrate 10 where the shallow trench isolation structure 15 is located includes a bottom semiconductor layer 11, a top semiconductor layer 13, and an insulating material layer 12 located between the bottom semiconductor layer 11 and the top semiconductor layer 13, it is easy to make the bottom of the shallow trench isolation structure 15 flush with the top of the insulating material layer 12 (such as Figure 3As shown in FIG. 1 ), or the bottom of the shallow trench isolation structure 15 is located in the insulating material layer 12, it is difficult for the test current to flow in the substrate 10 of different active regions i, thereby affecting the reliability of the GOI test structure. In particular, when the thickness of the insulating material layer 12 along the normal direction of the top surface of the substrate 10 is greater than the thickness of the gate dielectric layer 21, it is more difficult for the current of the GOI test to flow in the substrate 10 of different active regions i.

[0035] In order to solve the above technical problems, an embodiment of the present invention provides a GOI test structure, comprising: a substrate, wherein the substrate comprises an active area; a gate structure, which is located on the substrate of the active area and covers a partial area of ​​the active area where the gate structure is located, wherein the gate structure comprises a gate dielectric layer and a gate covering the gate dielectric layer, wherein the gate structure is used as a first test terminal, and in the active area where the gate structure is located, a pickup terminal is provided in the substrate exposed by the gate structure, and the pickup terminal is used as a second test terminal.

[0036] The GOI test structure provided in the embodiment of the present invention includes a gate structure located on the substrate of the active region and covering a part of the active region where the gate structure is located, the gate structure includes a gate dielectric layer and a gate covering the gate dielectric layer, the gate structure is used as a first test terminal, and in the active region where the gate structure is located, the substrate exposed by the gate structure has a pickup terminal, and the pickup terminal is used as a second test terminal. Because the gate structure only covers the substrate of a part of the active region, that is, the gate structure exposes the remaining substrate except the active region covered by it, it is possible to load a corresponding test signal on the top of the gate structure and the substrate of the active region exposed by the gate structure to test the integrity of the gate dielectric layer. Since the gate structure and the pickup terminal are located in the same active region, the test current can flow in the substrate of the same active region without being affected by the shallow trench isolation structure, thereby improving the reliability of the test result.

[0037] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figure 4 is a schematic diagram of a top view of a GOI test structure according to an embodiment of the present invention; Figure 5 yes Figure 4 A schematic diagram of the cross-sectional structure at AA1; Figure 6 1 is a schematic structural diagram of a substrate and a shallow trench isolation structure in an embodiment of a GOI test structure of the present invention; Figure 7 is a structural schematic diagram of another embodiment of a gate structure in the GOI test structure of the first embodiment of the present invention; Figure 8is a structural schematic diagram of another embodiment of a gate structure in the GOI test structure of the first embodiment of the present invention; Fig. 9 It is a structural diagram of another embodiment of the gate structure in the GOI test structure of the first embodiment of the present invention.

[0039] It should be noted that in order to clearly show the GOI test structure, Figure 4 The interconnect layers are omitted.

[0040] refer to Figures 4 to 9 In this embodiment, the GOI test structure includes: a substrate 100, wherein the substrate includes an active area I; a gate structure 110, which is located on the substrate 100 in the active area I and covers a partial area of ​​the active area I where it is located, wherein the gate structure 110 includes a gate dielectric layer 111 and a gate 112 covering the gate dielectric layer, wherein the gate structure 110 is used as a first test terminal (not marked), and in the active area I where the gate structure 110 is located, a pickup terminal 120 is provided in the substrate 100 exposed by the gate structure 110, and the pickup terminal is used as a second test terminal (not marked).

[0041] The substrate 100 is used to provide an operating platform for forming a test structure (not shown).

[0042] The base 100 includes a substrate (not shown), the material of which may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium or other materials, and may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0043] Specifically, the substrate is a P-type substrate doped with P-type ions, including B, Ga or In. In other embodiments, the substrate is an N-type substrate doped with N-type ions, including P, As or Sb.

[0044] like Figure 6 As shown, in this embodiment, the substrate 100 includes a bottom semiconductor layer 101, an insulating material layer 102 and a top semiconductor layer 103 which are stacked in sequence from bottom to top.

[0045] By making the substrate 100 include a bottom semiconductor layer 101, an insulating material layer 102 and a top semiconductor layer 103 stacked in sequence from bottom to top, it is possible to reduce parasitic capacitance, reduce losses, improve the operating speed of the integrated circuit, fundamentally avoid the latch effect, and have a higher degree of integration; moreover, the above structure can make the carriers generated by radiation three orders of magnitude smaller than those of bulk silicon devices, thereby having excellent radiation resistance characteristics.

[0046] Specifically, the insulating material layer 102 is a buried oxide layer (BOX), the material of the buried oxide layer may be silicon dioxide, the material of the bottom semiconductor layer 101 may be silicon, germanium or a mixture of germanium and silicon, the material of the top semiconductor layer 103 may be undoped silicon, doped silicon, undoped germanium or doped germanium, when the material of the top semiconductor layer 103 is undoped silicon or doped silicon, the substrate on the insulator is a silicon-on-insulator structure, and when the material of the top semiconductor layer is undoped germanium or doped germanium, the substrate on the insulator is a germanium-on-insulator structure. In this embodiment, the substrate on the insulator is a silicon-on-insulator.

[0047] In this embodiment, the GOI test structure further includes: a shallow trench isolation structure 105, which is located in the substrate 100 between adjacent active regions I, and the bottom of the shallow trench isolation structure 105 is lower than the top of the insulating material layer 102, or is flush with the top of the insulating material layer 102 (e.g. Figure 6 shown).

[0048] The shallow trench isolation structure 105 is used to isolate each semiconductor device to prevent leakage current between the devices.

[0049] The bottom of the shallow trench isolation structure 105 is lower than the top of the insulating material layer 102 , or is flush with the top of the insulating material layer 102 , which is beneficial to improving the isolation performance of the shallow trench isolation structure 105 .

[0050] Specifically, the material of the shallow trench isolation structure 105 is an insulating material. As an example, the material of the shallow trench isolation structure 105 is silicon oxide.

[0051] The active region I is generally used to provide a process platform for forming various semiconductor devices (eg, the gate structure 110 ).

[0052] In this embodiment, the area between the shallow trench isolation structures 105 is an active area.

[0053] Usually GOI test structures include: Bulk test structures (such as Figures 4 to 5 As shown), gate edge (PolyEdge) type test structure (as shown Fig.10 ) and Field Edge test structures (such as Fig.11 shown).

[0054] like Figure 4 As shown, in a specific embodiment, the GOI test structure is a body-type test structure, and accordingly, the active region I where the gate structure 110 is located is a block structure.

[0055] The gate structure 110 is used as a first test terminal of a GOI test structure.

[0056] Specifically, the gate 112 serves as a first test terminal for performing an integrity test on the gate dielectric layer 111 below the gate 112 .

[0057] In this embodiment, the gate structure 110 includes a first direction Y (eg Figure 4 ) and a first gate structure 116 extending in a second direction X (as shown in FIG. Figure 4 A second gate structure 117 extending from and connected to the first gate structure 116 is formed, wherein the second gate structure 117 is located at one side of the first gate structure 116, and the first direction Y and the second direction X are different.

[0058] The gate structure 110 includes a first gate structure 116 extending along a first direction Y, and a second gate structure 117 extending along a second direction X and connected to the first gate structure 116, so as to form a pick-up terminal on one side of the first gate structure 116 while forming a source-drain doped region on the other side of the first gate structure 116, and is conducive to better defining the region of the pick-up terminal 120 and the region of the gate structure 110.

[0059] In one embodiment, the horizontal dimension (e.g., length) of the first gate structure 116 along the first direction Y is greater than the horizontal dimension (e.g., width) of the second gate structure 117 along the first direction. By setting the first gate structure 116, it is beneficial to increase the area of ​​the side wall of the gate structure 110, thereby improving the sensitivity of the test structure and increasing the probability of detecting problems.

[0060] In other embodiments, the gate structure may also include only the second gate structure.

[0061] Here, the first direction Y and the second direction X are different means that the first direction Y and the second direction X intersect.

[0062] In a specific embodiment, the first direction Y is perpendicular to the second direction X. The first direction Y is perpendicular to the second direction X, that is, the first gate structure 116 and the second gate structure 117 are perpendicular, which is conducive to reducing the difficulty of forming the first gate structure 116 and the second gate structure 117 and improving the quality of the first gate structure 116 and the second gate structure.

[0063] Specifically, the shapes of the gate structure 110 include: T-shaped (such as Figure 4 and 7 As shown), L-shaped (as Figure 8 as shown) and H-shaped (as Fig. 9 One or more of the above.

[0064] It should be noted that the width of the first gate structure 116 along the second direction X and the width of the second gate structure 117 along the first direction Y can be adjusted as required.

[0065] For example, Figure 7 As shown, the width of the second gate structure 117 along the first direction Y is small, so that along the first direction Y, the width of the substrate 100 region exposed on both sides of the second gate structure 117 is larger, so the process window for forming the source and drain doping regions is larger.

[0066] In this embodiment, when the active region I where the gate structure 110 is located is a block structure, the gate structure 110 is also a block structure, and the active region I corresponds to the gate structure 110 one by one.

[0067] When the active area I where the gate structure 110 is located is a block structure, the gate structure 110 is also a block structure, and when the active area I corresponds to the gate structure 110 one by one, it is convenient to form a GOI test structure of a body test structure, and the body test structure is used to detect defects located in the block gate dielectric layer 111.

[0068] Specifically, the gate structure 110 may include a first gate structure 116 extending along a first direction Y, and a second gate structure 117 extending along a second direction X and connected to the first gate structure 116 .

[0069] In this embodiment, the side of the second gate structure 117 facing away from the first gate structure 116 also extends to above the shallow trench isolation structure 105, which is beneficial to improving the sensitivity of detecting product defects, thereby improving the detection accuracy.

[0070] In this embodiment, the gate 112 is a polysilicon gate. In other embodiments, the gate may also be a metal gate.

[0071] In this embodiment, the gate dielectric layer 111 may be made of silicon oxide, silicon nitride or a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0072] In this embodiment, along the normal direction of the top surface of the substrate 100 , the thickness of the insulating material layer 102 is greater than the thickness of the gate dielectric layer 111 .

[0073] The thickness of the insulating material layer 102 is greater than the thickness of the gate dielectric layer 111 , that is, when the thickness of the insulating material layer 102 is greater, it is beneficial to reduce parasitic capacitance, reduce loss, and improve the operating speed of the integrated circuit.

[0074] The pickup end 120 is used as a second testing end.

[0075] As an example, the pickup terminal 120 is doped with P-type ions. When performing a GOI test, the first test terminal is used to load a positive voltage, and the second test terminal is used to load a negative voltage.

[0076] In other embodiments, the pickup terminal is doped with N-type ions, and when performing a GOI test, the first test terminal is used to load a negative voltage, and the second test terminal is used to load a positive voltage.

[0077] The gate structure 110 located on the substrate 100 of the active region I and covering a portion of the active region I where it is located is used as a first test terminal, and the gate structure 110 includes a gate dielectric layer 111 and a gate 112 covering the gate dielectric layer 111; in the active region I where the gate structure 110 is located, the substrate 100 exposed by the gate structure 110 has a pickup terminal 120, and the pickup terminal 120 is used as a second test terminal. Because the gate structure 110 only covers a portion of the substrate 100 of the active region I, that is, the gate structure 110 exposes the remaining substrate 100 except the active region I covered by it, the corresponding test signal can be loaded on the top of the gate structure 110 and the substrate 100 of the active region I exposed by the gate structure 110 to test the integrity of the gate dielectric layer 111. Since the gate structure 110 and the pickup terminal 120 are located in the same active region I, the test current can flow in the substrate 100 in the same active region I without being affected by the shallow trench isolation structure 105, thereby improving the reliability of the test result.

[0078] In this embodiment, the gate structure 110 includes a first gate structure 116 extending along a first direction Y, and a second gate structure 117 extending along a second direction X and connected to the first gate structure 116, the second gate structure 117 is located on one side of the first gate structure 116, and the first direction Y and the second direction X are different; accordingly, the pickup end 120 is located on the side of the first gate structure 116 that is away from the second gate structure 117.

[0079] The pickup terminal 120 is located on the side of the first gate structure 116 facing away from the second gate structure 117, which is beneficial to increase the process window of the pickup terminal 120 and reduce the difficulty of forming the pickup terminal 120. It is also beneficial to form source and drain doping regions on both sides of the second gate structure 117 while forming the pickup terminal 120.

[0080] In other embodiments, the pickup end may also be located on a side of the first gate structure facing away from the second gate structure, and on both sides of the second gate structure.

[0081] It should be noted that the width range of the pickup end 120 should not be too small or too large. If the width of the pickup end 120 is too small, the process of forming the pickup end 120 is likely to be difficult, resulting in poor formation quality of the pickup end 120, and correspondingly, the effect of connecting the pickup end 120 with the external test circuit is likely to be poor. If the width of the pickup end 120 is too large, when the area of ​​the GOI test structure remains unchanged, the area of ​​the gate structure 110 is likely to be too small, and the area of ​​the gate dielectric layer 111 is correspondingly too small, thereby affecting the reliability of the GOI test structure; or, when the area of ​​the gate dielectric layer 111 remains unchanged, the area of ​​the GOI test structure is likely to be too large, thereby resulting in poor effect of reducing the area of ​​the semiconductor structure. Therefore, in this embodiment, the width range of the pickup end 120 is 0.3 micrometers to 1 micrometer.

[0082] Here, the width of the pickup end 120 refers to the width in a direction perpendicular to the sidewall of the first gate structure 116 , that is, the width along the second direction X.

[0083] In this embodiment, the GOI test structure further includes: source-drain doped regions 130 located in the substrate 100 on both sides of the second gate structure 117 , and the ion type of the source-drain doped regions 130 is opposite to the ion type in the substrate 100 corresponding to the pickup end 120 .

[0084] The source-drain doped region 130 is used as the source region and drain region of the transistor. When the device is working, the source-drain doped region 130 is used to provide a carrier source. The GOI test structure includes the source-drain doped region 130, which is conducive to simulating the actual working state of the semiconductor device and improving the reliability of the GOI test structure.

[0085] Specifically, the ion type in the substrate 100 corresponding to the pickup end 120 is P-type ion, and the corresponding ion type in the source-drain doping region 130 is N-type ion, and the N-type ion includes P, As or Sb.

[0086] In other embodiments, the ion type in the substrate corresponding to the pickup end is N-type ion, and the ion type in the source and drain doping regions is P-type ion, and the P-type ion includes B, Ga or In.

[0087] As an example, when performing a GOI test, a zero potential is applied to the source-drain doping region 130 , or the source-drain doping region 130 is in a floating state.

[0088] Continue to refer Figure 4 and Figure 5In this embodiment, the GOI test structure further includes: a plug 140, wherein the plug 140 includes a first plug 141 located on the gate structure 110, and a second plug 142 located on the pickup end 120, and the number of the first plug 141 and the second plug 142 are both multiple.

[0089] The number of the first plug 141 and the second plug 142 is both plural, which is beneficial to reducing the test current value of each sub-circuit during the GOI test, thereby reducing the probability of each film layer (such as the plug 140) being damaged during the GOI test, and further improving the reliability of the GOI test result.

[0090] It should be noted that the plug 140 may further include a third plug 143 , which is located on the top of the source / drain doped region 130 and is electrically connected to the source / drain doped region 130 .

[0091] Specifically, the GOI test structure further includes: an interconnection layer 150, located on the top of the plug 140, the interconnection layer includes a first interconnection layer 151 electrically connected to the first plug 141, and a second interconnection layer 152 electrically connected to the second plug 142, a plurality of the first plugs 141 are electrically connected to the same first interconnection layer 151, and a plurality of the second plugs 142 are electrically connected to the same second interconnection layer 152.

[0092] Multiple first plugs 141 are electrically connected to the same first interconnect layer 151, and multiple second plugs 142 are electrically connected to the same second interconnect layer 152, which is beneficial to increasing the process window for forming the first interconnect layer 151 and the second interconnect layer 152, thereby reducing the process difficulty of forming the first interconnect layer 151 and the second interconnect layer 152.

[0093] More specifically, the first interconnection layer 151 and the second interconnection layer 152 are located in the same layer and are separated from each other.

[0094] The first interconnect layer 151 and the second interconnect layer 152 are located in the same layer and are separated from each other, so the first interconnect layer 151 and the second interconnect layer 152 can be formed in the same step, which is beneficial to reducing the process steps of forming the first interconnect layer 151 and the second interconnect layer 152 and saving process costs.

[0095] It should be noted that the GOI test structure may further include a third interconnect layer (not shown), namely, the zeroth metal layer (M0), which is located on the top of the source and drain doped region 130, and the third interconnect layer is electrically connected to the source and drain doped region 130 through the third plug 143.

[0096] In this embodiment, the GOI test structure is located in a scribe line area on a wafer.

[0097] The GOI test structure is located in the scribe line area on the wafer, which is beneficial to reducing the impact of forming the GOI test structure on the chip size, thereby helping to reduce process costs.

[0098] refer to Fig.10 , Fig.10 It is a structural diagram of the second embodiment of the GOI test structure of the present invention.

[0099] The similarities between the second embodiment and the above-mentioned embodiment are not described here. The difference between the second embodiment and the above-mentioned embodiment is that the GOI test structure is a gate edge test structure, and accordingly, the active region I' where the gate structure 210 is located is a block structure, and the gate structure 210 includes a first gate structure 216 (i.e., a comb handle) extending along a first direction Y', and a plurality of second gate structures 217 (i.e., comb teeth) extending along a second direction X' and connected to the first gate structure 216, and the first direction Y' and the second direction X' are different.

[0100] When the active region I' where the gate structure 210 is located is a block structure, the gate structure 210 includes a plurality of comb-shaped second gate structures 217 extending along the second direction X', that is, the second gate structure 217 is a strip structure, which is convenient for forming a GOI test structure of a gate edge type test structure. The GOI test structure of the gate edge type test structure is used to detect defects on the side wall of the gate dielectric layer (not shown).

[0101] The gate structure 210 includes a first gate structure 216 extending along a first direction Y', and a plurality of second gate structures 217 extending along a second direction X' and connected to the first gate structure 216, which increases the area of ​​the sidewall of the gate structure 210, which is beneficial to improving the sensitivity of detecting product defects, thereby improving the detection accuracy. At the same time, the gate structure 210 includes the first gate structure 216 extending along the first direction Y', which is also beneficial to defining the position of the pickup end 220, reducing the difficulty of forming the gate structure 210.

[0102] In other embodiments, the gate structure may also only include a plurality of second gate structures extending along the second direction.

[0103] In this embodiment, the width of the pickup end ranges from 0.3 micrometers to 1 micrometer.

[0104] Here, the width of the pickup end 220 refers to the width in a direction perpendicular to the sidewall of the first gate structure 216 , that is, the width along the second direction X′.

[0105] refer to Fig.11 , Fig.11It is a structural diagram of the third embodiment of the GOI test structure of the present invention.

[0106] The similarities between the third embodiment and the aforementioned embodiment are not repeated here. The difference between the third embodiment and the aforementioned embodiment is that the GOI test structure is a field edge test structure, and accordingly, the active region I″ is a strip structure and the number is multiple, the gate structure 310 is a block structure, and the gate structure 310 spans across multiple active regions I″.

[0107] When the active area I″ is a strip structure and there are multiple active areas I″, the gate structure 310 is a block structure, and the gate structure 310 spans across multiple active areas I″ to facilitate the formation of a GOI test structure of a field edge type test structure. The GOI test structure of the field edge type test structure is used to detect defects on the side wall of the active area I″.

[0108] Specifically, the active regions I″ extend along the second direction X″ and are arranged at intervals along the first direction Y″, and the gate structure 310 spans across a plurality of the active regions I″ along the first direction Y″.

[0109] In this embodiment, the gate structure 310 only includes a first gate structure 316 extending along the first direction Y″. The gate structure 310 only includes the first gate structure 316 extending along the first direction Y″, which is beneficial to reducing the process difficulty of forming the gate structure 310 .

[0110] In other embodiments, the gate structure may also include a first gate structure extending in a first direction, and a second gate structure extending along a second direction and connected to the first gate structure.

[0111] Accordingly, in the present embodiment, along the extension direction of the active region I″, portions of the substrate 300 are exposed on both sides of the gate structure 310, that is, along the extension direction of the active region I″, the pickup end 320 is located on both sides of the gate structure 310. When portions of the substrate 300 are exposed on both sides of the gate structure 310, the consistency with the semiconductor structure in the actual working state is better, which is beneficial to improving the reliability of the GOI test structure.

[0112] In this embodiment, the width of the pickup end 320 ranges from 0.3 micrometers to 1 micrometer.

[0113] Here, the width of the pickup end 320 refers to the width along the extending direction of the first gate structure 316 , that is, the width along the first direction Y″.

[0114] refer to Fig.12 , Fig.12It is a Weibull plot of the gate oxide layer integrity ramp voltage test (GOIVramp) of the GOI test structure of the present invention, wherein the abscissa represents the breakdown voltage Vbd (V), the ordinate represents the cumulative failure percentage (%), the Model A line represents the operating voltage of the semiconductor device, and the Model B line represents 2 to 3 times the operating voltage of the semiconductor device. Fig.12 The different curves in the figure indicate the test data after the GOI test is performed respectively using the GOI test structures of the above-mentioned multiple embodiments.

[0115] Depend on Fig.12 It can be seen that the test results are all distributed on the right side of Model A and Model B. Therefore, the GOI test structure of the embodiment of the present invention has better reliability and can be used for GOI testing.

[0116] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A GOI test structure, characterized in that: include: a substrate, the substrate comprising an active region; A gate structure is located on the substrate of the active area and covers a partial area of ​​the active area where it is located, the gate structure includes a gate dielectric layer and a gate covering the gate dielectric layer, the gate structure is used as a first test end, in the active area where the gate structure is located, there is a pickup end in the substrate exposed by the gate structure, and the pickup end is used as a second test end.

2. The GOI test structure according to claim 1, characterized in that: The GOI test structure further includes plugs, wherein the plugs include a first plug located on the gate structure and a second plug located on the pickup end, and the first plug and the second plug are both in plural numbers.

3. The GOI test structure according to claim 2, characterized in that: The GOI test structure further includes: an interconnection layer located on top of the plug, the interconnection layer including a first interconnection layer electrically connected to the first plug, and a second interconnection layer electrically connected to the second plug, a plurality of the first plugs are electrically connected to the same first interconnection layer, and a plurality of the second plugs are electrically connected to the same second interconnection layer.

4. The GOI test structure according to claim 3, characterized in that: The first interconnection layer and the second interconnection layer are located in the same layer and are separated from each other.

5. The GOI test structure according to claim 1, characterized in that: The gate structure comprises a first gate structure extending along a first direction, and a second gate structure extending along a second direction and connected to the first gate structure, wherein the second gate structure is located at one side of the first gate structure, and the first direction and the second direction are different; The pickup end is located at a side of the first gate structure facing away from the second gate structure; or, The pickup end is located on a side of the first gate structure facing away from the second gate structure and on two sides of the second gate structure.

6. The GOI test structure according to claim 5, characterized in that: When the pickup end is located at a side of the first gate structure facing away from the second gate structure, the GOI test structure further includes: source and drain doping regions located in the substrate at both sides of the second gate structure.

7. The GOI test structure according to claim 5, characterized in that: The shape of the gate structure includes: One or more of T-shape, L-shape and H-shape.

8. The GOI test structure according to any one of claims 1 to 7, characterized in that: The width of the pickup tip ranges from 0.3 micrometers to 1 micrometer.

9. The GOI test structure according to claim 1, characterized in that: The substrate comprises a bottom semiconductor layer, an insulating material layer and a top semiconductor layer which are stacked in sequence from bottom to top.

10. The GOI test structure according to claim 9, characterized in that: The GOI test structure further includes: a shallow trench isolation structure located in the substrate between adjacent active regions, wherein the bottom of the shallow trench isolation structure is lower than the top of the insulating material layer, or is flush with the top of the insulating material layer.

11. The GOI test structure according to claim 1, characterized in that: The active region where the gate structure is located is a block structure, the gate structure is also a block structure, and the active region corresponds to the gate structure one by one; or, The active region where the gate structure is located is a block structure, and the gate structure includes a first gate structure extending along a first direction, and a plurality of second gate structures extending along a second direction and connected to the first gate structure, wherein the first direction and the second direction are different; or, The active region is a strip-shaped structure and the number of the active regions is multiple. The gate structure is a block-shaped structure and the gate structure spans across the multiple active regions.

12. The GOI test structure according to claim 1, characterized in that: The GOI test structure is located in a scribe line region on a wafer.

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