Memory for image sensor and forming method thereof

Abstract

The invention discloses a method for forming a memory for an image sensor. The method comprises the following steps: providing a substrate; etching the substrate to form a first groove and a charge storage region which are communicated with each other; forming a first trench isolation structure in the first trench; forming a gate structure of a transfer transistor above the substrate; at least part of a channel of the transfer transistor is in the vertical direction; and reading or writing operation of the charge storage area is realized by controlling the gate structure. Based on the process compatibility of the image sensor and the memory, the image sensor and the memory are manufactured on the same wafer, and the vertical transfer gate of the transfer transistor is formed on the memory array, so that the memory density is improved, and the cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to a memory for an image sensor and a method for forming the memory. Background Art

[0002] The data stored in random access memory (RAM) can be read or written as needed, and the speed of reading and writing has nothing to do with the storage location of the data. This type of memory has the fastest reading and writing speed among all memories, but the stored data will be lost when the power is off, so it is mainly used to store data used for a short time. According to the different storage information, random access memory can be divided into static random access memory (Static RAM, SRAM) and dynamic random access memory (Dynamic RAM, DRAM).

[0003] For image sensors, the image data of the image sensor pixel array needs to be cached in the storage array. The existing technology usually manufactures the pixel array module, logic processing circuit and storage array module of the image sensor separately through separate silicon wafers, and then packages the three silicon wafers together by stacking. This process is not only difficult, but also significantly increases the cost. Summary of the invention

[0004] Based on the problems existing in the prior art, the present invention proposes a process method for manufacturing the pixel array, logic circuit and storage array of an image sensor on the same silicon wafer. This method is compatible with the existing manufacturing process of image sensors and has significantly reduced costs. In addition, the vertical transfer gate of the transfer transistor is formed on the storage array, which can improve the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention will be further explained in the form of exemplary embodiments, which will be described in detail by means of the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same numerals represent the same structure.

[0006] Figure 1 The figure is a schematic diagram of the structure of an image sensor according to an embodiment of the present invention.

[0007] Figure 2 Schematic diagram of the structure of a pixel unit according to an embodiment of the present invention.

[0008] Figure 3 Schematic diagram of the structure of a storage unit according to an embodiment of the present invention.

[0009] Figure 4 The figure is a schematic structural diagram of a substrate according to an embodiment of the present invention.

[0010] Figures 5 to 11It is a schematic diagram of the cross-sectional structure during the process of forming a memory according to an embodiment of the present invention.

[0011] Fig.12 For the corresponding Fig.11 Schematic diagram of the three-dimensional structure during the memory formation process.

[0012] Figures 13 to 15 It is a schematic diagram of the cross-sectional structure during the process of forming a memory according to an embodiment of the present invention.

[0013] Fig.16 For the corresponding Fig.15 Schematic diagram of the three-dimensional structure during the memory formation process.

[0014] Fig.17 A schematic diagram of a three-dimensional structure in a process of forming a memory according to an embodiment of the present invention.

[0015] Fig.18 It is a schematic diagram of the cross-sectional structure during the process of forming a memory according to an embodiment of the present invention.

[0016] Fig.19 A schematic diagram of a three-dimensional structure in a process of forming a memory according to an embodiment of the present invention.

[0017] Fig. 20 and Fig.21 It is a schematic diagram of the cross-sectional structure during the process of forming a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0019] like Figure 1 As shown, the image sensor 100 includes a pixel array 110, a logic circuit 120 and a storage array 130. The pixel array 110 includes a plurality of pixel units 111, and a semiconductor device ( Figure 1 The memory array 130 may include a plurality of memory cells 131. The image data of the pixel array 110 may be cached in the memory array 130.

[0020] like Figure 2As shown, the pixel unit 111 includes a photodiode 111a and a transfer transistor 111b connected to one end thereof. The other end of the photodiode 111a can be grounded or a fixed voltage. Figure 3 As shown, the storage unit 131 includes a capacitor 131a and a transfer transistor 131b connected to one end thereof. The other end of the capacitor 131a can be grounded or a fixed voltage. Among them, the capacitor 131a can be a plate capacitor or a diode junction capacitor. Due to the structural similarity between the pixel unit 111 and the storage unit 131, the compatibility of the image sensor and the DRAM process can be achieved, that is, the pixel array, logic circuit and storage array of the image sensor are formed on the same silicon wafer to form a non-stacked image sensor.

[0021] The following describes a method for forming a memory (storage array 130) for an image sensor in conjunction with the relevant drawings. It should be noted that due to the structural similarity between the pixel unit 111 and the storage unit 131, the processes of the pixel array 110 and the storage array 130 can be implemented simultaneously. For the convenience of description, the following only describes the structure of the storage array 130.

[0022] like Figure 4 As shown, a substrate 200 is provided. As an example only, the substrate 200 may include a first substrate 201 having a first doping type (such as p-type doping); and a first epitaxial doping layer 202 (such as n-type doping) having an opposite doping type to the first doping type is formed on the first substrate 201 by epitaxy to form a charge storage region. The substrate 200 may also be of other types. No further description is given here.

[0023] Furthermore, if Figure 5 , etching the substrate 200, forming interconnected first grooves 300 and a plurality of charge storage areas 400 (i.e., a single storage unit) on the front side of the substrate 200. The plurality of charge storage areas 400 are arranged in a dispersed array. Similarly, a plurality of doping regions (such as n-type doping) of photodiodes can also be formed in the pixel array 110 of the image sensor at the same time. Considering that the charge storage area 400 is a dispersed columnar structure, the charge storage area 400 may topple or break during the etching process, and a connection structure 410 may be formed between the upper portions of different charge storage areas 400, and the bottom of the connection structure 410 is hollowed out, thereby avoiding the topple or break of the charge storage area 400 during the etching process. The process of how to form the connection structure 410 is not limited here.

[0024] Furthermore, if Figure 6 As shown, ions of a first doping type (such as p-type doping) are implanted into the bottom of the first trench 300 to form a plurality of isolated second doping regions 310. Figure 7As shown, through heat treatment, the doping ions of the plurality of isolated second doping regions 310 are diffused laterally, so that the plurality of isolated second doping regions 310 are connected. Figure 6 and Figure 7 The main purpose of the process step is to form better electrical isolation between different charge storage regions 400.

[0025] It should be noted that Figure 6 and Figure 7 The process step can be omitted in some cases, for example, the bottom of the first trench 300 is in the p-type substrate (such as Figure 4 The p-type doped region 201 and Figure 5 For another example, after the memory is formed, the back side of the substrate 200 may be thinned to achieve electrical isolation between the charge storage regions 400 .

[0026] Furthermore, if Figure 8 As shown, a first trench isolation structure 500 is formed in the first trench 300. Specifically, a first dielectric layer 510 and a first polysilicon 520 can be formed on the first trench surface 300 to form the first trench isolation structure 500. The first polysilicon 520, the first dielectric layer 510 and the charge storage area 400 can form a plate capacitor. The first polysilicon is connected to a voltage.

[0027] In one embodiment, the first dielectric layer 510 may be doped with ions (such as p-type doping); the doped ions are diffused by heat treatment to form a lateral PN junction (parallel to the surface of the substrate 200) with the charge storage region 400, thereby increasing a PN junction capacitance. The first dielectric layer 510 may be made of silicon nitride, silicon oxide, silicon oxynitride, and the like.

[0028] In another embodiment, a doped epitaxial layer (e.g., p-type doping) (not shown in the figure) can be formed on the surface of the first trench 300 by epitaxy to form a lateral PN junction with the charge storage area 400, thereby increasing a PN junction capacitance; a first dielectric layer 510 is formed on the surface of the third doped epitaxial layer in the first trench 300; and a first polysilicon 520 is deposited to fill the first trench 300 to form a first trench isolation structure 500. The first dielectric layer 510 can be made of materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0029] Furthermore, if Figures 9 to 21 , a gate structure of a transfer transistor Tx is formed above the substrate 200; at least a portion of the channel of the transfer transistor Tx is in a vertical direction; and by controlling the gate structure, a read or write operation on the charge storage area 400 is achieved.

[0030] Specifically, Fig. 9As shown, a first doped epitaxial layer 600 is formed on the substrate 200. The first doped epitaxial layer 600 may be a p-type doped epitaxial layer.

[0031] For reference only, Fig.10 , perform n-type doping ion implantation on the first doped epitaxial layer 600 to form a doped layer 601 for forming a subsequent floating diffusion region. This step can also be performed after forming the channel region of the transfer transistor Tx. This step can also be added in other process links, which is not limited here.

[0032] refer to Fig.11 and Fig.12 , the first doped epitaxial layer 600 is etched to form a first hole 700 .

[0033] refer to Fig.13 , an oxide layer 602 is formed on the side and bottom of the first hole 700 .

[0034] refer to Fig.14 , laying the second polysilicon 800 to fill the first hole 700 .

[0035] refer to Fig.15 and Fig.16 , the second polysilicon 800 is thinned by chemical mechanical polishing to expose the floating diffusion region 601 .

[0036] Fig.17 is a schematic diagram of a three-dimensional structure in a process of forming a memory according to an embodiment of the present invention, Fig.18 is a cross-sectional schematic diagram corresponding to the column direction. Fig.17 and Fig.18 As shown, since after the n-type doping ions are injected, the two adjacent floating diffusion areas 601 along the row direction are electrically connected. In order to electrically isolate the two adjacent floating diffusion areas 601 from each other, an isolation structure is required between the two adjacent floating diffusion areas 601. The upper part of the isolation structure is formed by etching the second hole 810, so that the adjacent floating diffusion areas 601 in the row direction cannot be electrically connected. The shape and size of the second hole 810 can be adjusted adaptively according to the process requirements.

[0037] Fig.19 is a schematic diagram of a three-dimensional structure in a process of forming a memory according to an embodiment of the present invention, Fig. 20 is a cross-sectional schematic diagram corresponding to the column direction, Fig.21 is a cross-sectional schematic diagram corresponding to the row direction. Fig.19 , 20As shown in Figure 21, in order to ensure that two adjacent floating diffusion regions 801 are completely isolated, the second polysilicon 800 is etched back through an etching process so that the surface of the second polysilicon layer 800 is lower than the upper surface of the floating diffusion region 601, so that the polysilicon gates 800 of different transfer transistors Tx along the column direction are separated from each other. After the back etching process, the depth of the second hole 810 continues to deepen, so that the depth of the isolation structure deepens, thereby completing the lower part of the isolation structure, so that the floating diffusion regions 601 of adjacent columns are isolated. Further, an electrical contact point can be formed above the second polysilicon 800, so that the same electrical contact point can be used to control two adjacent transfer transistors Tx in the row direction. Specifically, the polysilicon gate on the first side of the first transfer transistor and the polysilicon gate on the second side of the second transfer transistor in the two adjacent transfer transistors Tx in the row direction are connected to the same electrical contact point, so that the electrical contact point controls the two adjacent transfer transistors Tx.

[0038] like Fig.19 As shown, the floating diffusion region 601 is a connected structure along the column direction.

[0039] like Fig.21 As shown, a portion of the channel 600 of the transfer transistor Tx is in a vertical direction, and the charge of the transfer transistor Tx can be controlled to transfer between the floating diffusion region 601 and the charge storage region 400 through the polysilicon 800 located on both sides of the transfer channel 600. In some embodiments, the floating diffusion region 601 corresponds to the upper part of the middle area of ​​the charge storage region 400, that is, the floating diffusion region 601 is arranged above the center position of the charge storage region 400. In some embodiments, there may be a deviation between the floating diffusion region 601 and the middle area of ​​the charge storage region 400, that is, there is a certain deviation between the floating diffusion region 601 and the center position of the charge storage region 400.

[0040] The embodiment of the present invention also includes other subsequent process steps, which belong to conventional technical means and will not be described in detail here.

[0041] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.

[0042] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A method for forming a memory for an image sensor, characterized in that: include: providing a substrate; Etching the substrate to form a first trench and a charge storage area that are interconnected; forming a first trench isolation structure in the first trench; forming a gate structure of a transfer transistor above the substrate; at least a portion of a channel of the transfer transistor is in a vertical direction; By controlling the gate structure, a read or write operation on the charge storage area is achieved.

2. The method according to claim 1, characterized in that The providing of the substrate comprises: providing a first substrate having a first doping type; epitaxially forming a first epitaxial doping layer having a doping type opposite to the first doping type on the first substrate, so as to form the charge storage region; The substrate includes the first substrate and the first epitaxial doping layer.

3. The method according to claim 2, characterized in that After etching the substrate to form the first trench and the charge storage area interconnected with each other, the method further comprises: Performing ion implantation of a first doping type into the bottom of the first trench to form a plurality of isolated second doping regions; Through heat treatment, doping ions of the plurality of isolated second doping regions are laterally diffused, so that the plurality of isolated second doping regions are connected.

4. The method according to claim 3, characterized in that The forming of a first trench isolation structure in the first trench comprises: forming a first dielectric layer on the surface of the first trench; A first polysilicon is deposited to fill the first trench to form the first trench isolation structure.

5. The method according to claim 3, characterized in that The forming of a first trench isolation structure in the first trench comprises: forming a first dielectric layer with doped ions on the surface of the first trench; By heat treatment, the doping ions are diffused to form a lateral PN junction with the charge storage region; A first polysilicon is deposited to fill the first trench to form the first trench isolation structure.

6. The method according to claim 3, characterized in that The forming of a first trench isolation structure in the first trench comprises: forming a second doped epitaxial layer on the surface of the first trench to form a lateral PN junction with the charge storage region; forming a first dielectric layer on a surface of the second doped epitaxial layer in the first trench; A first polysilicon is deposited to fill the first trench to form the first trench isolation structure.

7. The method according to claim 1, characterized in that The gate structure of the transfer transistor formed above the substrate comprises: forming a first doped epitaxial layer on the substrate; Etching the first doped epitaxial layer to form a first hole; A gate structure of a transfer transistor is formed in the first hole; at least a portion of a channel of the transfer transistor is in a vertical direction; The gate structure of the transfer transistor formed in the first hole includes: forming an oxide layer on the side and bottom of the first hole; Laying a second polysilicon to fill the first hole; The second polysilicon is etched back so that the surface of the second polysilicon layer is lower than the upper surface of the floating diffusion region, and the gates of the multiple transfer transistors are separated from each other, thereby forming the gates of the transfer transistors.

8. The method according to claim 1, characterized in that It is characterized in that An isolation structure is provided between the first holes in the column direction, so that the floating diffusion regions in adjacent columns are isolated.

9. The method according to claim 8, characterized in that After laying the second polysilicon to fill the first hole, the method further comprises: Using chemical mechanical polishing to planarize the upper surface of the second polysilicon; An upper portion of the isolation structure is formed by etching between the first holes in the column direction.

10. The method according to claim 9, characterized in that After the polysilicon layer is etched back through the etching process so that the surface of the polysilicon layer is lower than the upper surface of the floating diffusion area, the gates of multiple transfer transistors are separated from each other, thereby forming the polysilicon gates of the transfer transistors, the depth of the isolation structure is deepened, thereby completing the lower part of the isolation structure, so that the floating diffusion areas of adjacent columns are isolated.

11. The method according to claim 10, characterized in that The floating diffusion area is a connected structure along the column direction.

12. The method according to claim 1, wherein: The polysilicon gate on the first side of the first transfer transistor and the polysilicon gate on the second side of the second transfer transistor in two adjacent transfer transistors in the row direction are connected to the same electrical contact point, so that the electrical contact point controls the two adjacent transfer transistors.

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