VCSEL wafer and manufacturing method thereof

Abstract

The invention discloses a VCSEL wafer and a manufacturing method thereof. The VCSEL wafer comprises at least one VCSEL light emitting point and at least one photodiode, and the VCSEL light emitting point and the photodiode extend on the same substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor lasers, and more specifically to a VCSEL wafer and a method for manufacturing the same. Background Art

[0002] With the development of current production technology, like traditional silicon-based chips, high-integration optical chips based on reliability are becoming more and more popular in the market due to cost and size requirements. For example, VCSEL chips are also developing in the direction of integration.

[0003] In traditional VSEL chip applications, VCSEL chips are often used as basic components (for example, as light sources) and are assembled into modules with other devices. When VCSEL chips are used in TOF camera modules, VCSEL chips are assembled with circuit boards, brackets, optical diffraction elements, metal protective covers and other devices to form a laser projection module for TOF camera modules. When VCSEL chips are used in structured light systems, VCSEL chips are assembled with circuit boards, brackets, optical diffraction elements, metal protective covers and other devices to form a laser projection module for structured light systems.

[0004] It is worth mentioning that in the actual industry, the VCSEL die needs to be packaged before it can be assembled with other devices. VCSEL die refers to unpackaged VCSEL chips. VCSEL die are usually provided by chip manufacturers, and the packaging factory completes the packaging of VCSEL and the assembly of packaged products. In other words, from VCSEL die to VCSEL packaged products, it passes through two nodes of the industrial chain. Moreover, in the actual industry, the packaging factory may purchase VCSEL die provided by different manufacturers. At the same time, there may be problems such as uneven assembly accuracy during the assembly process, which makes it difficult to ensure the consistency of the final VCSEL packaged products.

[0005] Therefore, low-cost VCSEL chips and high-uniformity VCSEL module solutions are the problems that need to be solved urgently to promote the full introduction of VCSEL into the market. Summary of the invention

[0006] One advantage of the present application is that it provides a VCSEL wafer and a method for manufacturing the same, wherein the VCSEL wafer integrates VCSEL light-emitting points and photodiodes at the wafer level, thereby improving the integration of the VCSEL wafer compared to a traditional VCSEL wafer.

[0007] Another advantage of the present application is that it provides a VCSEL wafer and a method for manufacturing the same, wherein the VCSEL wafer is formed with not only VCSEL light-emitting points but also photodiodes, each VCSEL light-emitting point or multiple VCSEL light-emitting points can form a VCSEL chip, and each photodiode or multiple photodiodes can form a photodiode chip, so that both the VCSEL chip and the photodiode chip can be completed in a VCSEL chip manufacturing plant.

[0008] Another advantage of the present application is that it provides a VCSEL wafer and a method for manufacturing the same, wherein the VCSEL wafer can achieve connection between the VCSEL chip and the photodiode at the wafer level, without the need to package the VCSEL chip and / or the photodiode and then connect them through other connection structures, which can improve the connection stability of the VCSEL chip and the photodiode and can also reduce the volume of the final assembled product to a certain extent.

[0009] In order to achieve at least one of the above advantages or other advantages and purposes, according to one aspect of the present application, a VCSEL wafer is provided, comprising:

[0010] At least one VCSEL light emitting point and at least one photodiode, the VCSEL light emitting point and the photodiode extend on a common substrate.

[0011] In the VCSEL wafer according to the present application, each VCSEL light-emitting point includes a VCSEL body, a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body, each of the VCSEL bodies includes a VCSEL substrate, an N-DBR layer, an active region, a restriction layer having a restriction hole and a P-DBR layer, each of the photodiodes includes a diode body, a diode positive electrode and a diode negative electrode electrically connected to the diode body, each of the diode bodies includes a diode substrate, an N-type semiconductor layer, an inner interlayer, a P-type semiconductor layer and a protective layer, and the VCSEL substrate and the diode substrate are a common substrate.

[0012] In the VCSEL wafer according to the present application, the VCSEL substrate, the N-DBR layer, the active area and the P-DBR layer are arranged in sequence from bottom to top, the restriction layer is located on the upper side of the active area and / or the lower side of the active area, and the diode substrate, the N-type semiconductor layer, the inner interlayer, the P-type semiconductor layer and the protective layer are arranged in sequence from bottom to top.

[0013] In the VCSEL wafer according to the present application, the VCSEL negative electrode and the diode negative electrode are integrally connected to form a common negative electrode.

[0014] In the VCSEL wafer according to the present application, the common negative electrode is located on the lower surface of the common substrate.

[0015] In the VCSEL wafer according to the present application, the VCSEL substrate, the P-DBR layer, the active area and the N-DBR layer are arranged in sequence from bottom to top, the restriction layer is located on the upper side of the active area and / or the lower side of the active area, and the diode substrate, the P-type semiconductor layer, the inner interlayer, the N-type semiconductor layer and the protective layer are arranged in sequence from bottom to top.

[0016] In the VCSEL wafer according to the present application, the VCSEL positive electrode and the diode positive electrode are integrally connected to form a common positive electrode.

[0017] In the VCSEL wafer according to the present application, the common positive electrode is located on the lower surface of the common substrate.

[0018] In the VCSEL wafer according to the present application, the VCSEL wafer includes at least one VCSEL chip, wherein the VCSEL chip only includes the VCSEL light-emitting point but does not include the photodiode.

[0019] In the VCSEL wafer according to the present application, the VCSEL wafer includes at least one VCSEL chip, and each of the VCSEL chips includes at least one VCSEL light emitting point and at least one photodiode.

[0020] According to another aspect of the present application, a method for manufacturing a VCSEL wafer is provided, comprising:

[0021] Forming at least one VCSEL body by an epitaxial growth process, wherein the VCSEL body comprises: a common substrate, an N-DBR layer, an active region, a restriction layer having a restriction hole, and a P-DBR layer;

[0022] Growing an N-type semiconductor layer, an inner interlayer, a P-type semiconductor layer and a protective layer on the common substrate to form a diode body;

[0023] forming a VCSEL positive electrode on the VCSEL body and forming a diode positive electrode on the diode body; and

[0024] A VCSEL negative electrode and a diode negative electrode are formed on the lower surface of the substrate.

[0025] In the method for manufacturing a VCSEL wafer according to the present application, the VCSEL negative electrode and the diode negative electrode are integrally formed to form a common negative electrode.

[0026] Further objectives and advantages of the present application will be fully reflected through understanding of the following description and drawings.

[0027] These and other objects, features and advantages of the present application are fully reflected in the following detailed description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] These and / or other aspects and advantages of the present application will become clearer and easier to understand from the following detailed description of the embodiments of the present application in conjunction with the accompanying drawings, in which:

[0029] Figure 1 FIG. 4 is a schematic diagram of a VCSEL wafer according to an embodiment of the present application.

[0030] Figure 2 Another schematic diagram of a VCSEL wafer according to an embodiment of the present application is illustrated.

[0031] Figure 3 FIG. 1 is a schematic partial cross-sectional view of a VCSEL wafer according to an embodiment of the present application.

[0032] Figure 4 FIG. 4 is another partial cross-sectional schematic diagram of a VCSEL wafer according to an embodiment of the present application.

[0033] Figure 5 The figure shows a schematic flow chart of a method for manufacturing a VCSEL wafer according to an embodiment of the present application.

[0034] Figure 6 A schematic diagram of a VCSEL wafer manufacturing process according to an embodiment of the present application is illustrated. DETAILED DESCRIPTION

[0035] The terms and words used in the following specification and claims are not limited to the literal meanings, but are merely used by the inventor to enable a clear and consistent understanding of the present application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of the present application is provided for illustration purposes only and not for the purpose of limiting the present application as defined by the appended claims and their equivalents.

[0036] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0037] Although ordinals such as "first," "second," and the like will be used to describe various components, those components are not limited herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component without departing from the teachings of the present application. The term "and / or" as used herein includes any and all combinations of one or more associated listed items.

[0038] The terms used herein are only used for the purpose of describing various embodiments and are not intended to be limiting. As used herein, singular forms are intended to also include plural forms, unless the context clearly indicates an exception. In addition, it will be understood that the terms "including" and / or "having" when used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0039] Application Overview

[0040] As mentioned above, in the actual industry, the VCSEL die needs to be packaged before it can be assembled with other devices. VCSEL die refers to unpackaged VCSEL chips, which are usually provided by chip manufacturers, and the packaging factory completes the packaging of VCSEL and the assembly of packaged products. In other words, from VCSEL die to VCSEL packaged products, there are two nodes in the industrial chain. Moreover, in the actual industry, the packaging factory may purchase VCSEL die provided by different manufacturers. At the same time, there may be problems such as uneven assembly accuracy during the assembly process, which makes it difficult to ensure the consistency of the final VCSEL packaged products.

[0041] Therefore, low-cost VCSEL chips and high-uniformity VCSEL module solutions are the problems that need to be solved urgently to promote the full introduction of VCSEL into the market.

[0042] Based on this, the inventor of this application proposes that, starting from the semiconductor product design and manufacturing process, the photodiode is integrated on the VCSEL wafer, and in this way, the VCSEL light-emitting point and the photodiode are integrated at the wafer level, and each VCSEL light-emitting point or multiple VCSEL light-emitting points can form a VCSEL chip, and each photodiode or multiple photodiodes can form a photodiode chip. The VCSEL light-emitting point and the photodiode are both formed on the same silicon wafer and produced by the same chip manufacturer, which can improve the uniformity between each VCSEL light-emitting point and the uniformity between each photodiode, and reduce the product quality gap between the VCSEL light-emitting point and the photodiode.

[0043] Accordingly, according to one aspect of the present application, the present application proposes a VCSEL wafer, which includes: at least one VCSEL light-emitting point and at least one photodiode, wherein the VCSEL light-emitting point and the photodiode extend on a common substrate.

[0044] After introducing the basic principles of the present application, various non-limiting embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0045] Schematic VCSEL wafer

[0046] like Figures 1 to 4 As shown, a VCSEL wafer 1 according to an embodiment of the present application is illustrated. In an embodiment of the present application, the VCSEL light emitting point 11 and the photodiode 210 can be formed on the same wafer. In some embodiments of the present application, each one or more VCSEL light emitting points 11 form a VCSEL chip 10, and each one or more VCSEL light emitting points 11 form a photodiode chip 20. In other embodiments of the present application, one or more photodiodes 210 and one or more VCSEL light emitting points 11 form a VCSEL chip 10, which is equivalent to integrating the photodiode 210 into the VCSEL chip 10.

[0047] Accordingly, in one embodiment of the present application, Figure 1 As shown, the VCSEL wafer 1 includes at least one VCSEL chip 10 and at least one photodiode chip 20. In this way, the VCSEL chip 10 and the photodiode chip 20 are both manufactured in a VCSEL chip manufacturing plant, and the product quality difference between the VCSEL chip 10 and the photodiode chip 20 is small, and the structural loss of the VCSEL chip 10 and / or the photodiode chip 20 during the transmission process before the two are assembled can be reduced. Figure 2 As shown, in another embodiment of the present application, the VCSEL wafer 1 includes at least one VCSEL chip 10, wherein the photodiode 210 is integrated into the VCSEL chip 10, which can further reduce the structural loss of the VCSEL chip 10 and the photodiode 210 during the assembly process, and the photodiode 210 is integrated into the VCSEL chip 10 at the wafer level so that the connection between the VCSEL chip 10 and the light spot diode 210 is more stable.

[0048] Specifically, Figure 3As shown, in the embodiment of the present application, each of the VCSEL chips 10 includes at least one VCSEL light-emitting point 11. That is, each of the VCSEL chips 10 includes one VCSEL light-emitting point 11 or multiple VCSEL light-emitting points 11. Each VCSEL light-emitting point 11 includes a VCSEL body 111, and a VCSEL positive electrode 112 and a VCSEL negative electrode 113 electrically connected to the VCSEL body 111. Each of the VCSEL bodies 111 includes a VCSEL base (i.e., a VCSEL substrate layer), an N-DBR layer 1112, an active region 1113, a limiting layer 1114 having a limiting hole 103, and a P-DBR layer 1115. It is worth mentioning that the VCSEL substrate will also serve as the substrate of the photodiode 210, that is, the VCSEL light-emitting point 11 and the photodiode 210 extend on the same substrate, and the VCSEL substrate is a common substrate 1111 of the VCSEL chip 10 and the photodiode 210.

[0049] In the embodiment of the present application, the VCSEL substrate, the N-DBR layer 1112, the active area 1113 and the P-DBR layer 1115 of the VCSEL light emitting point 11 are arranged in sequence from bottom to top, as shown in FIG. Figure 3 The confinement layer 1114 is located on the upper side of the active region 1113 and / or the lower side of the active region 1113 .

[0050] It should be understood that in a modified embodiment of the present application, the light-emitting body 111 of the VCSEL light-emitting point 11 can be arranged in the following manner: the VCSEL substrate, the P-DBR layer 1115, the active area 1113 and the N-DBR layer 1112 are arranged in sequence from bottom to top, such as Figure 4 The confinement layer 1114 is located on the upper side of the active region 1113 and / or the lower side of the active region 1113 .

[0051] In the embodiment of the present application, the material of the VCSEL substrate may be a doped material such as InP, GaN, GaAs, etc. When the N-DBR layer 1112 is grown on the upper surface of the VCSEL substrate, the VCSEL substrate is made of an N-type doped material, and when the P-DBR layer 1115 is grown on the upper surface of the VCSEL substrate, the VCSEL substrate is made of a P-type doped material.

[0052] The N-DBR layer 1112 is composed of N-type doped Al with high aluminum content. x Ga 1-x As (x = 1 ~ 0) and N-type doped low aluminum content Al x Ga 1-xThe P-DBR layer 1115 is formed by alternating layers of As (x=1-0). x Ga 1-x As (x = 1 ~ 0) and P-type doped low aluminum content Al x Ga 1-x As (x = 1 to 0) is formed. In some examples of the present application, the material of the N-DBR layer 1112 and the P-DBR layer 1115 may not even have an aluminum content, that is, it does not contain aluminum. It is worth mentioning that the material selection of the alternating layer depends on the operating wavelength of the laser emitted by the VCSEL light emitting point 11, and the optical thickness of the alternating layer is equal to or approximately equal to 1 / 4 of the operating wavelength of the laser.

[0053] The active region 1113 is sandwiched between the N-DBR layer 1112 and the P-DBR layer 1115 to form a resonant cavity, wherein photons are reflected back and forth in the resonant cavity after being excited and repeatedly amplified to form laser oscillation, thereby forming a laser. A person skilled in the art should know that the emission direction of the laser can be selectively controlled by configuring and designing the N-DBR layer 1112 and the P-DBR layer 1115, for example, emitting from the N-DBR layer 1112, or emitting from the P-DBR layer 1115. Accordingly, the N-DBR layer 1112 and the P-DBR layer 1115 are configured such that after the VCSEL light emitting point 11 is turned on, the laser generated by the active region 1113 is reflected multiple times in the resonant cavity formed between the N-DBR layer 1112 and the P-DBR layer 1115 and then emitted from the P-DBR layer 1115 or the N-PDBR layer.

[0054] After the VCSEL light-emitting point 11 is turned on, the current is restricted by the restriction layer 1114 and is finally introduced into the middle area of ​​the VCSEL light-emitting point 11, so that the middle area of ​​the active area 1113 generates laser. More specifically, in the embodiment of the present application, the restriction layer 1114 has a restriction area surrounding the restriction hole 103, the restriction area has a higher resistivity to restrict the flow of carriers into the middle area of ​​the VCSEL light-emitting point 11, and the refractive index of the restriction area is lower to laterally restrict photons. The carrier and optical lateral restriction increases the density of carriers and photons in the active area 1113, and improves the efficiency of generating light in the active area 1113.

[0055] In the embodiment of the present application, the confinement layer 1114 may be implemented as an oxidized confinement layer 1114, which is formed on the upper side and / or lower side of the active region 1113 through an oxidation process. The confinement layer 1114 may also be implemented as other types, for example, as an ion confinement layer 1114, which is formed on the upper side or lower side of the active region 1113 through an ion implantation process, which is not limited by the present application.

[0056] The formation positions of the VCSEL positive electrode 112 and the VCSEL negative electrode 113 are not limited by the present application. Figure 3 As shown, in the embodiment of the present application, when the VCSEL substrate, the N-DBR layer 1112, the active area 1113 and the P-DBR layer 1115 are arranged sequentially from bottom to top, the VCSEL positive electrode 112 is formed on the upper surface of the VCSEL body 111, that is, the body upper surface 101, and the VCSEL negative electrode 113 is formed on the lower surface of the VCSEL body 111, that is, the body upper surface 102. When the VCSEL light-emitting point 11 is turned on, the laser generated by the active area 1113 is emitted from the P-DBR layer 1115, and the VCSEL positive electrode 112 can be implemented as a ring-shaped positive electrode, the middle of which is a hollow structure, forming a light-emitting hole 104 corresponding to the limiting hole 103 to allow light to pass through. When the P-DBR layer 1115 is located above the active area 1113 and the VCSEL light-emitting point 11 is turned on, when the laser generated by the active area 1113 is emitted from the N-DBR layer 1112, the VCSEL negative electrode 113 can be implemented as a ring-shaped negative electrode, the middle of which is a hollow structure to form a light-emitting hole 104 corresponding to the limiting hole 103 to allow light to pass through.

[0057] It should be understood that in a modified embodiment of the present application, when the light-emitting body 111 of the VCSEL light-emitting point 11 can be arranged in the following manner: the VCSEL substrate, the P-DBR layer 1115, the active area 1113 and the N-DBR layer 1112 are arranged in sequence from bottom to top, the VCSEL positive electrode 112 is formed on the lower surface of the VCSEL body 111, that is, the upper surface 102 of the body, and the VCSEL negative electrode 113 is formed on the upper surface of the VCSEL body 111, that is, the upper surface 101 of the body, as shown in FIG. Figure 4As shown. When the N-DBR layer 1112 is located above the active area 1113 and the VCSEL light emitting point 11 is turned on, when the laser generated by the active area 1113 is emitted from the N-DBR layer 1112, the VCSEL negative electrode 113 can be implemented as a ring-shaped negative electrode, the middle of which is a hollow structure to form a light exit hole 104 corresponding to the limiting hole 103, so as to allow the light to pass through. When the N-DBR layer 1112 is located above the active area 1113 and the VCSEL light emitting point 11 is turned on, when the laser generated by the active area 1113 is emitted from the P-DBR layer 1115, the VCSEL positive electrode 112 can be implemented as a ring-shaped positive electrode, the middle of which is a hollow structure to form a light exit hole 104 corresponding to the limiting hole 103, so as to allow the light to pass through.

[0058] In the embodiment of the present application, each of the photodiodes 210 includes a diode body 21, a diode positive electrode 22 and a diode negative electrode 23 electrically connected to the diode body 21, and each of the diode bodies 21 includes a diode substrate (i.e., a diode substrate layer), an N-type semiconductor layer 211, an inner interlayer 212, a P-type semiconductor layer 213 and a protective layer 214. As described above, the VCSEL substrate will also serve as the substrate of the photodiode 210, i.e., the diode substrate, that is, the VCSEL substrate and the diode substrate are a common substrate 1111 of the VCSEL chip 10 and the photodiode 210.

[0059] In the embodiment of the present application, the N-type semiconductor layer 211 is made of N-type doped GaAs, the P-type semiconductor layer 213 is made of N-type doped GaAs, the inner depletion layer is made of non-doped GaAs or low-concentration N-type doped GaAs, and the protective layer 214 is made of anti-reflective silicon dioxide material and is located on the light-receiving surface of the photodiode. It should be understood that the N-type semiconductor layer 211, the P-type semiconductor layer 213, the inner interlayer 212 and the protective layer 214 can be made of other materials.

[0060] like Figure 3As shown, in the embodiment of the present application, when the VCSEL substrate, the N-DBR layer 1112, the active area 1113 and the P-DBR layer 1115 of the VCSEL light-emitting point 11 are arranged sequentially from bottom to top, the diode substrate, the N-type semiconductor layer 211, the inner interlayer 212, the P-type semiconductor layer and the protective layer 214 of the photodiode 210 are arranged sequentially from bottom to top, and the photodiode 210 is a 2CU type silicon photodiode. The VCSEL negative electrode 113 and the diode negative electrode 23 are formed on the lower surface of the VCSEL substrate, that is, the lower surface 102 of the main body. The VCSEL negative electrode 113 and the diode negative electrode 23 are connected integrally and are a common negative electrode.

[0061] like Figure 4 As shown, when the VCSEL substrate, the P-DBR layer 1115, the active area 1113 and the N-DBR layer 1112 of the VCSEL light emitting point 11 are arranged sequentially from bottom to top, the VCSEL substrate, the P-type semiconductor layer 213, the inner interlayer 212, the N-type semiconductor layer 211 and the protective layer 214 of the photodiode 210 are arranged sequentially from bottom to top, and the photodiode 210 is a 2DU type silicon photodiode. The VCSEL positive electrode 112 and the diode positive electrode 22 are formed below the VCSEL substrate. The VCSEL positive electrode 112 and the diode positive electrode 22 are a common negative electrode.

[0062] In the embodiments of the present application, Figure 1 As shown, the VCSEL wafer 1 includes multiple rows of VCSEL chips 10 and multiple rows of photodiode chips 20, and the multiple rows of VCSEL chips 10 and the multiple rows of photodiode chips 20 are arranged alternately, and a row of photodiode chips 20 is arranged every other row of VCSEL chips 10, or a row of VCSEL chips 10 is arranged every other row of photodiode chips 20. It should be understood that in the variant implementation of the present application, the VCSEL chips 10 and the photodiode chips 20 can be arranged in other ways, which is not limited by the present application.

[0063] It is worth mentioning that the VCSEL wafer 1 can be divided into multiple integrated structures by cutting lanes. For example, each one or more VCSEL light-emitting points 11 form a first integrated structure, that is, a VCSEL chip 10, and a first cutting lane is provided between each two adjacent VCSEL chips 10. Accordingly, in the subsequent process, at least part of the VCSEL wafer 1 can be cut into multiple VCSEL chips 10; for another example, each one or more photodiodes 210 form a second integrated structure, that is, a photodiode chip 20, and a second cutting lane is provided between each two adjacent photodiode chips 20. Accordingly, in the subsequent process, at least part of the VCSEL wafer 1 can be cut into multiple photodiode chips 20; for another example, each one or more VCSEL light-emitting points 11 and one or more photodiodes 210 form a third integrated structure, that is, a VCSEL chip 20 integrated with a photodiode 210. Accordingly, in the subsequent process, at least part of the VCSEL wafer 1 can be cut into multiple VCSEL chips 20 integrated with a photodiode 210.

[0064] Method for manufacturing VCSEL wafer

[0065] Accordingly, in an embodiment of the present application, a method for manufacturing a VCSEL wafer is proposed, such as Figure 5 and Figure 6 As shown, it includes: S110, forming at least one VCSEL body 111 by an epitaxial growth process, wherein the VCSEL body 111 includes: a common substrate 1111, an N-DBR layer 1112, an active area 1113, a restriction layer 1114 with a restriction hole 103 and a P-DBR layer 1115; S120, growing an N-type semiconductor layer 211, an inner interlayer 212 and a P-type semiconductor layer 213 on the VCSEL substrate to form a diode body 21; S130, forming a VCSEL positive electrode 112 on the VCSEL body 111, and forming a diode positive electrode 22 on the diode body 21; and, S140, forming a VCSEL negative electrode 113 and a diode negative electrode 23 on the lower surface of the VCSEL substrate.

[0066] In step S110, at least one VCSEL body 111 is formed by an epitaxial growth process. The specific implementation method of forming the VCSEL body 10 is not limited by the present application. In a specific example of the present application, first, a common substrate 1111 is provided, and then, an N-type semiconductor structure layer, an active area structure layer and a P-type semiconductor structure layer stacked on the common substrate 1111 are grown on the common substrate 1111 by an epitaxial growth process to form an epitaxial body structure, wherein the epitaxial body structure includes an N-type semiconductor structure layer, an active area structure layer and a P-type semiconductor structure layer stacked on the common substrate 1111. Then, at least a portion of the epitaxial body structure is removed by an etching process so that the epitaxial body structure is separated into a plurality of repeating unit structures, each repeating unit structure including: a local N-type semiconductor structure layer, a local active area structure layer and a local P-type semiconductor structure layer. The repeating unit structure is subjected to oxidation treatment, and the part of the alternating layers of the N-type semiconductor structure layer and / or the part of the alternating layers of the P-type semiconductor structure layer in the repeating unit structure near the outer edge of the repeating unit structure is oxidized to form a restriction area, and the part near the center of the repeating unit structure is not oxidized to form a restriction hole 103 in the restriction area, so that the part of the alternating layers of the N-type semiconductor structure layer and / or the part of the alternating layers of the P-type semiconductor structure layer in the repeating unit structure forms a restriction layer 1114 with a restriction hole 103. The restriction layer 1114 can also be formed by other methods, for example, by an ion implantation process. In this way, each oxidized repeating unit structure and the common substrate 1111 form a VCSEL body 10. Optionally, the common substrate 1111 can be thinned.

[0067] In step S120, an N-type semiconductor layer 211, an inner interlayer 212, and a P-type semiconductor layer 213 are grown on the common substrate 1111 to form a diode body 21. Specifically, an N-type semiconductor layer 211, an inner interlayer 212, and a P-type semiconductor layer 213 stacked on the common substrate 1111 are grown in multiple regions on the common substrate 1111 by an epitaxial growth process to form multiple diode bodies 21.

[0068] In step S130, a VCSEL positive electrode 112 is formed on the VCSEL body 111, and a diode positive electrode 22 is formed on the diode body 21. Specifically, the formation positions of the VCSEL positive electrode 112 and the diode positive electrode 22 are not limited by the present application. In one embodiment of the present application, the VCSEL positive electrode 112 is formed on the upper surface of the VCSEL body 111, that is, the upper surface 101 of the body, by electroplating, and the diode positive electrode 22 is formed on the upper surface of the diode body 21 by electroplating.

[0069] In step S140, a VCSEL negative electrode 113 and a diode negative electrode 23 are formed on the lower surface of the VCSEL substrate. In the embodiment of the present application, the VCSEL negative electrode 113 and the diode negative electrode 23 are formed on the lower surface of the common substrate, that is, the lower surface of the VCSEL body, that is, the body lower surface 102, by an electroplating process. The VCSEL negative electrode 113 and the diode negative electrode 23 are integrally formed to form a common negative electrode.

[0070] In summary, the VCSEL wafer 1 and the manufacturing method thereof are explained. The VCSEL wafer 1 integrates the VCSEL light-emitting point 11 and the photodiode 210 at the wafer level, which improves the integration of the VCSEL wafer compared to the traditional VCSEL wafer.

[0071] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

Claims

1. A VCSEL wafer, characterized in that: include: At least one VCSEL light emitting point and at least one photodiode, the VCSEL light emitting point and the photodiode extend on a common substrate.

2. The VCSEL wafer according to claim 1, wherein: Each VCSEL light-emitting point includes a VCSEL body, a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body, each VCSEL body includes a VCSEL substrate, an N-DBR layer, an active area, a restriction layer with a restriction hole and a P-DBR layer, each photodiode includes a diode body, a diode positive electrode and a diode negative electrode electrically connected to the diode body, each diode body includes a diode substrate, an N-type semiconductor layer, an inner interlayer, a P-type semiconductor layer and a protective layer, and the VCSEL substrate and the diode substrate are a common substrate.

3. The VCSEL wafer according to claim 2, wherein: The VCSEL substrate, the N-DBR layer, the active area and the P-DBR layer are arranged in sequence from bottom to top, the restriction layer is located on the upper side of the active area and / or the lower side of the active area, and the diode substrate, the N-type semiconductor layer, the inner interlayer, the P-type semiconductor layer and the protective layer are arranged in sequence from bottom to top.

4. The VCSEL wafer according to claim 3, wherein: The VCSEL negative electrode and the diode negative electrode are integrally connected to form a common negative electrode.

5. The VCSEL wafer according to claim 3, wherein: The common negative electrode is located on the lower surface of the common substrate.

6. The VCSEL wafer according to claim 2, wherein: The VCSEL substrate, the P-DBR layer, the active area and the N-DBR layer are arranged in sequence from bottom to top, the restriction layer is located on the upper side of the active area and / or the lower side of the active area, and the diode substrate, the P-type semiconductor layer, the inner interlayer, the N-type semiconductor layer and the protective layer are arranged in sequence from bottom to top.

7. The VCSEL wafer according to claim 6, wherein: The VCSEL positive electrode and the diode positive electrode are integrally connected to form a common positive electrode.

8. The VCSEL wafer according to claim 7, wherein: The common positive electrode is located on the lower surface of the common substrate.

9. The VCSEL wafer according to claim 1, wherein: The VCSEL wafer includes at least one VCSEL chip, wherein the VCSEL chip only includes the VCSEL light-emitting point but does not include the photodiode.

10. The VCSEL wafer according to claim 1, wherein: The VCSEL wafer includes at least one VCSEL chip, and each of the VCSEL chips includes at least one VCSEL light emitting point and at least one photodiode.

11. A method for manufacturing a VCSEL wafer, characterized in that: include: Forming at least one VCSEL body by an epitaxial growth process, wherein the VCSEL body comprises: a common substrate, an N-DBR layer, an active region, a restriction layer having a restriction hole, and a P-DBR layer; Growing an N-type semiconductor layer, an inner interlayer, a P-type semiconductor layer and a protective layer on the common substrate to form a diode body; forming a VCSEL positive electrode on the VCSEL body and forming a diode positive electrode on the diode body; and A VCSEL negative electrode and a diode negative electrode are formed on the lower surface of the substrate.

12. The method for manufacturing a VCELS wafer according to claim 11, wherein: The VCSEL negative electrode and the diode negative electrode are integrally formed to form a common negative electrode.

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