Novel floating voltage level conversion circuit with high power conversion rate tolerance

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a novel floating voltage level conversion circuit with high power conversion rate tolerance. The input stage is composed of NDMOS transistors HNM1 and HNM2, and the floating voltage domain is composed of PDMOS transistors HPM1-HPM4 and low-voltage NMOS (N-channel Metal Oxide Semiconductor) NM1-NM2. Wherein the transistor HPM1 / NM1 and the transistor HPM2 / NM2 form a pair of clamping inverters. According to the high-voltage level conversion circuit, the PDMOS of the level conversion circuit does not have a scaling relationship, so that the pull-up tube can use strong PDMOS (HPM1 and HPM2) to realize higher conversion speed, and the limitation of a traditional high-voltage level conversion circuit is solved. Four PDMOS transistors may be placed in the same N-well as the floating circuit (the PDMOS bodies are connected to VDDH). This reduces the number of N traps required for each level converter from 6 to 4, thereby saving 20-30% of area. The floating voltage level conversion circuit can resist high power conversion rate (dVSSH / dt) noise and has high reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a novel floating voltage level conversion circuit capable of withstanding high power conversion rates. Background Art

[0002] In a circuit system using two or more different power supply voltages, a floating voltage level converter is used for interconnect communication between sub-blocks. It is widely used in integrated circuit fields such as sensor interfaces, power management, communication interfaces, and medical electronics. There are various challenges in the design of level conversion circuits that convert signals from low voltage to high voltage, mainly including low propagation delay, low power consumption, small layout area, and high power conversion rate (dV / dt) tolerance. Traditional high-voltage level conversion circuits mainly include three types: current mirror level converters, capacitive coupling level converters, and direct coupling level converters. Among them, direct coupling level converters have the advantages of not consuming static current and not using high-voltage capacitors, and are widely used. Such as Figure 1 As shown, Figure 1 The paper "Nanosecond DelayFloating High Voltage Level Shifters in a 0.35μm HV-CMOS Technology" published by Y. Moghe, T. Lehmann and T. Piessens is cited as the most advanced direct-coupled level-shifting circuit topology. The main feature of this circuit is that in addition to the current contention between HNM1 and PM1, the ratio between HPM1 and PM1 is also a key design parameter. The reference device size ratio (W / L)pd / (W / L)p=12.4 is given in the paper, and the pMOS transistor cannot be made stronger because this will first prevent the PDMOS transistor from pulling down its source voltage. Compared with the PDMOS transistor, the pMOS transistor is weaker. Its pull-up action limits the conversion speed of the circuit. The paper proposes an improved circuit other than the basic level converter to speed up the basic circuit and reduce area and power consumption, but it requires a control signal for setting the initial state, which has certain application limitations. Summary of the invention

[0003] In view of the above problems, the present disclosure provides a novel floating voltage level conversion circuit with high power conversion rate tolerance, the circuit comprising a low voltage domain and a floating voltage domain connected to each other;

[0004] The low voltage domain includes NDMOS transistors HNM1 and HNM2;

[0005] Wherein, the gate of the NDMOS transistor HNM1 is connected to the input level, and the source of the NDMOS transistor HNM1 is connected to the ground terminal of the inverter I1;

[0006] The gate of the NDMOS transistor HNM2 is connected to the output terminal of the inverter I1, and the source of the NDMOS transistor HNM2 is connected to the ground terminal of the inverter I1;

[0007] The floating voltage domain includes PDMOS transistors HPM1, HPM2, HPM3, HPM4 and NMOS transistors NM1, NM2;

[0008] The gate of the PDMOS transistor HPM1 is connected to the gate of the NMOS transistor NM1, the drain of the PDMOS transistor HPM1 is connected to the drain of the PDMOS transistor HPM3, and the source of the PDMOS transistor HPM1 is connected to the source of the PDMOS transistor HPM2;

[0009] The gate of the PDMOS transistor HPM2 is connected to the gate of the NMOS transistor NM2, and the drain of the PDMOS transistor HPM2 is connected to the drain of the PDMOS transistor HPM4;

[0010] The gate of the PDMOS transistor HPM3 is connected to the source of the NMOS transistor NM1, and the source of the PDMOS transistor HPM3 is connected to the drain of the NMOS transistor NM1;

[0011] The gate of the PDMOS transistor HPM4 is connected to the source of the NMOS transistor NM2, and the source of the PDMOS transistor HPM4 is connected to the drain of the NMOS transistor NM2;

[0012] The source of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM2.

[0013] Preferably, the floating voltage domain further comprises a cascade inverter;

[0014] The cascade inverters are respectively composed of inverter I3, inverter I5, inverter I4 and inverter I2;

[0015] The input end of the inverter I3 is connected to the source of the PDMOS transistor HPM4;

[0016] The output end of the inverter I4 is connected to the gate of the PDMOS transistor HPM2, and the input end of the inverter I4 is connected to the output end of the inverter I2;

[0017] The output end of the inverter I5 is connected to the gate of the NDMOS transistor HNM1 , and the input end of the inverter I5 is connected to the output end of the inverter I3 .

[0018] Preferably, the drain of the NDMOS transistor HNM1 is connected to the drain of the PDMOS transistor HPM1;

[0019] The drain of the NDMOS transistor HNM2 is connected to the drain of the PDMOS transistor HPM2 .

[0020] Preferably, the power supply terminal of the inverter I1 is connected to the voltage V DDL Connect the ground terminal of the inverter I1 to the voltage V SSL connect.

[0021] Preferably, the source of the NMOS transistor NM1 and the source of the NMOS transistor NM2 are both connected to the voltage V SSH connect;

[0022] The source of the PDMOS transistor HPM1 and the source of the PDMOS transistor HPM2 are both connected to the voltage V DDH connect.

[0023] Preferably, the source of the PDMOS transistor HPM2 is connected to the power supply terminal of the inverter I2.

[0024] Preferably, the output end of the inverter I2 is connected to the output level;

[0025] The input end of the inverter I2 is connected to the source of the PDMOS transistor HPM3.

[0026] Preferably, the source of the PDMOS transistor HPM4 is connected to the gate of the NMOS transistor NM1;

[0027] The source of the PDMOS transistor HPM3 is connected to the gate of the NMOS transistor NM2 .

[0028] The present disclosure has the following beneficial effects:

[0029] In the present disclosure, a novel floating voltage level conversion circuit with high power conversion rate tolerance is proposed; there is no scaling relationship between the PDMOS of the level conversion circuit, so the pull-up tube can use strong PDMOS (HPM1 and HPM2) to achieve faster conversion speed, solving the limitations of traditional high-voltage level conversion circuits. Four PDMOS transistors can be placed in the same N well as the floating circuit (the PDMOS body is connected to V DDH ). This reduces the number of N-wells required per level shifter from 6 to 4, saving 20-30% area. In addition, the floating voltage level shifter circuit is resistant to dV SSH / dt noise, with high reliability.

[0030] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The purpose and other advantages of the present disclosure can be realized and obtained by the structures indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 Shows a conventional direct-coupled level conversion circuit diagram;

[0033] Figure 2 A circuit diagram showing a novel floating voltage level conversion circuit in an embodiment of the present disclosure;

[0034] Figure 3 A circuit diagram showing another novel floating voltage level conversion circuit in an embodiment of the present disclosure;

[0035] Figure 4 A transient waveform diagram of a floating voltage level converter after layout simulation in an embodiment of the present disclosure is shown;

[0036] Figure 5 The floating voltage level converter of the embodiment of the present disclosure is shown to be resistant to power supply dV SSH Post-layout simulation transient waveform under / dt noise. DETAILED DESCRIPTION

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0038] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware units or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0039] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to the actual situation.

[0040] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example.

[0041] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or sub-modules is not necessarily limited to those steps or sub-modules explicitly listed, but may include other steps or sub-modules not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0042] like Figure 2 As shown, the present disclosure proposes a novel floating voltage level conversion circuit with high power conversion rate tolerance, the circuit comprising a low voltage domain and a floating voltage domain connected to each other;

[0043] The low voltage domain includes NDMOS transistors HNM1 and HNM2;

[0044] Wherein, the gate of the NDMOS transistor HNM1 is connected to the input level, and the source of the NDMOS transistor HNM1 is connected to the ground terminal of the inverter I1;

[0045] The gate of the NDMOS transistor HNM2 is connected to the output terminal of the inverter I1, and the source of the NDMOS transistor HNM2 is connected to the ground terminal of the inverter I1;

[0046] The floating voltage domain includes PDMOS transistors HPM1, HPM2, HPM3, HPM4 and NMOS transistors NM1, NM2;

[0047] The gate of the PDMOS transistor HPM1 is connected to the gate of the NMOS transistor NM1, the drain of the PDMOS transistor HPM1 is connected to the drain of the PDMOS transistor HPM3, and the source of the PDMOS transistor HPM1 is connected to the source of the PDMOS transistor HPM2;

[0048] The gate of the PDMOS transistor HPM2 is connected to the gate of the NMOS transistor NM2, and the drain of the PDMOS transistor HPM2 is connected to the drain of the PDMOS transistor HPM4;

[0049] The gate of the PDMOS transistor HPM3 is connected to the source of the NMOS transistor NM1, and the source of the PDMOS transistor HPM3 is connected to the drain of the NMOS transistor NM1;

[0050] The gate of the PDMOS transistor HPM4 is connected to the source of the NMOS transistor NM2, and the source of the PDMOS transistor HPM4 is connected to the drain of the NMOS transistor NM2;

[0051] The source of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM2.

[0052] Specifically, the drain of the NDMOS transistor HNM1 is connected to the drain of the PDMOS transistor HPM1;

[0053] The drain of the NDMOS transistor HNM2 is connected to the drain of the PDMOS transistor HPM2 .

[0054] Specifically, the power supply terminal of the inverter I1 is connected to the voltage V DDL Connect the ground terminal of the inverter I1 to the voltage V SSL connect.

[0055] Specifically, the source of the NMOS transistor NM1 and the source of the NMOS transistor NM2 are both connected to the voltage V SSH connect;

[0056] The source of the PDMOS transistor HPM1 and the source of the PDMOS transistor HPM2 are both connected to the voltage V DDH connect.

[0057] Specifically, the source of the PDMOS transistor HPM2 is connected to the power supply terminal of the inverter I2.

[0058] Specifically, the output end of the inverter I2 is connected to the output level;

[0059] The input end of the inverter I2 is connected to the source of the PDMOS transistor HPM3.

[0060] Specifically, the source of the PDMOS transistor HPM4 is connected to the gate of the NMOS transistor NM1.

[0061] When operating this circuit, consider V D High is equal to V DDH In this case, the gate voltage of HNM1 is V SSL , the gate of HPM1 is V SSH To switch the level shifter, the following sequence occurs:

[0062] When HNM1 is turned on, V D is pulled low, since HPM3 is turned on, V N To flip the state of the level shifter, HNM1 needs to be sized relative to HPM1 so that when the gate of HNM1 is set to V DDL , the gate of HPM1 is still at V SSH , node voltage V N At least pull it down to V DDH -|V tp,HPM2 |Below. Since NM1 is off, HPM3 is on but no current flows. Therefore, V D =V N .

[0063] Under these conditions, HNM1 is in the saturation region and HPM1 is assumed to be in the linear region to conservatively overestimate its strength. The current through HNM1 and HPM1 is given by:

[0064]

[0065]

[0066] In the formula, I HNM1 represents the current of NDMOS transistor HNM1; K′=μC ox , the subscript indicates N-channel or P-channel. In the formula, μ represents the carrier mobility, C ox Represents the gate oxide capacitance per unit area; W represents the width of the transistor, and the subscript represents the corresponding device; L represents the length of the transistor, and the subscript represents the corresponding device; the symbol V tn and |V tp | represent the N-channel and P-channel threshold voltages respectively, and the subscripts represent the corresponding devices.

[0067] Since the same current flows through HNM1 and HPM1, combining the above two equations, we can get:

[0068]

[0069] To obtain good yield, the NMOS / PMOS ratio is set to slow N / fast P corner, with maximum V DDH and minimum value V DDL In actual design, HNM1 and HPM1 can be taken as the minimum size allowed by the process.

[0070] When V N Down to V DDH -|V tp,HPM2 |,HPM2 is turned on,

[0071] V DM Through HPM2 by V SSL Start charging when V DM >V NM =V SSH When |V GS,HPM4 |=V DM -V SSH >|V tp,HPM4 |, HPM4 is turned on.

[0072] V NM Can you follow V DM The pull-up depends on the pull-up and pull-down strengths of HPM2 and NM2. The NMOS transistor needs to be made weaker than the PDMOS transistor, otherwise the latch will never change state.

[0073] With V DM As V rises, the gate drive of HPM4 increases, which is a positive feedback process. Therefore, the size design parameters of HPM4 / HPM2 are decoupled from other devices. NM Gradually straightened up V DDH power rail, V N Pull down to V SSH , the conversion is complete.

[0074] The present disclosure proposes a novel floating voltage level conversion circuit with high power conversion rate tolerance, which is characterized in that the width-to-length ratio of HPM3 and HPM2 is decoupled, so the pull-up strength of the pull-up tube HPM1 is large, which improves the speed of level conversion. Further, but at the cost of using an additional high-voltage PDMOS.

[0075] Further, such as Figure 3 As shown, the simple cross-coupling of the level shifter is enhanced by inserting two cascaded inverters in each path.

[0076] Specifically, the floating voltage domain further includes a cascade inverter;

[0077] The cascade inverters are respectively composed of inverter I3, inverter I5, inverter I4 and inverter I2;

[0078] The input end of the inverter I3 is connected to the source of the PDMOS transistor HPM4;

[0079] The output end of the inverter I4 is connected to the gate of the PDMOS transistor HPM2, and the input end of the inverter I4 is connected to the output end of the inverter I2;

[0080] The output end of the inverter I5 is connected to the gate of the NDMOS transistor HNM1 , and the input end of the inverter I5 is connected to the output end of the inverter I3 .

[0081] This ensures that the source voltage of HPM3 and HPM4 is strictly limited to V DDH and V SSH Therefore, the four PDMOS transistors of the present disclosure can be placed in the same N-well as the floating circuit (the PDMOS body is connected to V DDH ). This reduces the number of N-wells required per level converter from 6 to 4, saving 20-30% of area. Figure 4 As shown in Figure 1, the post-layout simulation results of the 0.18μm HVBCD process show that the propagation delay of the proposed level converter is in the ns level when the level conversion voltage is 45V. In addition, for almost all commercial thin-gate oxide processes, in order to avoid device damage or reliability issues, the absolute values ​​of the gate-source voltage and source-substrate voltage must be less than 6V. Figure 5 As shown, even at V SSH The node is applied with a conversion rate of up to 200V / ns, and the output state can still follow the input (the voltage glitch when the output is low does not reach the voltage threshold of the state flip, and will be absorbed by the parasitic capacitance of the node and will not cause functional abnormality), and the intermediate node V N The voltage is still within the safe range (maximum 5.85V, minimum -0.94V), and there is no need to add any protection devices or redundant symmetric structures to the circuit. Therefore, the proposed DC-LS can guarantee a dV of up to 200V / ns. SSH / dt slew rate without trouble.

[0082] Those skilled in the art should understand that although the present disclosure is described in detail with reference to the aforementioned embodiments, it is still possible to modify the technical solutions recorded in the aforementioned embodiments, or to make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A novel floating voltage level conversion circuit with high power conversion rate tolerance, characterized in that: The circuit includes a low voltage domain and a floating voltage domain connected to each other; The low voltage domain includes NDMOS transistors HNM1 and HNM2; Wherein, the gate of the NDMOS transistor HNM1 is connected to the input level, and the source of the NDMOS transistor HNM1 is connected to the ground terminal of the inverter I1; The gate of the NDMOS transistor HNM2 is connected to the output terminal of the inverter I1, and the source of the NDMOS transistor HNM2 is connected to the ground terminal of the inverter I1; The floating voltage domain includes PDMOS transistors HPM1, HPM2, HPM3, HPM4 and NMOS transistors NM1, NM2; The gate of the PDMOS transistor HPM1 is connected to the gate of the NMOS transistor NM1, the drain of the PDMOS transistor HPM1 is connected to the drain of the PDMOS transistor HPM3, and the source of the PDMOS transistor HPM1 is connected to the source of the PDMOS transistor HPM2; The gate of the PDMOS transistor HPM2 is connected to the gate of the NMOS transistor NM2, and the drain of the PDMOS transistor HPM2 is connected to the drain of the PDMOS transistor HPM4; The gate of the PDMOS transistor HPM3 is connected to the source of the NMOS transistor NM1, and the source of the PDMOS transistor HPM3 is connected to the drain of the NMOS transistor NM1; The gate of the PDMOS transistor HPM4 is connected to the source of the NMOS transistor NM2, and the source of the PDMOS transistor HPM4 is connected to the drain of the NMOS transistor NM2; The source of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM2.

2. The novel floating voltage level conversion circuit with high power conversion rate tolerance according to claim 1, characterized in that: The floating voltage domain also includes a cascade inverter; The cascade inverters are respectively composed of inverter I3, inverter I5, inverter I4 and inverter I2; The input end of the inverter I3 is connected to the source of the PDMOS transistor HPM4; The output end of the inverter I4 is connected to the gate of the PDMOS transistor HPM2, and the input end of the inverter I4 is connected to the output end of the inverter I2; The output end of the inverter I5 is connected to the gate of the NDMOS transistor HNM1 , and the input end of the inverter I5 is connected to the output end of the inverter I3 .

3. The novel floating voltage level conversion circuit with high power conversion rate tolerance according to claim 1 or 2, characterized in that: The drain of the NDMOS transistor HNM1 is connected to the drain of the PDMOS transistor HPM1; The drain of the NDMOS transistor HNM2 is connected to the drain of the PDMOS transistor HPM2.

4. The novel floating voltage level conversion circuit with high power conversion rate tolerance according to claim 1 or 2, characterized in that: The power supply terminal of the inverter I1 is connected to the voltage V DDL Connect the ground terminal of the inverter I1 to the voltage V SSL connect.

5. The novel floating voltage level conversion circuit with high power conversion rate tolerance according to claim 1 or 2, characterized in that: The source of the NMOS transistor NM1 and the source of the NMOS transistor NM2 are both connected to the voltage V SSH connect; The source of the PDMOS transistor HPM1 and the source of the PDMOS transistor HPM2 are both connected to the voltage V DDH connect.

6. The novel floating voltage level conversion circuit with high power conversion rate tolerance according to claim 1 or 2, characterized in that: The source of the PDMOS transistor HPM2 is connected to the power supply terminal of the inverter I2.

7. The novel floating voltage level conversion circuit with high power conversion rate tolerance according to claim 1 or 2, characterized in that: The output end of the inverter I2 is connected to the output level; The input end of the inverter I2 is connected to the source of the PDMOS transistor HPM3.

8. The novel floating voltage level conversion circuit with high power conversion rate tolerance according to claim 1, characterized in that: The source of the PDMOS transistor HPM4 is connected to the gate of the NMOS transistor NM1; The source of the PDMOS transistor HPM3 is connected to the gate of the NMOS transistor NM2 .

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