Channel decoding method and related circuit

Abstract

The invention provides a channel decoding method and a related circuit, and relates to the technical field of channel decoding, and the method comprises the steps: initializing a check node and a variable node of a low density parity check (LDPC) code; and performing iteration updating processing for multiple times, and judging the variable node based on the variable node information after iteration updating to obtain a decoding result. According to the embodiment of the invention, the hardware implementation difficulty of channel decoding can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of channel decoding, and in particular to a channel decoding method and related circuits. Background Art

[0002] In communication systems, channel coding is the key to improving information transmission efficiency, suppressing interference and transmission errors. In related technologies, during channel decoding, the transmission of confidence information mainly relies on the sum-product algorithm, which contains nonlinear functions such as hyperbolic functions, making it difficult to implement in hardware. Summary of the invention

[0003] The embodiment of the present invention provides a channel decoding method and related circuits to solve the problem that the hardware implementation of the channel decoding method in the prior art is relatively difficult.

[0004] To solve the above technical problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides a channel decoding method, the method comprising:

[0006] Initialize the check nodes and variable nodes of the low-density parity check LDPC code;

[0007] Perform multiple iterative update processes, and judge the variable nodes based on the variable node information after iterative update to obtain a decoding result;

[0008] Among them, the iterative update process is as follows:

[0009] Performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information when first calculated;

[0010] The modified first check node information is transformed by using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0011] Determine second variable node information based on the first intermediate verification information and the first variable node information;

[0012] The second variable node information is transformed by using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0013] The second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0014] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0015] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0016] The first variable is obtained by performing forward recursive processing on the check node information of the check node, and the second variable is obtained by performing backward recursive processing on the check node information of the check node.

[0017] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value of the absolute value of the first variable and the absolute value of the second variable.

[0018] In a second aspect, an embodiment of the present invention further provides a node update calculation circuit, wherein the node update calculation circuit is used to:

[0019] Performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation;

[0020] The modified first check node information is transformed by using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0021] Determine second variable node information based on the first intermediate verification information and the first variable node information;

[0022] The second variable node information is transformed by using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0023] The second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0024] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0025] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0026] The first variable is obtained by performing forward recursive processing on the check node information of the check node, and the second variable is obtained by performing backward recursive processing on the check node information of the check node.

[0027] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value of the absolute value of the first variable and the absolute value of the second variable.

[0028] Optionally, the node update calculation circuit includes:

[0029] a pre-calculation unit, the pre-calculation unit being used to calculate a sum of the first variable and the second variable, and a difference between the first variable and the second variable, and to determine a minimum value between an absolute value of the first variable and an absolute value of the second variable;

[0030] A selector, the selector being connected to the pre-computation unit, the selector being used to transmit first input data and second input data to the post-computation unit respectively, the first input data being an absolute value of a sum of the first variable and the second variable, and the second input data being an absolute value of a difference between the first variable and the second variable;

[0031] A post-calculation unit, the post-calculation unit is connected to the selector and the pre-calculation unit respectively, the post-calculation unit is used to perform a shift operation on the first input data and the second input data respectively, and determine second verification information based on the shifted first input data and the second input data.

[0032] Optionally, the post-calculation unit includes:

[0033] a shift subunit, the shift subunit being connected to the selector and configured to perform a shift operation on the first input data and the second input data respectively;

[0034] A product subunit, the product subunit is connected to the shift subunit, and the product subunit is used to calculate a first product of the shifted first input data and a preset value, and to calculate a second product of the shifted second input data and the preset value;

[0035] a first summing subunit, the first summing subunit being connected to the product subunit, and the first summing subunit being used to calculate a first sum value of the first product and the second product;

[0036] The second summing subunit is connected to the first summing subunit and the pre-calculation unit respectively, and is used to calculate the sum of the first sum and the minimum value, and the minimum value is the minimum value of the absolute value of the first variable and the absolute value of the second variable.

[0037] In a third aspect, an embodiment of the present invention further provides a channel decoding circuit, wherein the channel decoding circuit includes the node update calculation circuit described in the second aspect.

[0038] Optionally, the channel decoding circuit includes a control circuit, a check node update circuit, a variable node update circuit and a decoding intermediate variable circuit, and the check node update circuit and the variable node update circuit both include the node update calculation circuit;

[0039] The control circuit is connected to the check node update circuit, the variable node update circuit and the decoding intermediate variable circuit respectively; the decoding intermediate variable circuit is connected to the check node update circuit and the variable node update circuit respectively.

[0040] Optionally, the decoding intermediate variable circuit includes at least one data sub-flow unit and at least one control sub-flow unit, and the control sub-flow unit is used to control the data sub-flow unit to perform calculations.

[0041] Optionally, one of the control sub-flow units in the decoding intermediate variable circuit is used to control one or more of the data sub-flow units.

[0042] Optionally, the channel decoding circuit also includes a first memory, a second memory and a third memory, the first memory is respectively connected to the control circuit and the variable node update circuit, and the first memory is used to store decoding input information; the second memory is respectively connected to the control circuit, the variable node update circuit and the decoding intermediate variable circuit, and the second memory is used to store decoding output information; the third memory is respectively connected to the control circuit, the variable node update circuit and the check node update circuit, and the third memory is used to store the check matrix.

[0043] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the channel decoding method described in the first aspect.

[0044] In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the channel decoding method described in the first aspect are implemented.

[0045] In an embodiment of the present invention, the check nodes and variable nodes of a low-density parity check LDPC code are initialized; multiple iterative update processes are performed, and the variable nodes are judged based on the iteratively updated variable node information to obtain a decoding result; wherein, an iterative update process is performed as follows: based on the first check node information and the first variable node information of the check node, correction processing is performed to obtain the corrected first check node information, and the first variable node information is the initial channel information during the first calculation; the corrected first check node information is transformed using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; based on the first intermediate check information and the first variable node information, second variable node information is determined; the second variable node information is transformed using a Jacobian function to obtain second intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; based on the second intermediate check information and the corrected first check node information, second check node information is determined. In this way, the correction term in the Jacobian function used for updating the check node or the variable node is approximated as an exponential function, which can reduce the difficulty of hardware implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0047] Figure 1 It is a Tanner graph of LDPC decoding in the related art;

[0048] Figure 2 is a flow chart of a channel decoding method provided by an embodiment of the present invention;

[0049] Figure 3 is a schematic diagram of a Jacobian correction term curve provided by an embodiment of the present invention;

[0050] Figure 4 is a schematic diagram of an approximation curve of a correction term exponential approximation method provided by an embodiment of the present invention;

[0051] Figure 5 It is a structural diagram of a node update calculation circuit provided by an embodiment of the present invention;

[0052] Figure 6 It is a schematic diagram of a reconfigurable chip architecture provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] For ease of understanding, some contents involved in the embodiments of the present invention are described below:

[0055] 1. Wireless communication

[0056] For a long time, human beings have been pursuing efficient, reliable and secure information communication methods, which have given rise to a wide variety of communication tools and means, and have continuously promoted the development and progress of human society. With the birth, development and popularization of wireless communication, people can now easily enjoy the convenient services brought by wireless communication, and the production and living landscape of human beings has also undergone tremendous changes.

[0057] In the past few decades, the development of wireless communication technology and the popularization of smart terminals have brought about explosive growth in traffic and the number of devices. By the end of 2017, global wireless communication traffic reached 11.5EB per month (1EB = 103PB = 109GB), higher than 6.7EB per month at the end of 2016, an increase of 71%. Wireless communication traffic in the Asia-Pacific region accounted for 51% of global wireless communication traffic. Wireless communication traffic was 686PB per month in 2012, which has increased 17 times in the past five years. It is expected that by 2022, global wireless communication traffic will reach 77EB per month, and wireless communication traffic in the Asia-Pacific region will account for 55.7% of global wireless communication traffic, with a compound annual growth rate of 49%.

[0058] Globally, nearly 650 million mobile devices and connections were added in 2017, and the number of mobile devices and connections increased from 7.9 billion in 2016 to 8.6 billion, of which machine-to-machine (M2M) devices accounted for 11% of the total. Among the new connections in 2017, there were 526 million wearable devices, of which 19 million wearable devices were connected to mobile communication networks. It is estimated that by 2022, there will be 12.3 billion mobile connected devices worldwide, of which 33% will be M2M devices, and there will be 1.5 mobile devices per capita.

[0059] In the global wireless communication traffic, wireless local area network (WLAN) traffic accounted for 54% of the total mobile data traffic in 2017, exceeding mobile communication (MC). This part of data traffic is mainly transmitted through single-mode or dual-mode devices of Wi-Fi (Wireless Fidelity) networks and small base stations (Small Cell). Mobile communication is also called cellular communication (CC). It is expected that by 2022, 59% of the traffic will be generated from wireless local area network traffic. In mobile communication traffic, in 2017, the third generation mobile communication (3G) accounted for 30.0% of the connections and 21% of the mobile data traffic, the fourth generation mobile communication (4G) accounted for 35% of the connections and 72% of the mobile data traffic, and the fifth generation mobile communication (5G) accounted for 0% of the connections and 0% of the mobile data traffic. 5G technology is expected to be put into commercial operation in 2019. It is estimated that by 2022, the third generation of mobile communications (3G) will account for 19.8% of the connections and 17% of the mobile data traffic, the fourth generation of mobile communications (4G) will account for 54.3% of the connections and 71% of the mobile data traffic, and the fifth generation of mobile communications (5G) will account for 3.4% of the connections and 12% of the mobile data traffic. In wireless LAN traffic, the total number of public Wi-Fi hotspots (including public Wi-Fi commercial hotspots and home user points) worldwide in 2017 was 124 million, and it is expected to increase to 549 million by 2022.

[0060] It can be seen that with the rapid growth of wireless data, mobile communications and wireless LANs will become an important part of global wireless communication traffic for a long time in the future. At the same time, the rapidly growing data traffic demand also puts higher requirements on the capacity of wireless networks. In addition to adding new frequency bands, improving spectrum efficiency, and measures such as carrier aggregation (CA), small cell technology has been proposed to reduce signal blind spots and improve signal quality. Compared with the deployment difficulty and cost of macro base stations, it has the advantages of large-scale deployment. Small cell technology has been widely used in LTE technology and has become a powerful supplement to the signal coverage of macro base stations.

[0061] In the development of wireless communication, the innovation of baseband algorithm and Very Large Scale Integration (VLSI) technology have made the realization of System on Chip (SoC) suitable for wireless communication a reality, which provides a chip-level solution of Application Specific Integrated Circuit (ASIC) for the baseband physical layer, making it possible to miniaturize and facilitate wireless communication equipment. Therefore, it is of great value to the research of wireless communication technology and VLSI realization.

[0062] 2. Channel coding

[0063] In 1948, CE Shannon published a paper of great significance in the history of communication research, "A Mathematical Theory of Communication", which proposed the model of the communication system for the first time. At the same time, he proposed that the balance between the effectiveness and reliability of the processing system is the key to the communication system, ensuring the efficiency of information transmission and suppressing interference and transmission errors, and channel coding is an important method to achieve this function. In the paper, the noisy channel coding theorem was proposed, which opened up the research on channel coding.

[0064] 3. Low Density Parity Check (LDPC) Code

[0065] In 1962, MIT scholar Gallager first proposed LDPC codes. However, due to the lack of hardware conditions and other reasons, this achievement has not been taken seriously and paid attention to. In the 1990s, French scholar Berrou et al. proposed and constructed Turbo codes, which approached the Shannon limit of the channel and set off a new wave of research on channel coding. Under the influence of Turbo code research, Mackay et al. re-proposed and studied LDPC codes. During this period, Tanner proposed a bipartite graph model ("Tanner graph") in 1981, which provided an intuitive and efficient tool for the subsequent graph model research of LDPC codes. Since the LDPC code was re-proposed, it has been proved to have excellent performance close to the Shannon limit, becoming one of the important hotspots in the field of channel coding.

[0066] LDPC codes (Low Density Parity Check Codes), or low-density parity check codes, have a very sparse check matrix as one of their most notable features. The proportion of non-zero elements in the check matrix of LDPC codes decreases as the code length increases, and they have a typical sparse characteristic. Theoretical analysis can prove that the sparse characteristic of the check matrix is ​​one of the important reasons why LDPC codes have excellent performance, which allows decoding to be performed effectively even when the code length is long.

[0067] 4. LDPC code decoding algorithm

[0068] The decoding algorithms of LDPC codes can be divided into hard decision decoding algorithms and soft decision decoding algorithms. The former is the bit flipping (BF) decoding algorithm, which has low complexity and is easy to implement in hardware, but has poor decoding performance and is only applicable to communication systems with excellent channel quality; the latter refers to the belief propagation (BP) decoding algorithm based on a posteriori probability calculation, which has performance close to the maximum likelihood decoding algorithm and is widely used. The iterative decoding algorithm of LDPC codes is relatively simple to implement, and its complexity is linear with the code length, which is conducive to hardware implementation.

[0069] 4.1 Hard Decision Decoding Algorithm

[0070] Assume that the signal transmission information sequence is X = {x0, x1, ..., x n-1}, the received information sequence after passing through the channel is Y = {y0,y1,…,y n-1}. The decoding process is as follows:

[0071] (1) First, determine the channel transmission message and obtain the bit sequence;

[0072] (2) Substitute the result of step (1) into the verification equation for calculation. If the verification equation holds, stop the iteration and the decoding is successful. Otherwise, find the variable node with the largest number of invalid values ​​and flip all its bits uniformly.

[0073] (3) If the verification equation in step (2) does not hold, substitute the flipped judgment result into the verification equation again, calculate its verification result, and repeat step (2) until all verification equations hold or the maximum number of iterations is reached.

[0074] The problem with this algorithm is that after a certain iteration, if there are multiple nodes with the largest number of invalid nodes, they will flip at the same time, resulting in a high error rate. At present, some studies have proposed some improvements to the BF algorithm, such as adding certain weights to variable nodes, but the performance is average. Therefore, this algorithm is only suitable for situations with good channel conditions such as optical fiber communication.

[0075] 4.2 Soft Decision Decoding Algorithm

[0076] The soft decision decoding algorithm of LDPC code is a research hotspot in communication system. The decoding of LDPC code is an iterative algorithm based on probability message passing, and its implementation in logarithmic domain is usually called Sum Product Algorithm (SPA).

[0077] The mean is 0 and the variance is σ 2 The additive white Gaussian noise channel (AWGN) is analyzed under the condition of binary phase shift keying (BPSK) modulation. The dimension of the check matrix H is M×N. The signal transmission information sequence is X={x0,x1,…,x n-1}, the received information sequence after passing through the channel is Y = {y0,y1,…,y n-1}, l max is the maximum number of iterations. Figure 1 In the example, v is a variable node and c is a check node. The related concepts are defined as follows: ①M(j) represents the set of check nodes linked to variable node j; ②N(i) represents the set of variable nodes linked to check node i; ③N(i)\j represents N(i) after removing element j; ④M(j)\i represents M(j) after removing element i; ⑤ It is a modulo-2 operation; ⑥ The channel initially receives information represents the probability that the transmission variable xj takes the value a∈{1,-1}; ⑦ Check node c i To variable node v j The verification information sent is used Indicates that the variable node v j To the check node c i The variable information transmitted is used express.

[0078] The steps of LDPC code soft decision decoding are as follows:

[0079] (1) Initialization: l = 0, initialize the information of each LDPC code check node and variable node, and initialize the receiving value of the channel

[0080] (2) Iterative message update and delivery:

[0081] Step 1 (check node update): For check node c i Connected variable node v j , j∈N(i), send verification information one by one Variable node vj To receive information and the initial value of the channel Based on the correction

[0082] Step 2 (variable node update): For variable node v j Each check node c connected i , i∈M(j), transmit variable information one by one Check Node c i To receive information Based on the correction

[0083] (3) Judgment and decoding attempt:

[0084] Each variable node v j Receiving information and the initial value received by the channel Calculated based on And for the variable node v j The decoding result is obtained. Order decision codeword otherwise The resulting decision codeword is x = [x1, x2, ..., x N ], if the decoding check formula is satisfied, stop iterative decoding, declare the decoding successful, and output x as the decoding result, otherwise return to step (2) to continue execution. max , terminate the decoding operation.

[0085] In the above steps, during the first iteration, check node c i For other variable nodes v j of The message is unknown, and the variable message value it transmits is calculated with equal probability, that is, Initialized to 0.

[0086] For the LDPC decoding algorithm, the update calculation operation of the above iterative decoding varies with the different metrics of message passing. In general, the common sum-product decoding algorithm metrics are divided into two types: probability-based and log-likelihood ratio-based. The sum-product decoding algorithm based on probability metric requires multipliers for information transmission between nodes, which is not easy to implement in hardware. Therefore, we focus on introducing and using the sum-product decoding algorithm based on log-likelihood ratio measurement.

[0087] Under the sum-product decoding algorithm of log-likelihood ratio measure, Initialized to 0. The initial probability of the prior information of xj = a is In the decoding iteration process, information is transmitted in the form of log likelihood ratio (LLR). When updating the calculation, addition operation is used instead of multiplication operation of probability measure, and normalization is not required. The common information update formula is as follows:

[0088] f j =L(x j |y j )=log(P(x j =0|y j ) / P(x j =1|y j ))=2y j / σ 2

[0089]

[0090] The value of the log-likelihood ratio measure of the decoded symbol received information is:

[0091]

[0092] When making a decoding decision, if Q j If ≥0, the received signal judgment is 1, otherwise it is 0.

[0093] 4.3. Sum-Product Algorithm

[0094] For the SPA algorithm, when LLR is used as information measurement for transmission, in order to simplify the operation and improve efficiency, there are a series of implementation methods for the update operation of the check node. Several common LLR-SPA algorithms are discussed below.

[0095] (1) Sum-product algorithm based on Tanh rule

[0096]

[0097] (2) Sum-product algorithm based on Gallager function

[0098]

[0099] (3) Sum-product algorithm based on Jacobian function

[0100] The aforementioned Tanh rule can also be expressed as follows:

[0101]

[0102] This transformation is also called Jacobian transformation. i , there is c variable node vj Connected to it, the input variable information is Two auxiliary set definitions are proposed: and

[0103] Using auxiliary collections, you can get variable information from the input Output information is obtained from and We can get:

[0104]

[0105] The update formula of the check node is transformed into:

[0106]

[0107] This algorithm is essentially a forward-backward recursive decoding algorithm for a single parity-check code.

[0108] In general, the sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, which makes it difficult to implement in hardware.

[0109] 4.4 Minimum Sum Algorithm

[0110] In order to reduce the complexity of LDPC decoding implementation, Fossorier et al. simplified the annoying check node processing flow in the sum-product algorithm, eliminated this type of nonlinear function, and obtained the classic minimum sum (MS) algorithm, which only performs addition and comparison operations when calculating the check node information update, which is conducive to hardware implementation. The understanding of these simplified algorithms can be inspired by the analysis of the Jacobian algorithm. The MS algorithm simplifies the check node information processing in the sum-product decoding algorithm as follows:

[0111]

[0112] Applying this approximation to the iterative decoding process of LDPC, the calculation formula for updating the check node information is transformed into:

[0113]

[0114] According to the above formula, the MS algorithm can perform decoding operations with only the minimum sign and amplitude of the information transmitted by the node. The method for finding the minimum value can generally use the binary tree method. The MS algorithm verifies that the node information update is only based on the sign of the transmitted information and the minimum modulus value, which greatly simplifies the complexity of hardware implementation. However, the amplitude of many variable information transmissions is ignored during the decoding process, resulting in performance loss. In order to compensate for the performance loss, scholars have proposed corresponding offset measures, namely the Normalized Min Sum (NMS) decoding algorithm and the Offset Min Sum (OMS) algorithm as improvements.

[0115] 4.5. Normalized Minimum Sum Algorithm

[0116] The Normalized Min Sum (NMS) decoding algorithm is an improved decoding algorithm based on the MS algorithm. The minimum value of the transmitted information in the check node information update can be multiplied by a value α less than 1. At this time, the formula for updating the check node information is:

[0117]

[0118] From the perspective of optimization, α should change with different decoding environments and iteration times to obtain the optimal decoding result. However, for the convenience of implementation, common NMS algorithms usually take α as a constant, and its value can be estimated using the density evolution (DE) method.

[0119] 4.6 Minimum Sum Algorithm with Offset

[0120] The Offset Min Sum (OMS) algorithm is an improved decoding algorithm based on the MS algorithm. The minimum value obtained by transferring information in the check node information update can be subtracted by a value β. At this time, the formula for updating the check node information is:

[0121]

[0122] From the perspective of optimization, β should change with different decoding environments and iteration times to obtain the best decoding result. However, for the convenience of implementation, the common OMS algorithm usually takes β as a constant. The improvement of this method over the NMS algorithm is that information with an amplitude less than β will be set to zero, and the impact on the update of the variable node in the next iteration will be ignored.

[0123] It can be seen that the MS algorithm, OMS algorithm and NMS algorithm only need the channel reception value as input, and do not require channel-related information.

[0124] In the existing channel decoding schemes, the transmission of confidence information mainly relies on the sum-product algorithm, the minimum sum algorithm, the normalized minimum sum algorithm, and the minimum sum algorithm with offset.

[0125] The sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, which makes it difficult to implement in hardware.

[0126] The minimum sum algorithm verifies that node information is updated only by the sign of the transmitted information and the minimum modulus value, which greatly simplifies the complexity of hardware implementation. However, the amplitude of many variable information transmissions is ignored during the decoding process, resulting in performance loss.

[0127] The normalized minimum sum decoding algorithm is based on the minimum sum algorithm to obtain the minimum value of the transmitted information in the check node information update multiplied by a value less than 1, but since more channel information is omitted, there is still room for improvement in performance.

[0128] The minimum sum decoding algorithm with offset is based on the minimum sum algorithm to obtain the minimum value of the transmitted information in the check node information update minus an offset value, but since more channel information is omitted, there is still room for improvement in performance.

[0129] In the embodiment of the present invention, a channel decoding method and related circuits are proposed to solve the problem that the hardware implementation of the channel decoding method in the prior art is relatively difficult.

[0130] See also Figure 2 , Figure 2 is a flow chart of a channel decoding method provided by an embodiment of the present invention, such as Figure 2 As shown, the method comprises the following steps:

[0131] Step 101: Initialize the check nodes and variable nodes of the low-density parity check LDPC code.

[0132] Among them, the channel decoding method can be used to implement LDPC code soft decision decoding.

[0133] Step 102, performing multiple iteration update processes, judging the variable nodes based on the variable node information after the iteration update, and obtaining a decoding result;

[0134] Among them, the iterative update process is as follows:

[0135] Performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information when first calculated;

[0136] The modified first check node information is transformed by using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0137] Determine second variable node information based on the first intermediate verification information and the first variable node information;

[0138] The second variable node information is transformed by using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0139] The second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0140] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0141] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0142] The first variable is obtained by performing forward recursive processing on the check node information of the check node, and the second variable is obtained by performing backward recursive processing on the check node information of the check node.

[0143] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value of the absolute value of the first variable and the absolute value of the second variable.

[0144] It should be noted that the core operation of the sum-product algorithm based on the Jacobian function is to introduce the Jacobian transform into the SPA algorithm of LDPC decoding to obtain the following Jacobian function:

[0145]

[0146] This transformation is also called Jacobian transformation. i , there is cvariable node v j Connected to it, the input variable information is Two auxiliary set definitions are proposed: and It can be considered as the first variable (ie, L(U)) obtained by forward recursive processing of the variable node information of the variable node or the check node information of the check node. It can be considered as the second variable (ie, L(V)) obtained by performing backward recursive processing on the variable node information of the variable node or the check node information of the check node. sign(L(U))sign(L(V))min{|L(U)|,|L(V)|} is the target subfunction.

[0147] Taking the update of the check node as an example, the input information passed from the variable node can be Output information is obtained from and The update formula of the check node is:

[0148]

[0149] To further simplify the processing, the following functions can be extracted for analysis:

[0150] f c (x) = log(1 + e -x );

[0151] This function is also called the Jacobian correction term, where x>0. Figure 3 is the correction term f c (x) curve, f c (x) is a monotonically decreasing function with respect to x in the region greater than 0. When x is 0, it reaches the maximum value ln(2)≈0.693147, and when x is 5, the value is 0.006715. Generally, when x is greater than 5, its value is set to 0. The analysis below is also basically in the interval 0≤x≤5.

[0152] Since the correction term itself is a nonlinear function, by observing the curve characteristics of the Jacobian correction term, this embodiment proposes a nonlinear approximation method, and the approximation formula is as follows:

[0153]

[0154] In the embodiment of the present invention, the Jacobian correction term is approximately: Therefore, the correction term log(1+exp{-|L(U)+L(V)|}) in the Jacobian function can be approximated as: That is, the first correction term; the correction term log(1+exp{-|L(U)-L(V)|} in the Jacobian function can be approximated as: This method has high approximation accuracy, and the exponential operation can be completed through hardware shift operation. Figure 4 The curves of the Jacobian correction term using the exponential approximation method and the ideal correction term are drawn. It can be seen that the proposed method has good fitting characteristics.

[0155] The embodiment of the present invention proposes a new confidence information transmission scheme in channel decoding, which is applicable to channel decoding taking LDPC code as an example. The correction term is approached by exponential fitting to achieve fast, high-precision, and easy-to-hardware channel decoding, and its hardware circuit is designed. This scheme is also applicable to POLAR, fountain code, etc.

[0156] In an embodiment of the present invention, the check nodes and variable nodes of a low-density parity check LDPC code are initialized; multiple iterative update processes are performed, and the variable nodes are judged based on the iteratively updated variable node information to obtain a decoding result; wherein, an iterative update process is performed as follows: based on the first check node information and the first variable node information of the check node, correction processing is performed to obtain the corrected first check node information, and the first variable node information is the initial channel information during the first calculation; the corrected first check node information is transformed using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; based on the first intermediate check information and the first variable node information, second variable node information is determined; the second variable node information is transformed using a Jacobian function to obtain second intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; based on the second intermediate check information and the corrected first check node information, second check node information is determined. In this way, the correction term in the Jacobian function used for updating the check node or the variable node is approximated as an exponential function, which can reduce the difficulty of hardware implementation.

[0157] The embodiment of the present invention further provides a node update calculation circuit, wherein the node update calculation circuit is used to:

[0158] Performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation;

[0159] The modified first check node information is transformed by using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0160] Determine second variable node information based on the first intermediate verification information and the first variable node information;

[0161] The second variable node information is transformed by using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term;

[0162] The second check node information is determined based on the second intermediate check information and the corrected first check node information.

[0163] Optionally, the Jacobian correction term includes a first correction term and a second correction term, the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable;

[0164] The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or

[0165] The first variable is obtained by performing forward recursive processing on the check node information of the check node, and the second variable is obtained by performing backward recursive processing on the check node information of the check node.

[0166] Optionally, the Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value of the absolute value of the first variable and the absolute value of the second variable.

[0167] Optionally, the node update calculation circuit includes:

[0168] a pre-calculation unit, the pre-calculation unit being used to calculate a sum of the first variable and the second variable, and a difference between the first variable and the second variable, and to determine a minimum value between an absolute value of the first variable and an absolute value of the second variable;

[0169] A selector, the selector being connected to the pre-computation unit, the selector being used to transmit first input data and second input data to the post-computation unit respectively, the first input data being an absolute value of a sum of the first variable and the second variable, and the second input data being an absolute value of a difference between the first variable and the second variable;

[0170] A post-calculation unit, the post-calculation unit is connected to the selector and the pre-calculation unit respectively, the post-calculation unit is used to perform a shift operation on the first input data and the second input data respectively, and determine second verification information based on the shifted first input data and the second input data.

[0171] Optionally, the post-calculation unit includes:

[0172] a shift subunit, the shift subunit being connected to the selector and configured to perform a shift operation on the first input data and the second input data respectively;

[0173] A product subunit, the product subunit is connected to the shift subunit, and the product subunit is used to calculate a first product of the shifted first input data and a preset value, and to calculate a second product of the shifted second input data and the preset value;

[0174] a first summing subunit, the first summing subunit being connected to the product subunit, and the first summing subunit being used to calculate a first sum value of the first product and the second product;

[0175] The second summing subunit is connected to the first summing subunit and the pre-calculation unit respectively, and is used to calculate the sum of the first sum and the minimum value, and the minimum value is the minimum value of the absolute value of the first variable and the absolute value of the second variable.

[0176] As a specific embodiment, Figure 5 As shown, the check node update operation will first perform addition and subtraction operations on L(U) and L(V) synchronously, and at the same time, the smaller value of L(U) and L(V) will be obtained according to the sign of the result of the subtraction operation. The calculated value will be used to read the corresponding parameters in the LUT and perform segment selection, multiplication and addition operations. The selector will control |L(U)+L(V)| and |L(U)-L(V)| to enter the post-calculation unit independently in sequence. In the post-calculation unit, its core operation is to complete the shift operation of the input data according to the input variable x, and multiply it by the constant log2 of the algorithm. After the calculation is completed, the calculation results of |L(U)+L(V)| and |L(U)-L(V)| are added to complete the calculation of the update information of a single check node.

[0177] In the whole process of updating the verification node information, such calculation operations need to be repeated and iterated, and finally all the node transmission information is fed back to the verification node to complete the whole information aggregation work.

[0178] In an embodiment of the present invention, the node update calculation circuit is used to: perform correction processing based on the first check node information and the first variable node information of the check node to obtain the corrected first check node information, wherein the first variable node information is the initial channel information during the first calculation; transform the corrected first check node information using the Jacobian function to obtain the first intermediate check information, wherein the Jacobian function includes the Jacobian correction term, and the Jacobian correction term is an exponential function term; determine the second variable node information based on the first intermediate check information and the first variable node information; transform the second variable node information using the Jacobian function to obtain the second intermediate check information, wherein the Jacobian function includes the Jacobian correction term, and the Jacobian correction term is an exponential function term; determine the second check node information based on the second intermediate check information and the corrected first check node information. In this way, in the process of updating the check node or variable node, the correction term of the Jacobian function is approached by exponential fitting, and the node update calculation circuit can realize fast, high-precision, and easy-to-hardware channel decoding.

[0179] An embodiment of the present invention further provides a channel decoding circuit, which includes the node update calculation circuit described in the embodiment of the present invention.

[0180] Optionally, the channel decoding circuit includes a control circuit, a check node update circuit, a variable node update circuit and a decoding intermediate variable circuit, and the check node update circuit and the variable node update circuit both include the node update calculation circuit;

[0181] The control circuit is connected to the check node update circuit, the variable node update circuit and the decoding intermediate variable circuit respectively; the decoding intermediate variable circuit is connected to the check node update circuit and the variable node update circuit respectively.

[0182] Optionally, the decoding intermediate variable circuit includes at least one data sub-flow unit and at least one control sub-flow unit, and the control sub-flow unit is used to control the data sub-flow unit to perform calculations.

[0183] Optionally, one of the control sub-flow units in the decoding intermediate variable circuit is used to control one or more of the data sub-flow units.

[0184] Optionally, the channel decoding circuit also includes a first memory, a second memory and a third memory, the first memory is respectively connected to the control circuit and the variable node update circuit, and the first memory is used to store decoding input information; the second memory is respectively connected to the control circuit, the variable node update circuit and the decoding intermediate variable circuit, and the second memory is used to store decoding output information; the third memory is respectively connected to the control circuit, the variable node update circuit and the check node update circuit, and the third memory is used to store the check matrix.

[0185] As a specific embodiment, for high-bandwidth, low-latency channel coding (Channel Code), the embodiment of the present invention proposes a reconfigurable chip architecture suitable for its hardware implementation. The proposed reconfigurable channel coding architecture is as follows: Figure 6 In the present embodiment, a reconfigurable decoding stream concept is proposed, which divides the data inside the decoder into multiple parallel reconfigurable data streams, including at least a data decoding stream (such as Figure 6 Calculator part in M_UNIT) and control decoding flow (such as Figure 6 The SHIFTControl part in M_UNIT in the figure), each decoding stream can also be divided into multiple decoding sub-streams, and each decoding sub-stream is used to control the data flow or control process of the corresponding computing unit. For the reconfigurable decoding structure proposed in the embodiment of the present invention, the control sub-stream is mainly used to adjust the shift operation depth, which can be further extended to other reconfigurable parameter configuration information. Furthermore, the embodiment of the present invention proposes a reconfigurable multi-sub-stream mixing mechanism, that is, multiple data decoding sub-streams such as M can form a one-to-one or many-to-one mapping with multiple control decoding sub-streams such as N, which can further reduce the hardware overhead brought by the data sub-stream and improve the decoding speed, wherein the data decoding sub-stream can be implemented by the data sub-stream unit (Calculator), and the control decoding sub-stream can be implemented by the control sub-stream unit (SHIFTControl). Specifically, such as Figure 6 As shown, the entire decoder module mainly includes a control circuit Decoder_Controller, a check node update circuit CNU_UNIT, a variable node update circuit VNU_UNIT, a decoding intermediate variable circuit M_UNIT, and a first memory RAM_IN for storing decoding input information, a second memory RAM_OUT for storing decoding output information, and a third memory ROM_H for storing a check matrix. The approximation algorithm proposed in the embodiment of the present invention is mainly implemented in the decoding intermediate variable unit M_UNIT. Figure 6As shown, a feasible reconfigurable configuration method is that data substream 1, Calculator_1, is configured by control substream 1, SHIFTControl1, data substream 2, Calculator_2, is configured by control substream 2, SHIFTControl2, and so on, one to one matching; another feasible reconfigurable configuration method is that data substream 1, Calculator_1, data substream 2, Calculator_2 to data substream M, Calculator_M, are all configured by control substream 1, SHIFTControl1, and another group of data substreams M+1, Calculator_M+1, data substream M+2, Calculator_M+2 to data substream M+N, Calculator_M+N, are all configured by control substream 2, SHIFTControl2, which can reduce the number of control substream configurations required for decoding calculations, and the mapping relationship between data substreams and configuration substreams is regulated by Decoder_controller. Reconstruction conversion is supported between multiple substreams, that is, the decoding substream used for the data path can also be converted into the control path substream, and vice versa.

[0186] The reconfigurable chip architecture suitable for high-bandwidth, low-latency channel coding proposed in this embodiment, as well as the mapping relationship between multiple decoding sub-streams and sub-streams and the reconfigurable conversion mechanism in the architecture can further improve the decoding rate.

[0187] The embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, each process of the channel decoding method embodiment described above is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. The computer-readable storage medium is, for example, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0188] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0189] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0190] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A channel decoding method, characterized in that: The method comprises: Initialize the check nodes and variable nodes of the low-density parity check LDPC code; Perform multiple iterative update processes, and judge the variable nodes based on the variable node information after iterative update to obtain a decoding result; Among them, the iterative update process is as follows: Performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information when first calculated; The modified first check node information is transformed by using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; Determine second variable node information based on the first intermediate verification information and the first variable node information; The second variable node information is transformed by using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; The second check node information is determined based on the second intermediate check information and the corrected first check node information.

2. The method according to claim 1, characterized in that The Jacobian correction term includes a first correction term and a second correction term, wherein the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable; The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or The first variable is obtained by performing forward recursive processing on the check node information of the check node, and the second variable is obtained by performing backward recursive processing on the check node information of the check node.

3. The method according to claim 2, characterized in that The Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

4. A node update calculation circuit, characterized in that: The node update calculation circuit is used for: Performing correction processing based on first check node information and first variable node information of the check node to obtain corrected first check node information, wherein the first variable node information is initial channel information during the first calculation; The modified first check node information is transformed by using a Jacobian function to obtain first intermediate check information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; Determine second variable node information based on the first intermediate verification information and the first variable node information; The second variable node information is transformed by using a Jacobian function to obtain second intermediate verification information, wherein the Jacobian function includes a Jacobian correction term, and the Jacobian correction term is an exponential function term; The second check node information is determined based on the second intermediate check information and the corrected first check node information.

5. The node update calculation circuit according to claim 4, characterized in that: The Jacobian correction term includes a first correction term and a second correction term, wherein the first correction term is an exponential function term of the absolute value of the sum of the first variable and the second variable, and the second correction term is an exponential function term of the absolute value of the difference between the first variable and the second variable; The first variable is obtained by performing forward recursive processing on the variable node information of the variable node, and the second variable is obtained by performing backward recursive processing on the variable node information of the variable node; or The first variable is obtained by performing forward recursive processing on the check node information of the check node, and the second variable is obtained by performing backward recursive processing on the check node information of the check node.

6. The node update calculation circuit according to claim 5, characterized in that: The Jacobian function is the sum of the Jacobian correction term and a target sub-function, the target sub-function is the product of the sign function of the first variable, the sign function of the second variable and a minimum function, and the minimum function is the minimum value between the absolute value of the first variable and the absolute value of the second variable.

7. The node update calculation circuit according to claim 5 or 6, characterized in that: The node update calculation circuit comprises: a pre-calculation unit, the pre-calculation unit being used to calculate a sum of the first variable and the second variable, and a difference between the first variable and the second variable, and to determine a minimum value between an absolute value of the first variable and an absolute value of the second variable; A selector, the selector being connected to the pre-computation unit, the selector being used to transmit first input data and second input data to the post-computation unit respectively, the first input data being an absolute value of a sum of the first variable and the second variable, and the second input data being an absolute value of a difference between the first variable and the second variable; A post-calculation unit, the post-calculation unit is connected to the selector and the pre-calculation unit respectively, the post-calculation unit is used to perform a shift operation on the first input data and the second input data respectively, and determine second verification information based on the shifted first input data and the second input data.

8. The node update calculation circuit according to claim 7, characterized in that: The post-calculation unit comprises: a shift subunit, the shift subunit being connected to the selector and configured to perform a shift operation on the first input data and the second input data respectively; A product subunit, the product subunit is connected to the shift subunit, and the product subunit is used to calculate a first product of the shifted first input data and a preset value, and to calculate a second product of the shifted second input data and the preset value; a first summing subunit, the first summing subunit being connected to the product subunit, and the first summing subunit being used to calculate a first sum value of the first product and the second product; The second summing subunit is connected to the first summing subunit and the pre-calculation unit respectively, and is used to calculate the sum of the first sum and the minimum value, and the minimum value is the minimum value of the absolute value of the first variable and the absolute value of the second variable.

9. A channel decoding circuit, characterized in that: The channel decoding circuit comprises the node update calculation circuit according to any one of claims 4-8.

10. The channel decoding circuit according to claim 9, characterized in that: The channel decoding circuit includes a control circuit, a check node update circuit, a variable node update circuit and a decoding intermediate variable circuit, and the check node update circuit and the variable node update circuit both include the node update calculation circuit; The control circuit is connected to the check node update circuit, the variable node update circuit and the decoding intermediate variable circuit respectively; the decoding intermediate variable circuit is connected to the check node update circuit and the variable node update circuit respectively.

11. The channel decoding circuit according to claim 10, characterized in that: The decoding intermediate variable circuit includes at least one data sub-flow unit and at least one control sub-flow unit, and the control sub-flow unit is used to control the data sub-flow unit to perform calculations.

12. The channel decoding circuit according to claim 11, characterized in that: One of the control sub-flow units in the decoding intermediate variable circuit is used to control one or more of the data sub-flow units.

13. The channel decoding circuit according to claim 10, characterized in that: The channel decoding circuit also includes a first memory, a second memory and a third memory, the first memory is connected to the control circuit and the variable node update circuit respectively, and the first memory is used to store decoding input information; the second memory is connected to the control circuit, the variable node update circuit and the decoding intermediate variable circuit respectively, and the second memory is used to store decoding output information; the third memory is connected to the control circuit, the variable node update circuit and the check node update circuit respectively, and the third memory is used to store the check matrix.

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