Semiconductor structure and preparation method thereof
By designing the gate accommodating grooves on the side walls of the channel region in the semiconductor structure and filling the gate, the problem of gate control capability reduction caused by the reduction of the characteristic size of the vertical channel array transistor is solved, and the read and write speed and electrical performance of DRAM are improved .
Patent Information
- Application Number
- CN202310789597.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-29
- Publication Date
- 2024-12-31
AI Technical Summary
As the characteristic size of vertical channel array transistors decreases, the gate control capability weakens, affecting DRAM read and write speed and power consumption performance. How to optimize gate control capability has become an urgent problem.
By designing the channel region side wall in the semiconductor structure with a gate accommodating groove and filling the gate in the groove, the contact area between the gate and the channel region is increased, thereby enhancing the gate's control ability to the semiconductor structure and improving the switch ratio and electrical properties.
In the case of occupying the same substrate area, the number of active columns and gates is increased, space utilization is improved, gate control capabilities are enhanced, leakage current is reduced, and switching ratio and electrical performance of semiconductor devices are improved.
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Figure CN119233629A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] With the development of dynamic random access memory (DRAM) technology, the size of storage cells is getting smaller and smaller, and its array architecture is from 8F to 2 Go to 6F 2 Then to 4F 2 (F: minimum pattern size obtainable under given process conditions).
[0003] In order to reduce the area of transistors in a single array area as much as possible and pursue higher chip area utilization, vertical channel array transistor (VCT) technology has emerged. However, as the feature size continues to shrink, the VCT gate control capability will weaken, affecting the transistor's switching ratio and subthreshold swing, and thus affecting DRAM read and write speed and power consumption. Therefore, in the face of the continuous reduction of VCT feature size, how to optimize the VCT gate control capability is a problem that needs to be solved urgently. Summary of the invention
[0004] Based on this, the present application provides a semiconductor structure and a method for preparing the same, in order to address the deficiencies in the prior art.
[0005] In one aspect, the present application provides a semiconductor structure, comprising:
[0006] A substrate; the substrate comprises a plurality of active pillars arranged in an array, the active pillars comprise a channel region, and the sidewalls of the channel region have a gate accommodating groove;
[0007] A plurality of gates; the gates cover the channel regions corresponding to the active pillars, and the gates at least fill the gate receiving grooves.
[0008] In some embodiments, the gate includes a first portion filled in the gate receiving groove;
[0009] The first portion of the gate includes an upper surface and a lower surface parallel to the substrate, and a side surface connecting the upper surface and the lower surface.
[0010] In some embodiments, the side surface is perpendicular to the upper surface and the lower surface.
[0011] In some embodiments, the ratio of the depth of the gate receiving groove to the radial dimension of the active pillar is in a range of 1 / 5 to 1 / 3.
[0012] In some embodiments, the gate further includes a second portion connected to the first portion;
[0013] The second portion of the gate is located on the side wall of the channel region, and its orthographic projection on the active pillar covers the gate receiving groove.
[0014] In some embodiments, a ratio of a size of the second portion of the gate in a direction perpendicular to the substrate to a size of the first portion of the gate in a direction perpendicular to the substrate is in a range of 1.5-2.
[0015] In some embodiments, the semiconductor structure further includes: a gate dielectric layer; the gate dielectric layer at least conformally covers the inner wall of the gate receiving groove;
[0016] The gate is located on a surface of the gate dielectric layer away from the active pillar.
[0017] On the other hand, the present application also provides a method for preparing a semiconductor structure, comprising:
[0018] A substrate is provided; a plurality of active pillars arranged in an array are formed on a surface of one side of the substrate, the active pillars are formed with a channel region, and a gate accommodating groove is formed on a sidewall of the channel region;
[0019] A plurality of gates are formed; the gates cover the channel regions of the active pillars in the same row and at least fill the gate receiving grooves.
[0020] In some embodiments, providing a substrate comprises:
[0021] Etching the substrate to form a plurality of initial active pillars arranged in an array on a surface of one side of the substrate; the initial active pillars are formed with initial channel regions;
[0022] A plurality of spaced bit lines are formed in the substrate; each of the bit lines extends along the second direction and is spaced along the first direction, and is located below the initial active pillars, so as to sequentially connect the initial active pillars located in the same row along the second direction; the second direction intersects the first direction;
[0023] The initial active column is etched to form a gate accommodating groove in the initial channel region; the retained initial active column is used as the active column, and the retained initial channel region is used as the channel region; the gate accommodating groove includes a first surface and a second surface parallel to the substrate, and a third surface connecting the first surface and the second surface.
[0024] In some embodiments, forming a plurality of gates includes:
[0025] The first part of the gate is filled in the gate receiving groove, and the second part of the gate is formed on the side wall of the channel region; the second part is connected to the first part, and its orthographic projection on the active pillar covers the gate receiving groove.
[0026] In some embodiments, before forming the plurality of gates, the method for preparing the semiconductor structure further includes: conformally covering the inner wall of the gate accommodating groove with a gate dielectric layer.
[0027] The semiconductor structure and the method for preparing the same provided by the present application have at least the following beneficial effects:
[0028] In the embodiment of the present application, the gate is arranged in a manner of covering the active pillar channel region, so that more active pillars and gates can be arranged under the premise of occupying the same substrate area, thereby improving the space utilization rate, which is beneficial to improving the device integration and storage density. In the embodiment of the present application, the side wall of the channel region has a gate accommodating groove, and the gate is filled in the gate accommodating groove, which can increase the contact area between the gate and the channel region, which is beneficial to enhancing the gate control ability of the gate to the semiconductor structure, and can reduce the leakage current, thereby making the semiconductor structure have a higher switching ratio, which is beneficial to improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0030] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor structure provided in some embodiments of the present application;
[0031] Figure 2 FIG. (a) is a graph showing the relationship between the subthreshold swing amplitude and the gate receiving groove depth in the semiconductor structure provided by some embodiments of the present application; Figure 2 FIG. (b) is a graph showing the relationship between the subthreshold swing amplitude and the size change of the first portion of the gate in a direction perpendicular to the substrate in the semiconductor structure provided by some embodiments of the present application;
[0032] Figure 3 Figure (a) is a graph showing the relationship between the switching ratio and the gate receiving groove depth in the semiconductor structure provided by some embodiments of the present application; Figure 3 FIG. (b) is a graph showing the relationship between the switching ratio and the size of the first portion of the gate in a direction perpendicular to the substrate in a semiconductor structure provided by some embodiments of the present application;
[0033] Figure 4 A schematic cross-sectional view of a semiconductor structure provided in some embodiments of the present application;
[0034] Figure 5 A schematic diagram of a process for preparing a semiconductor structure provided in some embodiments of the present application;
[0035] Figure 6 A schematic diagram of a process for providing a substrate in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0036] Figure 7 A schematic cross-sectional view of a structure obtained by sequentially depositing a first silicon oxide layer, a polysilicon layer, a first silicon oxynitride layer, a spin-coated hard mask layer, and a first silicon oxynitride layer on a surface of one side of a substrate in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0037] Figure 8 A schematic diagram of a cross-sectional structure of a structure obtained after a patterned photoresist layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0038] Fig. 9 A schematic cross-sectional view of a structure obtained after a mask pattern is transferred to a first silicon oxynitride layer and a spin-coated hard mask layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0039] Fig.10 A schematic diagram of a cross-sectional structure of a structure obtained after depositing a second silicon oxide layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0040] Fig.11 A schematic cross-sectional view of a structure obtained after removing the second silicon oxide layer, the first silicon oxynitride layer and the spin-coated hard mask layer located on top of the first silicon oxynitride layer and the spin-coated hard mask layer in the method for preparing the semiconductor structure provided in some embodiments of the present application;
[0041] Fig.12 A schematic diagram of a cross-sectional structure of a structure obtained after etching a first silicon oxynitride layer and a polysilicon layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0042] Fig.13 FIG. (a) shows a structure obtained after forming a plurality of initial active pillars in a method for preparing a semiconductor structure provided in some embodiments of the present application. Figure 4 Schematic diagram of the cross-sectional structure in the cc' direction; Fig.13 Figure (b) is Fig.13 The structure shown in Figure (a) is Figure 4 Schematic diagram of the cross-sectional structure in the aa' direction;
[0043] Fig.14 A schematic cross-sectional view of a structure obtained after a sidewall protection layer is formed on the sidewall of an initial active column in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0044] Fig.15 A schematic diagram of a cross-sectional structure of a structure obtained after a bit line is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0045] Fig.16 A schematic diagram of a cross-sectional structure of a structure obtained after etching a stop layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0046] Fig.17 A schematic cross-sectional view of a structure obtained after a gate receiving groove is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0047] Fig.18 A schematic diagram of a cross-sectional structure of a structure obtained after removing an etching stop layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0048] Fig.19 A schematic diagram of a cross-sectional structure of a structure obtained after a gate dielectric layer is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0049] Fig. 20 A schematic cross-sectional view of a structure obtained after forming a first isolation dielectric layer in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0050] Fig.21 FIG. (a) shows a structure obtained after exposing the gate dielectric layer covering the channel region in a method for preparing a semiconductor structure provided in some embodiments of the present application. Figure 4 Schematic diagram of the cross-sectional structure in the aa' direction; Fig.21 Figure (b) is Fig.21 The structure shown in Figure (a) is Figure 4 Schematic diagram of the cross-sectional structure in the cc' direction;
[0051] Fig. 22 A schematic diagram of a cross-sectional structure of a structure obtained after a gate is formed in a method for preparing a semiconductor structure provided in some embodiments of the present application;
[0052] Fig.23 This is a schematic diagram of the cross-sectional structure of a structure obtained after forming a protective layer in a method for preparing a semiconductor structure provided in some embodiments of the present application.
[0053] Description of reference numerals:
[0054] 1. Substrate; 10. Active pillar; 10'. Initial active pillar; 100. Channel region; 100'. Initial channel region; 100A. Gate accommodating groove; 2. Gate; 21. First part; 22. Second part; 3. Gate dielectric layer; 4A. First silicon oxide layer; 4B. Polysilicon layer; 4C. First silicon oxynitride layer; 4D. Spin-on hard mask layer; 4E. Second silicon oxynitride layer; 4F. Patterned photoresist layer; 4G. Second silicon oxide layer; 5. Bit line; 6. Sidewall protection layer; 7. Etch stop layer; 81. First isolation dielectric layer; 82. Second isolation dielectric layer; 9. Protection layer; T1. First isolation groove; T2. Second isolation groove. DETAILED DESCRIPTION
[0055] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0057] It should be understood that when an element or layer is referred to as being "located on" or "connected to" another element or layer, it can be directly located on or connected to the other element or layer; or, there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below can be represented as a second element, component, region, layer or portion; for example, a first surface can be referred to as a second surface, and similarly, a second surface can be referred to as a first surface; the first surface and the second surface are different surfaces.
[0058] Spatial relational terms such as "on..." may be used to describe the relationship of an element or feature shown in a figure to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "on..." will be oriented as "below..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0059] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0060] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques, and the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.
[0061] In view of the above-mentioned deficiencies in the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, the details of which will be described in subsequent embodiments.
[0062] According to some embodiments, the present application provides a semiconductor structure.
[0063] As an example, the semiconductor structure can be used to form a semiconductor device (such as DRAM), and the DRAM can include a transistor structure and a capacitor structure connected to the transistor structure, the capacitor structure is used to store data, and the transistor structure is used to read data in the capacitor structure or write data into the capacitor structure. It can be understood that the semiconductor structure provided in the embodiment of the present application can be used as a component of the transistor structure in the DRAM, for example, it can be a vertical channel array transistor, but it is not limited to this. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.
[0064] See also Figure 1In some embodiments, the semiconductor structure may include a substrate and a plurality of gates 2 .
[0065] The substrate may include a plurality of active pillars 10 arranged in an array. The active pillars 10 may include a channel region 100 . The sidewall of the channel region 100 has a gate receiving groove 100A.
[0066] The gate 2 covers the channel region 100 corresponding to the active pillar 10 , and the gate 2 at least fills the gate receiving groove 100A.
[0067] In the semiconductor structure provided in the above embodiment, the gate 2 is arranged in a manner of covering the channel region 100 of the active pillar 10, so that more active pillars 10 and gates 2 can be arranged under the premise of occupying the same substrate area, thereby improving the space utilization rate, which is beneficial to improving the integration and storage density of the semiconductor device. In the above embodiment, the side wall of the channel region 100 has a gate accommodating groove 100A, and the gate 2 is filled in the gate accommodating groove 100A, so that the contact area between the gate 2 and the channel region 100 can be increased, which is beneficial to enhance the gate control ability of the gate 2 to the semiconductor structure, and can reduce the leakage current, thereby reducing the subthreshold swing (SS) of the semiconductor structure. The subthreshold swing is a performance indicator for measuring the mutual conversion rate between the on and off states of a semiconductor device. It represents the change in gate voltage required for the source-drain current to change ten times. The smaller the subthreshold swing, the faster the switching ratio. For example, compared with the related art, the subthreshold swing of the semiconductor structure provided in the embodiment of the present application can be reduced by 13%. Therefore, the semiconductor structure provided by the above embodiment has a higher on / off ratio, which is beneficial to improving the electrical performance of the semiconductor device. For example, the on / off ratio can be improved by one order of magnitude by using the semiconductor structure provided by the embodiment of the present application.
[0068] As an example, the first direction is parallel to the substrate.
[0069] Please continue reading Figure 1 In some embodiments, the gate 2 may include a first portion 21 filled in the gate receiving groove 100A.
[0070] As an example, Figure 1 As shown, the first portion 21 of the gate 2 may include an upper surface and a lower surface parallel to the substrate, and a side surface connecting the upper surface and the lower surface.
[0071] In some embodiments, Figure 1 As shown, the side surface may be perpendicular to the upper surface and the lower surface.
[0072] In some embodiments, the ratio of the depth of the gate receiving groove 100A to the radial dimension of the active pillar 10 is in the range of 1 / 5 to 1 / 3; for example, the ratio of the depth of the gate receiving groove 100A to the radial dimension of the active pillar 10 can be 1 / 5, 1 / 4 or 1 / 3, etc. Figure 1 Indicated by EW.
[0073] The embodiment of the present application does not specifically limit the depth EW of the gate receiving groove 100A. As an example, the depth EW of the gate receiving groove 100A may be 1 nm to 3 nm; for example, the depth EW of the gate receiving groove 100A may be 1 nm, 2 nm or 3 nm.
[0074] Please combine Figure 2 As can be understood from FIG. (a) in FIG. 1 , the subthreshold swing of the semiconductor structure can be reduced as the depth EW of the gate receiving groove 100A increases. Figure 3 As shown in FIG. 8( a ), the on / off ratio of the semiconductor structure can be improved as the depth EW of the gate receiving groove 100A increases.
[0075] Please continue reading Figure 1 In some embodiments, the gate 2 may further include a second portion 22 connected to the first portion 21 .
[0076] The second portion 22 of the gate 2 may be located on the sidewall of the channel region 100 , and its orthographic projection on the active pillar 10 may cover the gate receiving groove 100A.
[0077] As an example, the extension direction of the active pillar 10 may be a direction perpendicular to the substrate.
[0078] The embodiment of the present application does not specifically limit the size of the first portion 21 of the gate 2 in the direction perpendicular to the substrate. The size of the first portion 21 of the gate 2 in the direction perpendicular to the substrate can refer to Figure 1 As indicated by EL1 in the figure. As an example, the dimension EL1 of the first portion 21 of the gate 2 in the direction perpendicular to the substrate may be 2nm to 8nm; for example, the dimension EL1 of the first portion 21 of the gate 2 in the direction perpendicular to the substrate may be 2nm, 4nm, 6nm or 8nm, etc.
[0079] Please combine Figure 2 As can be understood from FIG. (b) in FIG. 1 , the subthreshold swing of the semiconductor structure can be reduced as the dimension EL1 of the first portion 21 of the gate 2 in the direction perpendicular to the substrate increases. Figure 3 As shown in FIG. 2( b ), the switching ratio of the semiconductor structure can be improved as the size EL1 of the first portion 21 of the gate 2 in the direction perpendicular to the substrate increases.
[0080] In some embodiments, the ratio of the size of the second portion 22 of the gate 2 in the direction perpendicular to the substrate to the size EL1 of the first portion 21 in the direction perpendicular to the substrate is in the range of 1.5 to 2; for example, the ratio of the size of the second portion 22 of the gate 2 in the direction perpendicular to the substrate to the size EL1 of the first portion 21 in the direction perpendicular to the substrate can be 1.5, 1.75 or 2, etc. The size of the second portion 22 of the gate 2 in the direction perpendicular to the substrate can refer to Figure 1 Indicated by EL2.
[0081] Please continue reading Figure 1 In some embodiments, the semiconductor structure may further include a gate dielectric layer 3 .
[0082] The gate dielectric layer 3 at least conformally covers the inner wall of the gate receiving groove 100A.
[0083] In the semiconductor structure provided by the above embodiment, the gate 2 is located on the surface of the gate dielectric layer 3 away from the active pillar 10 .
[0084] In some embodiments, the semiconductor structure may further include a plurality of word lines (WL) arranged at intervals. Each of the word lines extends along a first direction (eg, X direction). Each of the word lines sequentially connects the gates 2 in the same row in series.
[0085] In some embodiments, the semiconductor structure may further include a plurality of bit lines arranged at intervals, and the bit lines are located below the active pillars 10 .
[0086] Please combine Figure 4 It is understood that in the embodiment of the present application, the second direction intersects with the first direction. The embodiment of the present application is described below by taking the first direction as the X direction and the second direction as the Y direction as an example.
[0087] like Figure 4 As shown, each bit line 5 extends along the second direction (eg, the Y direction) and is arranged at intervals along the first direction (eg, the X direction), and the active pillars 10 located in the same column along the second direction (eg, the Y direction) are serially connected in sequence.
[0088] According to some embodiments, the present application also provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure provided by some of the above embodiments.
[0089] See also Figure 5 In some embodiments, the method for preparing the semiconductor structure may include the following steps:
[0090] S100: providing a substrate; forming a plurality of active pillars arranged in an array on a surface of one side of the substrate, the active pillars forming a channel region, and a gate accommodating groove formed on a sidewall of the channel region.
[0091] S200: forming a plurality of gates; each gate extends along a first direction to cover a channel region of an active pillar located in the same row; and the gate at least fills a gate receiving groove.
[0092] In the method for preparing the semiconductor structure provided in the above embodiment, the gate is made by covering the active pillar channel region, so more active pillars and gates can be arranged under the premise of occupying the same substrate area, thereby improving the space utilization rate, which is beneficial to improving the device integration and storage density. In the above embodiment, a gate accommodating groove is formed on the side wall of the channel region, and the gate is filled in the gate accommodating groove, which can increase the contact area between the gate and the channel region, which is beneficial to enhancing the gate control ability of the gate to the semiconductor structure, and can reduce the leakage current, thereby making the semiconductor structure have a higher switching ratio, which is beneficial to improving the electrical performance of the semiconductor device.
[0093] See also Figure 6 In some embodiments, step S100 of providing a substrate may include the following steps:
[0094] S110: etching the substrate to form a plurality of initial active pillars arranged in an array on a surface of one side of the substrate; the initial active pillars are formed with initial channel regions.
[0095] S120: forming a plurality of spaced-apart bit lines in the substrate; each bit line extends along a second direction and is located below the initial active pillars to sequentially connect the initial active pillars in the same row in series; the second direction intersects the first direction.
[0096] S130: etching the initial active pillar to form a gate receiving groove in the initial channel region; the retained initial active pillar serves as the active pillar, and the retained initial channel region serves as the channel region; the gate receiving groove includes a first surface and a second surface parallel to the substrate, and a third surface connecting the first surface and the second surface.
[0097] It should be understood that although Figure 5 and Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5 and Figure 6 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0098] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiments, Figures 7 to 23 Understand some embodiments of the present application.
[0099] In step S100, refer to Figures 7 to 17 A substrate 1 is provided. A plurality of active pillars 10 arranged in an array are formed on one surface of the substrate 1. The active pillars 10 are formed with channel regions 100. The sidewalls of the channel regions 100 are formed with gate accommodating grooves 100A.
[0100] The embodiments of the present application do not specifically limit the constituent materials of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on an insulator.
[0101] In some embodiments, step S100 provides a substrate 1 , which may be specifically performed as follows steps S110 to S130 .
[0102] In step S110, refer to Figures 7 to 13 The substrate 1 is etched to form a plurality of initial active pillars 10 ′ arranged in an array on a surface of one side of the substrate 1 , wherein the initial active pillars 10 ′ are formed with initial channel regions 100 ′.
[0103] In step S120, refer to Figure 14 to Figure 15 A plurality of spaced-apart bit lines 5 are formed in the substrate 1. Each bit line 5 extends along the second direction (eg, the Y direction) and is located below the initial active pillars 10' to sequentially connect the initial active pillars 10' in the same row.
[0104] In step S130, refer to Figures 14 to 17 , the initial active pillar 10' is etched to form a gate receiving groove 100A in the initial channel region 100'. The retained initial active pillar 10' serves as the active pillar 10, and the retained initial channel region 100' serves as the channel region 100. The gate receiving groove 100A may include a first surface and a second surface parallel to the substrate 1, and a third surface connecting the first surface and the second surface.
[0105] The embodiment of the present application does not specifically limit the method of forming the initial active pillars 10' on the surface of the substrate 1 in step S110. As an example, a self-aligned double patterning (SADP) process may be used to form a plurality of initial active pillars 10' arranged in an array on one side of the substrate 1, and the specific steps may include but are not limited to:
[0106] like Figure 7 As shown, a first silicon oxide (SiO 2 ) layer 4A, polysilicon layer 4B, first silicon oxynitride (SiON) layer 4C, spin-on hard mask (SOH) layer 4D and second silicon oxynitride layer 4E. It can be understood that in the embodiment of the present application, the spin-on hard mask layer 4D can be formed by a spin coating process; for example, the spin-on hard mask layer 4D can be an insulating layer of a carbon hydrogen (CxHy) system, which can include a silicon hard mask material, a carbon hard mask material, and an organic hard mask material.
[0107] like Figure 8 As shown, a photoresist (PR) layer is formed on the surface of the structure obtained in the above steps, and the photoresist layer is exposed and developed to form a mask pattern in the photoresist layer, thereby forming a patterned photoresist layer 4F.
[0108] like Fig. 9 As shown, the second silicon oxynitride layer 4E and the spin-on hard mask layer 4D are etched based on the patterned photoresist layer 4F to transfer the mask pattern into the second silicon oxynitride layer 4E and the spin-on hard mask layer 4D, and remove the patterned photoresist layer 4F.
[0109] like Fig.10 As shown, a second silicon oxide layer 4G is deposited on the sidewalls and top of the remaining second silicon oxynitride layer 4E and the spin-on hard mask layer 4D.
[0110] like Fig.11 As shown, the structure obtained in the above steps is etched back to remove the second silicon oxide layer 4G, the second silicon oxide layer 4E and the spin-coated hard mask layer 4D located on the top of the second silicon oxynitride layer 4E and the spin-coated hard mask layer 4D, and retain the second silicon oxide layer 4G located on the sidewalls of the second silicon oxynitride layer 4E and the spin-coated hard mask layer 4D. For example, this step can be etched back using anisotropic etching, which can selectively etch materials in a preset crystal direction or crystal plane direction, leaving only a few or almost no etching marks in other directions. In this step, the morphology of the obtained structure can be made more accurate and controllable by using anisotropic etching for back etching.
[0111] like Fig.12 As shown, the first silicon oxynitride layer 4C and the polysilicon layer 4B are etched using the second silicon oxide layer 4G retained in the previous step as a mask.
[0112] like Fig.13 Figure (a) and Fig.13 As shown in FIG. 7 (b), the first silicon oxynitride layer 4C and the polysilicon layer 4B retained in the previous step are used as masks to continue etching the first silicon oxide layer 4A and the substrate 1, and the first silicon oxide layer 4A is removed, thereby forming a plurality of initial active pillars 10' on one side surface of the substrate 1.
[0113] In step S110, Fig.13 Figure (a) and Fig.13 As shown in FIG. 2( b ), the substrate 1 may be etched to form a first isolation trench T1 extending along the second direction and a second isolation trench T2 extending along the first direction. The first isolation trench T1 and the second isolation trench T2 may together isolate a plurality of initial active pillars 10 ′.
[0114] The present application embodiment does not specifically limit the material of the bit line 5. As an example, the material of the bit line 5 may include at least one of metal silicide or metal. In some embodiments, the material of the bit line 5 may only include metal silicide, such as titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ) and nickel silicide (NiSi 2 )etc.
[0115] The embodiment of the present application does not specifically limit the method of forming the bit line 5 in the substrate 1 in step S120. As an example, the bit line 5 can be formed in the substrate 1 in step S120 by the following steps, for example:
[0116] like Fig.14 As shown, a sidewall protection layer 6 is formed on the sidewalls of the initial active pillar 10 ′.
[0117] like Fig.15 As shown, the substrate 1 is etched to form a plurality of bit line trenches arranged at intervals and extending along the second direction (eg, the Y direction) below the initial active pillars 10 ′; and bit lines 5 are formed in the bit line trenches.
[0118] It should be noted that in the embodiment of the present application, there is no order restriction for the steps of forming the bit line 5 and the steps of forming the initial active pillar 10' and the gate receiving groove 100A. The above embodiment is only used as an example. In the actual embodiment, any of the three can be performed first or simultaneously.
[0119] The present embodiment of the application does not specifically limit the material of the sidewall protection layer 6 in the aforementioned step. As an example, the material of the sidewall protection layer 6 may include but is not limited to silicon nitride (SiN).
[0120] The embodiment of the present application does not specifically limit the method of forming the gate receiving groove 100A in the initial channel region 100' in step S120. As an example, the gate receiving groove 100A can be formed in the initial channel region 100' by the following steps, for example:
[0121] like Fig.16 As shown, an etch stop layer 7 is formed at the bottom of the second isolation trench T2; the plane where the top surface of the etch stop layer 7 is located is higher than the plane where the bottom surface of the initial channel region 100' is located, or is flush with the plane where the bottom surface of the initial channel region 100' is located. The etch stop layer 7 can be used to define the position of the gate receiving trench 100A.
[0122] like Fig.17 As shown, the initial active pillar 10 ′ is etched based on the etch stop layer 7 to form a gate accommodating groove 100A in the initial channel region 100 ′; the retained initial active pillar 10 ′ serves as the active pillar 10 , and the retained initial channel region 100 ′ serves as the channel region 100 .
[0123] In some embodiments, see Figure 17 to Figure 18 After forming the gate receiving groove 100A, the method for preparing the semiconductor structure may further include the following steps: gradually removing the etching stop layer 7 .
[0124] The embodiment of the present application does not specifically limit the material of the etch stop layer 7. In some embodiments, the material of the etch stop layer 7 can be the same as or similar to the material of the sidewall protection layer 6.
[0125] As an example, the material of the etch stop layer 7 may include but is not limited to silicon nitride.
[0126] In some embodiments, see Fig.19 Before forming a plurality of gates, the method for preparing the semiconductor structure may further include the following steps: conformally covering the inner wall of the gate receiving groove 100A with a gate dielectric layer 3 .
[0127] In some embodiments, see Fig. 20 After forming the gate dielectric layer 3 and before forming a plurality of gates, the method for preparing the semiconductor structure may further include the following steps: filling the second isolation trench T2 with a first isolation dielectric layer 81 .
[0128] The present embodiment of the application does not specifically limit the material of the first isolation dielectric layer 81. As an example, the material of the first isolation dielectric layer 81 may include but is not limited to silicon nitride.
[0129] In step S200, refer to Figure 21 to Figure 22 , forming a plurality of gates 2. Each gate 2 extends along a first direction (eg, X direction) to cover the channel region 100 of the active pillars 10 located in the same row. In the embodiment of the present application, the gate 2 can at least fill the gate receiving groove 100A.
[0130] In some embodiments, Fig.21 As shown in FIG. 2( b ), the method for preparing the semiconductor structure may further include the following steps: filling the first isolation trench T1 with a second isolation dielectric layer 82 .
[0131] The present embodiment of the application does not specifically limit the material of the second isolation dielectric layer 82. In some embodiments, the material of the second isolation dielectric layer 82 can be the same as or similar to the material of the first isolation dielectric layer 81.
[0132] As an example, the material of the first isolation dielectric layer 81 may include but is not limited to silicon nitride.
[0133] The embodiment of the present application does not specifically limit the method for forming the gate 2. As an example, the gate 2 may be formed in the following manner, for example:
[0134] like Fig.21 Figure (a) and Fig.21 As shown in FIG. 8( b ), the first isolation dielectric layer 81 and the second isolation dielectric layer 82 are etched to expose the gate dielectric layer 3 covering the channel region 100 .
[0135] like Fig. 22 As shown, a gate 2 is formed on the exposed surface of the gate dielectric layer 3 .
[0136] In some embodiments, please refer to Fig. 22 The formation of the gate 2 may specifically include the following steps: filling the first portion 21 of the gate 2 in the gate receiving groove 100A, and forming the second portion 22 of the gate 2 on the sidewall of the channel region 100 .
[0137] Please combine Figure 1 It is understood that the second portion 22 is connected to the first portion 21 , and its orthographic projection on the active pillar 10 covers the gate receiving groove 100A.
[0138] It can be understood that in the embodiment where the inner wall of the gate receiving groove 100A is conformally covered with the gate dielectric layer 3 , the gate dielectric layer 3 is located between the gate 2 and the gate receiving groove 100A.
[0139] The embodiment of the present application does not specifically limit the material of the gate 2. As an example, the material of the gate 2 may include at least one of tungsten metal and copper metal.
[0140] In some embodiments, the method for preparing the semiconductor structure further comprises: forming a plurality of word lines arranged at intervals, each of which extends along a first direction (eg, X direction), and each of which sequentially connects gates 2 located in the same row.
[0141] In some embodiments, see Fig.23 After forming a plurality of gate electrodes 2 in step S200 , the method for preparing the semiconductor structure may further include the following step: forming a protection layer 9 on the top surface of the obtained structure.
[0142] In the method for preparing the semiconductor structure provided in the above embodiment, the protective layer 9 can be used to protect the underlying structure from the influence of the external environment, provide a certain mechanical strength and corrosion resistance, and prevent external moisture, oxidants and other harmful substances from corroding and damaging the underlying structure, thereby improving the production yield of the preparation method and the reliability of the obtained semiconductor structure.
[0143] It should be noted that the preparation methods of the semiconductor structures provided in the embodiments of the present application can be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that technical personnel in this field can understand the technical content of the present application.
[0144] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0145] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A semiconductor structure, characterized in that: include: A substrate; the substrate comprises a plurality of active pillars arranged in an array, the active pillars comprise a channel region, and the sidewalls of the channel region have a gate accommodating groove; Multiple gates; The gate covers the channel region corresponding to the active pillar, and the gate at least fills the gate receiving groove.
2. The semiconductor structure according to claim 1, characterized in that: The gate includes a first portion filled and disposed in the gate receiving groove; The first portion of the gate includes an upper surface and a lower surface parallel to the substrate, and a side surface connecting the upper surface and the lower surface.
3. The semiconductor structure according to claim 2, characterized in that: The side surface is perpendicular to the upper surface and the lower surface.
4. The semiconductor structure according to claim 2, characterized in that: The ratio of the depth of the gate accommodating groove to the radial dimension of the active pillar is in a range of 1 / 5 to 1 / 3.
5. The semiconductor structure according to claim 2, characterized in that: The gate further includes a second portion connected to the first portion; The second portion of the gate is located on the side wall of the channel region, and its orthographic projection on the active pillar covers the gate receiving groove.
6. The semiconductor structure according to claim 5, characterized in that: The ratio of the size of the second portion of the gate in a direction perpendicular to the substrate to the size of the first portion in a direction perpendicular to the substrate is in a range of 1.5-2.
7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: It also includes a gate dielectric layer; the gate dielectric layer at least conformally covers the inner wall of the gate accommodating groove; The gate is located on a surface of the gate dielectric layer away from the active pillar.
8. A method for preparing a semiconductor structure, characterized in that: include: A substrate is provided; a plurality of active pillars arranged in an array are formed on a surface of one side of the substrate, the active pillars are formed with a channel region, and a gate accommodating groove is formed on a sidewall of the channel region; A plurality of gates are formed; the gates cover the channel regions of the active pillars in the same row and at least fill the gate receiving grooves.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The providing of a substrate comprises: Etching the substrate to form a plurality of initial active pillars arranged in an array on a surface of one side of the substrate; the initial active pillars are formed with initial channel regions; A plurality of spaced bit lines are formed in the substrate; each of the bit lines extends along the second direction and is spaced along the first direction, and is located below the initial active pillars, so as to sequentially connect the initial active pillars located in the same row along the second direction; the second direction intersects the first direction; The initial active column is etched to form a gate accommodating groove in the initial channel region; the retained initial active column is used as the active column, and the retained initial channel region is used as the channel region; the gate accommodating groove includes a first surface and a second surface parallel to the substrate, and a third surface connecting the first surface and the second surface.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The forming of a plurality of gates comprises: The first part of the gate is filled in the gate receiving groove, and the second part of the gate is formed on the side wall of the channel region; the second part is connected to the first part, and its orthographic projection on the active pillar covers the gate receiving groove.
11. The method for preparing a semiconductor structure according to any one of claims 8 to 10, characterized in that: Before forming the plurality of gates, the method further includes: conformally covering the inner wall of the gate accommodating groove with a gate dielectric layer.