Array substrate, manufacturing method thereof and display panel

Abstract

The invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a substrate body, a plurality of thin film transistors, a first shielding layer and a second shielding layer. The multiple thin film transistors are located on one side of the substrate, and the second shielding layer and the first shielding layer are stacked between the substrate and the thin film transistors. According to the invention, the non-graphical second shielding layer which is in contact with the first shielding layer is added, and the orthographic projections of all thin film transistors on the substrate are arranged in the orthographic projection range of the second shielding layer on the substrate. Therefore, the first shielding layer and the second shielding layer can provide the functions of shielding impurity ions, free charges and other negative effects for all the thin film transistors so as to improve the electrical property stability of all the thin film transistors, thereby effectively improving the display problems of ghost shadows and the like of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] With the development of display technology, flexible display panels have been increasingly widely used due to their advantages such as ultra-thinness, light weight and rollability. The production of flexible display panels mainly involves forming display devices on flexible substrates and performing thin film encapsulation on the display devices. Therefore, in recent years, many manufacturers have formed flexible AMOLED display panels by making active matrix organic light emitting diode (AMOLED) display layers on flexible substrates and then performing thin film encapsulation. This display panel technology has gradually become the research direction of major manufacturers.

[0003] However, during the use of products with flexible AMOLED display panels, the presence of the flexible substrate will affect the electrical properties of the display panel thin film transistors, causing some display problems. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a manufacturing method thereof and a display panel, which are used to improve the problem that the flexible substrate affects the electrical performance of the thin film transistor.

[0005] In a first aspect, an array substrate is provided, the array substrate comprising a base substrate, a plurality of thin film transistors, and a first shielding layer and a second shielding layer. The plurality of thin film transistors are located on one side of the base substrate, and the second shielding layer and the first shielding layer are stacked between the base substrate and the thin film transistors. The second shielding layer is in contact with the first shielding layer, the second shielding layer comprises an amorphous silicon layer, the first shielding layer is a patterned film layer, the orthographic projections of the plurality of thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projection of the first shielding layer on the base substrate is located within the orthographic projection range of the second shielding layer on the base substrate.

[0006] In combination with the first aspect, in some implementations of the first aspect, the second shielding layer is located between the base substrate and the first shielding layer.

[0007] In combination with the first aspect, in some implementations of the first aspect, the second shielding layer covers the entire surface of the substrate on a side close to the first shielding layer.

[0008] In combination with the first aspect, in some implementations of the first aspect, the first shielding layer is located between the base substrate and the second shielding layer.

[0009] In combination with the first aspect, the second shielding layer includes a non-patterned film layer.

[0010] In combination with the first aspect, in some implementations of the first aspect, the array substrate further includes an adhesion layer, and the adhesion layer is located between the base substrate and the first shielding layer.

[0011] In combination with the first aspect, in some implementations of the first aspect, the adhesion layer includes a silicon oxide layer.

[0012] In combination with the first aspect, in some implementations of the first aspect, the conductivity of the first shielding layer is greater than the conductivity of the second shielding layer, and the transmittance of the second shielding layer is greater than the transmittance of the first shielding layer.

[0013] In combination with the first aspect, in some implementations of the first aspect, the first shielding layer includes a metal layer.

[0014] In combination with the first aspect, in some implementations of the first aspect, the second shielding layer includes a conductive doping material.

[0015] In combination with the first aspect, in some implementations of the first aspect, the conductive doping material includes at least one of boron trifluoride, phosphine, and arsine.

[0016] In combination with the first aspect, in some implementations of the first aspect, the first shielding layer is a mesh structure.

[0017] In combination with the first aspect, in certain implementations of the first aspect, in a direction perpendicular to the substrate, the thickness of the second shielding layer does not exceed 100 angstroms.

[0018] In combination with the first aspect, the second shielding layer has a thickness ranging from 30 angstroms to 100 angstroms.

[0019] In combination with the first aspect, in some implementations of the first aspect, the array substrate further includes a constant voltage signal line, and the first shielding layer is electrically connected to the constant voltage signal line.

[0020] In a second aspect, a method for manufacturing an array substrate is provided, comprising the following steps:

[0021] providing a substrate base plate;

[0022] Sequentially preparing two shielding layers on the substrate, the two shielding layers comprising a first shielding layer and a second shielding layer, the first shielding layer is in contact with the second shielding layer, wherein the first shielding layer is a patterned film layer, and the second shielding layer is an amorphous silicon layer;

[0023] A plurality of thin film transistors are prepared on the side of the shielding layer prepared later away from the base substrate, and the orthographic projections of some of the thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projections of the plurality of thin film transistors on the base substrate are all located within the orthographic projection range of the second shielding layer on the base substrate.

[0024] In combination with the second aspect, the step of sequentially preparing two shielding layers on the substrate includes:

[0025] A second shielding layer is formed on one side of the substrate, and a first shielding layer is formed on a side of the second shielding layer away from the substrate; or

[0026] Prepare a first shielding layer on one side of the substrate, and prepare a second shielding layer on a side of the first shielding layer away from the substrate;

[0027] Preferably, the second shielding layer covers the entire surface of the substrate substrate on a side close to the first shielding layer;

[0028] Preferably, the second shielding layer is a patterned film layer.

[0029] In conjunction with the second aspect, in certain implementations of the second aspect, preparing the second shielding layer on one side of the substrate includes:

[0030] preparing an amorphous silicon layer including a conductive doping material by a vapor deposition method;

[0031] In conjunction with the second aspect, in certain implementations of the second aspect, preparing the second shielding layer on one side of the substrate includes:

[0032] The amorphous silicon layer is prepared by a vapor deposition method;

[0033] The amorphous silicon layer is doped by ion implantation;

[0034] In combination with the second aspect, in some implementations of the second aspect, a first shielding layer is prepared on a side of the second shielding layer away from the base substrate, the first shielding layer is in contact with the second shielding layer, and the first shielding layer is a patterned film layer, further comprising:

[0035] Etching the first shielding layer to obtain a patterned first shielding layer;

[0036] Preferably, etching the first shielding layer further comprises:

[0037] Controlling the etching degree by controlling the etching loss so that the thickness of the second shielding layer meets the preset requirements;

[0038] Preferably, the second shielding layer comprises a non-patterned film layer;

[0039] Preferably, the thickness of the second shielding layer does not exceed 100 angstroms;

[0040] Preferably, the thickness of the second shielding layer is in the range of 30 angstroms to 100 angstroms.

[0041] In a third aspect, a display panel is provided, comprising any of the array substrates mentioned above.

[0042] The present application provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes a base substrate, a plurality of thin film transistors, and a first shielding layer and a second shielding layer. The plurality of thin film transistors are located on one side of the base substrate, and the second shielding layer and the first shielding layer are stacked between the base substrate and the thin film transistors. The second shielding layer is in contact with the first shielding layer, the second shielding layer is an amorphous silicon layer, the first shielding layer is a patterned film layer, the orthographic projections of the plurality of thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projection of the first shielding layer on the base substrate is located within the orthographic projection range of the second shielding layer on the base substrate;

[0043] Preferably, the second shielding layer is a non-patterned film layer.

[0044] The embodiment of the present application adds a second non-patterned shielding layer that is in contact with the first shielding layer, and sets the orthographic projections of all thin film transistors on the substrate to be within the orthographic projection range of the second shielding layer on the substrate, so that the second shielding layer can provide a shielding effect for all thin film transistors, block the influence of impurity ions, free charges, etc. at the substrate on all thin film transistors, so as to improve the electrical performance stability of all thin film transistors, thereby effectively improving display problems such as afterimages of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0046] Figure 1a It is a schematic diagram of the cross-sectional structure of an array substrate in the prior art.

[0047] Figure 1b yes Figure 1a A top view of the array substrate is shown.

[0048] Figure 2a Schematic diagram of the cross-sectional structure of an array substrate in one embodiment of the present application.

[0049] Figure 2b for Figure 2a A top view of the array substrate is shown in FIG.

[0050] Figure 3 This is a top view of an array substrate in another embodiment of the present application.

[0051] Figure 4a FIG. 4 is a schematic diagram of the cross-sectional structure of an array substrate in another embodiment of the present application.

[0052] Figure 4b for Figure 4a A top view of the array substrate is shown in FIG.

[0053] Figure 5 Flow chart of a method for manufacturing an array substrate in one embodiment of the present application.

[0054] Figure 6 This is a flow chart of a method for manufacturing an array substrate in another embodiment of the present application.

[0055] Figure 7 This is a flow chart of a method for manufacturing an array substrate in another embodiment of the present application.

[0056] Figure 8 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. The features and exemplary embodiments of various aspects of the present application will be described in detail below.

[0058] Figure 1a is a schematic diagram of the cross-sectional structure of an array substrate in the prior art, Figure 1b yes Figure 1a The top view of the array substrate is shown in FIG. Figure 1a and Figure 1b As shown, the array substrate includes a base substrate 100 , a plurality of thin film transistors 200 and a first shielding layer 300 . The plurality of thin film transistors 200 are located on one side of the base substrate 100 , and the first shielding layer 300 is stacked between the base substrate 100 and the thin film transistors 200 .

[0059] In many application scenarios, the material of the substrate 100 is a flexible organic material such as polyimide. Under the action of an electric field, the organic molecular structure will be polarized, and the defect charges and impurity ions in the organic substrate will move under the action of the electric field, which will produce a back channel effect and react to the thin film transistor, affecting the electrical performance stability of the thin film transistor 200, thereby damaging the stability of the display device. Therefore, in the prior art, a first shielding layer 300 is set between the substrate 100 and the thin film transistor 200 to block the impurity ions, free charges, etc. under the first shielding layer 300, thereby improving the electrical performance of the thin film transistor.

[0060] However, since the material of the first shielding layer 300 is generally copper or tinned copper, the transmittance of the first shielding layer 300 is relatively low. Many products on the market have certain requirements for the overall transmittance of the product. Considering the transmittance problem, the setting area of ​​the first shielding layer 300 cannot be too large, resulting in the first shielding layer 300 not being able to shield all thin film transistors 200. Figure 1b As shown, the orthographic projections of the thin film transistors 200 located at various edge positions of the array substrate on the base substrate 100 are not located within the orthographic projection range of the first shielding layer 300 on the base substrate 100 .

[0061] Also based on transmittance considerations, the first shielding layer 300 is generally set to a graphical structure, such as a mesh structure, and the orthographic projection of some thin film transistors 200 located at the hollowed-out position of the first shielding layer 300 on the base substrate 100 is not located within the orthographic projection range of the first shielding layer 300 on the base substrate 100. In summary, the existence of the first shielding layer 300 cannot completely shield the influence of the base substrate 100 on all thin film transistors 200, and the shielding effect is not good, which will cause display problems such as afterimages.

[0062] In view of this, the present application provides an array substrate and a manufacturing method thereof and a display panel. The embodiment of the present application adds a non-patterned second shielding layer between the base substrate and the first shielding layer, and sets the orthographic projections of all thin film transistors on the base substrate to be within the orthographic projection range of the second shielding layer on the base substrate, so that the second shielding layer can provide a shielding effect for all thin film transistors, block the influence of impurity ions, free charges, etc. at the base substrate on all thin film transistors, so as to improve the electrical performance stability of all thin film transistors, thereby effectively improving the display problems such as afterimage of the display panel.

[0063] Figure 2a is a schematic diagram of a cross-sectional structure of an array substrate in an embodiment of the present application, Figure 2b for Figure 2a The top view of the array substrate is shown in FIG. Figure 2a and Figure 2bAs shown, the array substrate includes a base substrate 100, a plurality of thin film transistors 200, a first shielding layer 300 and a second shielding layer 400. The plurality of thin film transistors 200 are located on one side of the base substrate 100, and the second shielding layer 400 and the first shielding layer 300 are stacked between the base substrate 100 and the thin film transistors 200.

[0064] Specifically, the second shielding layer 400 is located between the base substrate 100 and the first shielding layer 300. The second shielding layer 400 is in contact with the first shielding layer 300, the second shielding layer 400 includes an amorphous silicon layer, the first shielding layer 300 is a patterned film layer, the orthographic projections of the plurality of thin film transistors 200 on the base substrate 100 are located within the orthographic projection range of the first shielding layer 300 on the base substrate 100, and the orthographic projection of the first shielding layer 300 on the base substrate 100 is located within the orthographic projection range of the second shielding layer 400 on the base substrate 100.

[0065] and Figure 1a and Figure 1b In comparison, the embodiment of the present application adds a non-patterned second shielding layer 400 that is in contact with the first shielding layer 300, and sets the orthographic projections of all thin film transistors 200 on the base substrate 100 to be within the orthographic projection range of the second shielding layer 400 on the base substrate 100, so that the second shielding layer 400 can provide a shielding effect for all thin film transistors 200, block the influence of impurity ions, free charges, etc. at the base substrate 100 on all thin film transistors 200, so as to improve the electrical performance stability of all thin film transistors 200, thereby effectively improving display problems such as afterimages of the display panel.

[0066] In one embodiment, the conductivity of the first shielding layer 300 is greater than that of the second shielding layer 400, and the transmittance of the second shielding layer 400 is greater than that of the first shielding layer 300. The first shielding layer 300 with better conductivity is provided as a functional layer electrically connected to the external circuit, so that the shielding effect can be better. The area of ​​the second shielding layer 400 with higher transmittance is set to be larger than the area of ​​the first shielding layer 300 with lower transmittance, so as to ensure that the transmittance of the array substrate is higher under the premise of providing a shielding effect for all thin film transistors 200. Therefore, the array substrate of this embodiment can take into account both good shielding effect and good overall transmittance.

[0067] In one embodiment, the first shielding layer 300 is a mesh structure, specifically, Figure 2b Generally speaking, the transmittance of the first shielding layer 300 is poor, and the transmittance of the array substrate can be improved by setting the first shielding layer 300 as a mesh structure.

[0068] In combination with the first aspect, in certain implementations of the first aspect, the thickness of the amorphous silicon layer in a direction perpendicular to the substrate is no more than 100 angstroms.

[0069] In one embodiment, the array substrate further includes a constant voltage signal line, and the first shielding layer 300 is electrically connected to the constant voltage signal line. In this embodiment, the first shielding layer 300 is electrically connected to the constant voltage signal line, so that the first shielding layer is a shielding layer with a constant potential; and because the second shielding layer 400 is in contact with the first shielding layer 300 and the two are electrically connected, the second shielding layer can also form a shielding layer with a constant potential. By maintaining a constant potential, the first shielding layer 300 and the second shielding layer 400 help to ensure the uniformity and stability of the electrical properties of the thin film transistor 200, thereby improving the display effect. In addition, the constant potential helps to protect the display panel from damage caused by electrostatic discharge, thereby ensuring the quality of the sensitive components of the display panel.

[0070] In one embodiment, the first shielding layer 300 includes a metal layer, and the second shielding layer 400 includes an amorphous silicon layer. Generally speaking, metal materials have relatively better conductivity, while the amorphous silicon layer can achieve higher transmittance.

[0071] In one embodiment, the material constituting the first shielding layer 300 includes red copper or tinned copper.

[0072] In one embodiment, the second shielding layer 400 includes but is not limited to a cadmium telluride film, a copper indium gallium selenide film, and a transparent conductive oxide film.

[0073] In one embodiment, the transparent conductive oxide film includes but is not limited to an indium gallium zinc oxide film, an indium tin oxide film, a fluorine-doped tin oxide film, and an aluminum-doped zinc oxide film. Such materials allow light to pass through while providing a carrier transmission path, thus having both conductivity and good transmittance.

[0074] In one embodiment, the amorphous silicon layer includes a conductive doping material. The amorphous silicon layer is an amorphous semiconductor material. The introduction of the conductive doping material is to introduce a small amount of other elements into the amorphous silicon layer, and improve the conductivity of the amorphous silicon layer by providing additional carriers to increase the carrier concentration. This embodiment improves the conductivity of the amorphous silicon layer, so that the connection between the second shielding layer 400 and the first shielding layer 300 is more reliable, the potential of the second shielding layer 400 is more stable, and it helps to improve the shielding effect of the second shielding layer 400.

[0075] In one embodiment, the conductive doping material includes at least one of boron trifluoride, phosphine, and arsine. The conductive doping material can be n-type (such as phosphine, arsine) or p-type (such as boron trifluoride). N-type conductive doping materials increase the concentration of free electrons, and n-type doping usually leads to the filling of the valence band and the reduction of the conduction band, while p-type conductive doping materials increase the concentration of holes, and p-type doping leads to the cavitation of the conduction band and the increase of the valence band. This change in the band structure helps to improve the injection and movement of electrons and holes, thereby improving conductivity.

[0076] Figure 3 FIG. 1 is a top view of an array substrate in another embodiment of the present application. Figure 2a and Figure 3 As shown, the second shielding layer 400 covers the entire surface of the substrate 100 close to the first shielding layer 300. This configuration not only increases the shielding area of ​​the second shielding layer 400, but also further improves the shielding effect of the second shielding layer 400; on the other hand, it can simplify the preparation process and improve production efficiency.

[0077] Figure 4a is a schematic diagram of a cross-sectional structure of an array substrate in another embodiment of the present application, Figure 4b for Figure 4a The top view of the array substrate is shown in FIG. Figure 4a and Figure 4b As shown, Figure 2a and Figure 2b compared to, Figure 4a and Figure 4b The second shielding layer 400 of the array substrate shown in the figure is located on a side of the first shielding layer 300 away from the base substrate 100 , that is, the first shielding layer 300 is located between the base substrate 100 and the second shielding layer 400 .

[0078] In the embodiment of the present application, a second shielding layer 400 which is in contact with the first shielding layer 300 and is non-patterned is added on the side of the first shielding layer 300 away from the base substrate 100, and the orthographic projections of all thin film transistors 200 on the base substrate 100 are set to be located within the orthographic projection range of the second shielding layer 400 on the base substrate 100, so that the second shielding layer 400 can provide a shielding effect for all thin film transistors 200, block the influence of impurity ions, free charges, etc. at the base substrate 100 on all thin film transistors 200, so as to improve the electrical performance stability of all thin film transistors 200, thereby effectively improving display problems such as afterimages of the display panel.

[0079] In one embodiment, the array substrate further includes an adhesion layer 500, and the adhesion layer 500 is located between the base substrate 100 and the first shielding layer 300. Since it is not easy to directly prepare a metal layer with excellent performance on the base substrate 100 composed of organic materials, the present embodiment effectively improves the adhesion between the first shielding layer 300 and the base substrate 100 by arranging the adhesion layer 500 between the base substrate 100 and the first shielding layer 300, thereby ensuring the stability of the first shielding layer 300. Optionally, the adhesion layer 500 can be directly prepared on the base substrate 100.

[0080] In one embodiment, the adhesion layer 500 includes a silicon oxide layer. Since silicon oxide is chemically very stable and does not easily react chemically with other substances, it is very useful in protecting the underlying material from environmental influences. In addition, the silicon oxide film layer can have good coverage and can be easily and evenly covered on substrates of different shapes, including flat surfaces and surfaces with complex structures. In addition, the silicon oxide layer has good transparency, especially in the ultraviolet and visible light ranges, so it is also suitable for occasions requiring optical transparency, such as in the array substrate in the embodiment of the present application.

[0081] The present application also provides a method for manufacturing an array substrate, the specific steps of which are as follows: Figure 5 shown. Figure 5 This is a flow chart of a method for manufacturing an array substrate in an embodiment of the present application. The specific steps of the method for manufacturing the array substrate are described as follows.

[0082] S510: providing a substrate;

[0083] S520: preparing two shielding layers on the substrate in sequence, the two shielding layers including a first shielding layer and a second shielding layer, the first shielding layer is in contact with the second shielding layer, wherein the first shielding layer is a patterned film layer, and the second shielding layer is an amorphous silicon layer;

[0084] S530: Prepare multiple thin film transistors on the side of the shielding layer prepared later away from the base substrate, and the orthographic projections of some of the thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projections of multiple thin film transistors on the base substrate are all located within the orthographic projection range of the second shielding layer on the base substrate.

[0085] In one embodiment, the second shielding layer covers the entire surface of the substrate close to the first shielding layer.

[0086] In one embodiment, the second shielding layer is a patterned film layer.

[0087] Figure 6This is a flow chart of a method for manufacturing an array substrate in another embodiment of the present application. The specific steps of the method for manufacturing the array substrate are described as follows.

[0088] S610: providing a substrate;

[0089] S620: preparing a second shielding layer on one side of the substrate, wherein the second shielding layer is an amorphous silicon layer;

[0090] S630: preparing a first shielding layer on a side of the second shielding layer away from the substrate, the first shielding layer is in contact with the second shielding layer, and the first shielding layer is a patterned film layer;

[0091] S640: Prepare multiple thin film transistors on the side of the first shielding layer away from the base substrate, and the orthographic projections of some thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projections of multiple thin film transistors on the base substrate are all located within the orthographic projection range of the second shielding layer on the base substrate.

[0092] In one embodiment, the second shielding layer is a non-patterned film layer.

[0093] In this embodiment, during the manufacturing process of the array substrate, a second non-patterned shielding layer is added between the base substrate and the first shielding layer, which is in contact with the first shielding layer, and the orthographic projections of all thin film transistors on the base substrate are set to be within the orthographic projection range of the second shielding layer on the base substrate, so that the second shielding layer can provide a shielding effect for all thin film transistors, block the influence of impurity ions, free charges, etc. at the base substrate on all thin film transistors, so as to improve the electrical performance stability of all thin film transistors, thereby effectively improving display problems such as afterimages of the display panel.

[0094] In one embodiment, in step S620, preparing the second shielding layer on the substrate side includes: preparing an amorphous silicon layer including a conductive doping material by using a vapor deposition method.

[0095] In one embodiment, preparing the amorphous silicon layer including the conductive doping material by using the vapor deposition method includes: preparing the amorphous silicon layer by using the vapor deposition method; and doping the amorphous silicon layer by using the ion implantation method.

[0096] In one embodiment, in step S630, a first shielding layer is prepared on a side of the second shielding layer away from the base substrate, the first shielding layer is in contact with the second shielding layer, and the first shielding layer is a patterned film layer, further comprising: etching the first shielding layer to obtain a patterned first shielding layer.

[0097] In one embodiment, etching the first shielding layer to obtain a patterned first shielding layer includes: etching the first shielding layer to obtain a first shielding layer with a mesh structure.

[0098] In one embodiment, the etching degree is controlled by controlling the etching loss so that the thickness of the second shielding layer meets the preset requirements. Preferably, the thickness of the second shielding layer does not exceed 100 angstroms. Further preferably, the thickness of the second shielding layer ranges from 30 angstroms to 100 angstroms.

[0099] In this embodiment, etching loss is controlled by adjusting etching parameters, such as etching rate, etching solution performance (performance parameters such as etching solution concentration, temperature, pH value, etc.), mask alignment accuracy, etc.

[0100] Specifically, by adjusting the formulation, concentration, temperature and other parameters of the etching solution, as well as optimizing the parameter settings of the etching equipment, the etching rate can be precisely controlled and the occurrence of over-etching can be reduced. High-precision mask alignment technologies, such as laser alignment and electron beam alignment, can be used to improve the alignment accuracy of the mask and reduce material loss caused by alignment errors. The performance parameters of the etching solution, such as concentration, temperature, and pH value, can be regularly tested to ensure that it operates within the optimal range. Once it is found that the performance parameters deviate from the optimal range, they should be adjusted in a timely manner. The etching equipment can also be regularly maintained and calibrated to ensure its accuracy and stability. Aging equipment components should be replaced or repaired in a timely manner.

[0101] The present application also provides a method for manufacturing an array substrate, the specific steps of which are as follows: Figure 7 shown. Figure 7 This is a flow chart of a method for manufacturing an array substrate in another embodiment of the present application. The specific steps of the method for manufacturing the array substrate are described as follows.

[0102] S710: providing a substrate;

[0103] S720: preparing a first shielding layer on one side of the substrate, wherein the first shielding layer is a patterned film layer;

[0104] S730: preparing a second shielding layer on a side of the first shielding layer away from the base substrate, the second shielding layer contacts the first shielding layer, the second shielding layer is an amorphous silicon layer, and the orthographic projection of the first shielding layer on the base substrate is within the range of the orthographic projection of the second shielding layer on the base substrate;

[0105] S740: Prepare multiple thin film transistors on the side of the second shielding layer away from the base substrate, and the orthographic projections of some thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projections of multiple thin film transistors on the base substrate are all located within the orthographic projection range of the second shielding layer on the base substrate.

[0106] In one embodiment, the second shielding layer is a non-patterned film layer.

[0107] In this embodiment, during the manufacturing process of the array substrate, a second non-patterned shielding layer is added to the side of the first shielding layer away from the base substrate, which is in contact with the first shielding layer, and the orthographic projections of all thin film transistors on the base substrate are set to be within the orthographic projection range of the second shielding layer on the base substrate, so that the second shielding layer can provide a shielding effect for all thin film transistors, block the influence of impurity ions, free charges, etc. at the base substrate on all thin film transistors, so as to improve the electrical performance stability of all thin film transistors, thereby effectively improving display problems such as afterimages of the display panel.

[0108] In one embodiment, in step S720, a first shielding layer is prepared on one side of the base substrate, and before the first shielding layer is patterned as a film layer, the method further includes: preparing an adhesion layer on one side of the base substrate.

[0109] An embodiment of the present application further provides a display panel, comprising any of the above array substrates. Figure 8 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel in an embodiment of the present application. Figure 8 As shown, the display panel includes an array substrate 10, which includes a base substrate 100, a second shielding layer 400, a third shielding layer 300, and a plurality of thin film transistors 200 stacked in sequence. In addition, the display panel also includes an anode layer 20, a light-emitting functional layer 30, a cathode layer 40, and an encapsulation layer 50 stacked in sequence on one side of the array substrate 10.

[0110] The display panel in this embodiment uses an array substrate 10 with good shielding function to block the influence of impurity ions, free charges, etc. at the base substrate 100 on all thin film transistors 200, thereby improving the electrical performance stability of all thin film transistors 200, thereby effectively solving display problems such as afterimages of the display panel and improving the display effect of the display panel.

[0111] The present application also provides a display device, including any of the above display panels. The display device of the present application embodiment can be a mobile terminal, such as a mobile phone, or a notebook, a tablet computer, a computer, a wearable device, etc., which is not specifically limited in the present application.

[0112] It should be noted that in the drawings of the present application document, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0113] In addition, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0114] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A plurality of thin film transistors, wherein the plurality of thin film transistors are located on one side of the substrate; as well as A first shielding layer and a second shielding layer stacked between the substrate and the thin film transistor; Among them, the first shielding layer is in contact with the second shielding layer, the first shielding layer is a patterned film layer, the second shielding layer includes an amorphous silicon layer, the orthographic projections of some of the thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projections of the multiple thin film transistors on the base substrate are all located within the orthographic projection range of the second shielding layer on the base substrate.

2. The array substrate according to claim 1, characterized in that: The second shielding layer is located between the base substrate and the first shielding layer; Preferably, the second shielding layer covers the entire surface of the substrate close to the first shielding layer. Preferably, the second shielding layer comprises a non-patterned film layer.

3. The array substrate according to claim 1, characterized in that: The first shielding layer is located between the base substrate and the second shielding layer; Preferably, the array substrate further comprises an adhesive layer, and the adhesive layer is located between the base substrate and the first shielding layer; Preferably, the adhesion layer comprises a silicon oxide layer.

4. The array substrate according to claim 1, characterized in that: The conductivity of the first shielding layer is greater than that of the second shielding layer, and the transmittance of the second shielding layer is greater than that of the first shielding layer; Preferably, the first shielding layer comprises a metal layer; Preferably, the second shielding layer comprises a conductive doped material; Preferably, the conductive doping material includes at least one of boron trifluoride, phosphine and arsine.

5. The array substrate according to claim 1, characterized in that: The first shielding layer is a mesh structure; Preferably, in a direction perpendicular to the substrate, the thickness of the second shielding layer does not exceed 100 angstroms; Preferably, the thickness of the second shielding layer is in the range of 30 angstroms to 100 angstroms.

6. The array substrate according to claim 1, characterized in that: The array substrate further includes a constant voltage signal line, and the first shielding layer is electrically connected to the constant voltage signal line.

7. A method for manufacturing an array substrate, characterized in that: The following steps are involved: providing a substrate base plate; Sequentially preparing two shielding layers on the substrate, the two shielding layers comprising a first shielding layer and a second shielding layer, the first shielding layer is in contact with the second shielding layer, wherein the first shielding layer is a patterned film layer, and the second shielding layer is an amorphous silicon layer; A plurality of thin film transistors are prepared on the side of the shielding layer prepared later away from the base substrate, and the orthographic projections of some of the thin film transistors on the base substrate are located within the orthographic projection range of the first shielding layer on the base substrate, and the orthographic projections of the plurality of thin film transistors on the base substrate are all located within the orthographic projection range of the second shielding layer on the base substrate.

8. The method for manufacturing an array substrate according to claim 7, characterized in that: The step of sequentially preparing two shielding layers on the substrate includes: A second shielding layer is formed on one side of the substrate, and a first shielding layer is formed on a side of the second shielding layer away from the substrate; or Prepare a first shielding layer on one side of the substrate, and prepare a second shielding layer on a side of the first shielding layer away from the substrate; Preferably, the second shielding layer covers the entire surface of the substrate substrate on a side close to the first shielding layer; Preferably, the second shielding layer is a patterned film layer.

9. The method for manufacturing an array substrate according to claim 8, characterized in that: The step of preparing a second shielding layer on one side of the substrate includes: preparing an amorphous silicon layer including a conductive doping material by a vapor deposition method; Preferably, the step of preparing the amorphous silicon layer including the conductive doping material by vapor deposition comprises: The amorphous silicon layer is prepared by a vapor deposition method; doping the amorphous silicon layer by ion implantation; Preferably, the first shielding layer is prepared on a side of the second shielding layer away from the base substrate, the first shielding layer is in contact with the second shielding layer, and the first shielding layer is a patterned film layer, further comprising: Etching the first shielding layer to obtain a patterned first shielding layer; Preferably, etching the first shielding layer further comprises: Controlling the etching degree by controlling the etching loss so that the thickness of the second shielding layer meets the preset requirements; Preferably, the thickness of the second shielding layer does not exceed 100 angstroms; Preferably, the thickness of the second shielding layer is in the range of 30 angstroms to 100 angstroms.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 6.

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