Filter chip, filter chip preparation method and filter device

Abstract

The invention relates to the technical field of filters, in particular to a filter chip and a preparation method thereof, and the filter chip comprises a piezoelectric substrate, an IDT electrode and a frequency modulation dielectric layer. The IDT electrodes are arranged on the piezoelectric substrate at intervals, and the frequency modulation dielectric layer covers the piezoelectric substrate and the IDT electrodes. Wherein the final thickness of the frequency modulation dielectric layer on the IDT electrode and the piezoelectric substrate is determined by a formula (1), and the formula (1) is as follows: H1 = [F1-(F2 + FS + FIDT)] / A, the H1 is the final thickness of the frequency modulation dielectric layer, the F1 is the target frequency of the frequency modulation dielectric layer, the F2 is the electrical frequency measurement value of the piezoelectric substrate after the IDT electrode is deposited, the FS is the electrical frequency influenced by the piezoelectric substrate, the FIDT is the frequency compensation value of the IDT electrode manufacturing process, and the A is the sensitivity coefficient. Therefore, the electrical stability of the filter chip can be effectively improved, and the product yield is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of filters, and in particular to a filter chip, a filter chip preparation method and a filter device, which can be used for elastic wave filters. Background Art

[0002] Elastic wave devices are solid devices that perform various functions by processing the acoustic signals propagating on the surface of a piezoelectric substrate using the characteristics of an acoustic-electric transducer. Elastic wave filters are mainly composed of a base material with piezoelectric properties and interdigital transducers (IDTs) made of metal thin films on the polished surface of the material.

[0003] At present, a known frequency bandwidth adjustment method is to uniformly cover the entire surface of the piezoelectric substrate of the filter including the interdigital electrodes with an insulating film, and etch the insulating film to provide a thickness according to the required frequency. The following describes the manufacturing process of the elastic wave filter according to this method.

[0004] First, a piezoelectric substrate is prepared. After the piezoelectric substrate is polished, a resist pattern formed of a photoresist is applied to the surface of the substrate using a known technique. Then, a metal film made of Al or Au with high conductivity is deposited thereon by a technique such as vapor deposition to provide a predetermined thickness.

[0005] Next, the obtained product is immersed in a solvent and then melted or peeled off simultaneously by ultrasonic radiation, so that the resist pattern and the metal film covering the resist pattern are removed. At this time, an IDT electrode having a desired pattern is formed by the remaining metal film.

[0006] Then, an insulating film made of a material such as SiO2 having an etching rate different from that of the electrodes is deposited on the entire piezoelectric substrate including the electrodes and attached by sputtering or chemical vapor deposition (CVD) or the like to provide a predetermined thickness.

[0007] The frequency is measured by applying an electrical signal to the electrode using a wafer prober, and the difference between the measured frequency and the target value is determined. The difference is then etched through the insulating film to zero, thus achieving frequency adjustment.

[0008] The traditional algorithm adjusts the thickness of the insulating film based on the difference between the measured frequency and the target value. However, this approach cannot ensure product yield and electrical stability.

[0009] It should be noted that the information disclosed in this background technology section is only intended to increase the understanding of the overall background of the present invention, and should not be regarded as acknowledging or suggesting in any form that the information constitutes prior art already known to a person skilled in the art. Summary of the invention

[0010] The invention provides a filter chip, which comprises a piezoelectric substrate, an IDT electrode and a frequency modulation dielectric layer.

[0011] The IDT electrodes are arranged on the piezoelectric substrate at intervals. The frequency modulation dielectric layer covers the piezoelectric substrate and the IDT electrodes. The final thickness of the frequency modulation dielectric layer on the IDT electrode and the piezoelectric substrate is determined by formula (1), which is as follows: H1 = [F1-(F2+△F S +△F IDT )] / A. H1 is the final thickness of the frequency modulated dielectric layer, F1 is the target frequency of the frequency modulated dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrode is deposited, △F S is the electrical frequency affected by the piezoelectric substrate,

[0012] △F IDT is the frequency compensation value of the IDT electrode process, and A is the sensitivity coefficient.

[0013] The present invention also provides a filter chip, which includes a piezoelectric substrate, an IDT electrode and a frequency modulation dielectric layer. The IDT electrodes are arranged on the piezoelectric substrate at intervals. The frequency modulation dielectric layer covers the piezoelectric substrate and the IDT electrodes. The final thickness of the frequency modulation dielectric layer is determined based on the thickness of the piezoelectric substrate, the spacing between the IDT electrodes and the deposition thickness of the frequency modulation dielectric layer.

[0014] The present invention also provides a method for preparing a filter chip, which comprises the following steps: forming spaced IDT electrodes on a piezoelectric substrate; depositing a frequency-modulated dielectric layer on the piezoelectric substrate and the IDT electrodes; and adjusting the frequency-modulated dielectric layer according to the thickness of the piezoelectric substrate, the spacing between the IDT electrodes and the deposited thickness of the frequency-modulated dielectric layer to obtain a final thickness of the frequency-modulated dielectric layer.

[0015] A filter chip and a preparation method thereof provided in one embodiment of the present invention determine the final thickness of the frequency modulation dielectric layer based on the thickness of the piezoelectric substrate, the spacing of the IDT electrodes and the deposition thickness of the frequency modulation dielectric layer. The final thickness of the frequency modulation dielectric layer can be adjusted more accurately, so that the filter chip can reach the required target frequency more accurately, adapt to product requirements, improve the electrical stability of the filter chip, ensure product yield, and improve the problem of low product yield caused by traditional algorithm deviation.

[0016] Other features and beneficial effects of the present invention will be described in the following description, and some of the technical features and beneficial effects can be obviously derived from the description or understood by implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1a is a partial cross-sectional schematic diagram of a filter chip provided by an embodiment of the present invention;

[0019] Figure 1b is a partial top view schematic diagram of a filter chip provided by an embodiment of the present invention;

[0020] Figures 2 to 5 is a schematic diagram of the structure of the filter chip shown in FIG1 at various stages in the manufacturing process;

[0021] Figure 6 It is a schematic flow chart of a filter chip manufacturing method provided by an embodiment of the present invention;

[0022] Figure 7 is a frequency distribution diagram of a filter wafer implemented according to the present invention;

[0023] Figure 8 This is the frequency distribution diagram of a traditional filter wafer;

[0024] Fig. 9 is a cross-sectional schematic diagram of a filter device implemented according to the present invention.

[0025] Reference numerals:

[0026] 1-filter chip; 10-support substrate; 12-piezoelectric substrate; 14-IDT electrode; 14a-IDT; 14b-reflector 16-frequency modulation dielectric layer; 22-wiring substrate; 24-bump; 26-sealing part; L1-interval between IDT electrodes; H2-thickness of piezoelectric substrate. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments; the technical features designed in different implementation modes of the present invention described below can be combined with each other as long as they do not conflict with each other; based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0028] In the description of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof all mean "at least including".

[0029] The filter chip disclosed in the following embodiments may be, for example, a substrate formed of a piezoelectric single crystal such as lithium tantalate, lithium niobate or crystal. The filter chip may also be, for example, a substrate formed of piezoelectric ceramics. The filter chip may also be, for example, a substrate formed by bonding a piezoelectric substrate and a supporting substrate. The supporting substrate may be, for example, a substrate formed of sapphire, silicon, alumina, spinel, crystal or glass. The filter chip is a substrate provided with functional components, for example, a receiving filter and a transmitting filter are provided on the main surface of the filter chip.

[0030] The following embodiments are described in detail by taking the bonding of a piezoelectric substrate and a supporting substrate as an example.

[0031] See also Figure 1a , Figure 1a 1 is a partial cross-sectional schematic diagram of a filter chip provided by an embodiment of the present invention. In order to achieve at least one of the above advantages or other advantages, an embodiment of the present invention provides a filter chip. As shown in the figure, the filter chip includes a piezoelectric substrate 12, an IDT electrode 14 and a frequency modulation dielectric layer 16.

[0032] In a preferred embodiment, the piezoelectric substrate 12 can be arranged on the supporting substrate 10, and the filter chip includes the supporting substrate 10, and the supporting substrate 10 is made of high-acoustic-velocity material. Specifically, the supporting substrate 10 is prepared by using a high-acoustic-velocity material, so that the supporting substrate 10 plays a supporting role and transmits signals as a high-acoustic-velocity medium. The supporting substrate 10 can be a substrate formed of a material selected from the group consisting of, for example, silicon carbide, aluminum oxide, aluminum nitride, sapphire, silicon nitride, silicon, spinel and magnesium oxide. In a preferred embodiment, the supporting substrate 10 is made of polycrystalline material, which is conducive to suppressing clutter. The piezoelectric substrate 12 has a piezoelectric effect, that is, when subjected to an external force, a charge distribution will be generated, thereby generating a voltage. The material of the piezoelectric substrate 12 can be lithium tantalate (LT) or lithium niobate (LN), but the present case is not limited thereto, and the material of the piezoelectric substrate 12 can also be other materials with relatively stable crystal structures, such as quartz. In some embodiments, the thickness H2 of the piezoelectric substrate 12 ranges from 0.5 to 5 μm. In a preferred embodiment, the thickness of the piezoelectric substrate is preferably 1.05-1.5 μm.

[0033] In some embodiments, a dielectric layer may be formed between the piezoelectric substrate 12 and the support substrate 10, and the dielectric layer may include a high acoustic velocity layer, a low acoustic velocity layer, or a combination of the two. The high acoustic velocity layer is made of any one of the following materials: aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride, DLC film or diamond, a material with any one of the aforementioned materials as a main component, or a material with a mixture of the aforementioned materials as a main component. The low acoustic velocity layer is made of any one of the following materials: silicon oxide, glass, silicon oxynitride, tantalum oxide, or a compound formed by adding fluorine, carbon or boron to silicon oxide, or a material with each of the above materials as a main component.

[0034] like Figure 1bAs shown, the main surface of the piezoelectric substrate 12 is provided with an IDT (Interdigital Transducer) 14a and a pair of reflectors 14b. The IDT 14a and the reflector 14b are provided to excite elastic surface waves. For example, the IDT 14a and the reflector 14b are made of an alloy of aluminum and copper. For example, the IDT 14a and the reflector 14b are made of a suitable metal such as titanium, palladium, silver, or an alloy thereof. For example, the IDT 14a and the reflector 14b can be a stacked metal film formed by stacking a plurality of metal layers. The thickness of the IDT 14a and the reflector 14b is, for example, between 150nm and 400nm. The IDT 14a has a pair of comb-shaped electrodes 14c. The comb-shaped electrodes 14c are opposite to each other. The comb-shaped electrodes 14c each have a plurality of electrode fingers 14d and a bus bar 14e. The electrode fingers 14d extend in the longitudinal direction. The bus bar 14e connects the electrode fingers 14d. One reflector 14b is adjacent to one side of the IDT 14a, and the other reflector 14b is adjacent to the other side of the IDT 14a. That is, the two reflectors 14b are respectively located on opposite sides of the IDT 14a, and are respectively located on the left and right sides of the IDT 14a in the illustrated embodiment.

[0035] The IDT electrodes 14 are arranged at intervals on the piezoelectric substrate 12. IDT (Inter Digital Transducer) is an interdigital transducer. By adding a high-frequency electrical signal to both ends of the IDT electrode 14, the surface of the piezoelectric substrate 12 will generate mechanical vibrations and simultaneously excite surface acoustic waves with the same frequency as the external electrical signal, and this surface acoustic wave will propagate along the surface of the piezoelectric substrate 12. If a pair of IDT electrodes 14 are made on the SAW (surface acoustic wave) propagation path, the SAW can be detected and converted into an electrical signal. The IDT electrode 14 can be formed on the piezoelectric substrate 12 by semiconductor planar process technology.

[0036] The frequency modulation dielectric layer 16 covers the piezoelectric substrate 12 and the IDT electrode 14. By adjusting the coverage thickness of the frequency modulation dielectric layer 16, the frequency of the filter chip can be changed so that the filter chip reaches the required target frequency and adapts to product requirements. The traditional confirmation of the thickness of the frequency modulation dielectric layer 16 is mainly based on the difference between the measured frequency and the target value to adjust the thickness of the frequency modulation dielectric layer 16. However, this approach cannot ensure the product yield and electrical stability. The inventor found in the experimental process that the deviation of the current traditional method is too large, mainly based on the following two aspects: 1. When the spacing L1 of the IDT electrode 14 is too large or too small, continuing to use the traditional algorithm will produce obvious deviations, resulting in a decrease in product yield; 2. When the thickness H2 of the piezoelectric substrate 12 is less uniform, the filter is greatly affected by the uniformity of the thickness of the piezoelectric substrate 12, resulting in the inability of the traditional algorithm to ensure the electrical stability of the product. Therefore, the inventor proposes to determine the final thickness of the frequency-modulating dielectric layer 16 based on the thickness H2 of the piezoelectric substrate 12, the spacing L1 of the IDT electrode 14 and the deposition thickness of the frequency-modulating dielectric layer 16, so as to achieve precise control of the frequency-modulating dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield.

[0037] In one embodiment, the final thickness of the frequency modulated dielectric layer 16 on the IDT electrode 14 and the piezoelectric substrate 12 can be determined by formula (1), which is as follows: H1 = [F1-(F2+ΔF S +△F IDT )] / A. H1 is the final thickness of the frequency modulated dielectric layer 16. The frequency modulated dielectric layer 16 is etched according to H1, and the remaining thickness of the frequency modulated dielectric layer 16 is the final thickness. F1 is the target frequency of the frequency modulated dielectric layer 16, that is, the target frequency that the filter chip needs to achieve. F2 is the electrical frequency measurement value of the piezoelectric substrate 12 after the IDT electrode 14 is deposited (that is, the electrical frequency measurement value when it is not covered with the frequency modulated dielectric layer 16). △F S is the electrical frequency affected by the piezoelectric substrate 12. IDT is the frequency compensation value of the IDT electrode 14 process, and A is the sensitivity coefficient. It should be noted that the final thickness of the frequency modulated dielectric layer 16 on the IDT electrode 14 and the final thickness on the piezoelectric substrate 12 may be different. The final thickness of the frequency modulated dielectric layer 16 on the IDT electrode 14 and the final thickness on the piezoelectric substrate 12 can be accurately determined by the above formula (1) to ensure the quality of the filter chip, and the final thickness of the frequency modulated dielectric layer 16 at various locations on the piezoelectric substrate 12 can also be determined based on the surface flatness of the piezoelectric substrate 12 (the surface flatness of the piezoelectric substrate 12 will affect the thickness H2 of the piezoelectric substrate 12).

[0038] Since F = V / λ, the thickness H2 of the piezoelectric substrate 12 will affect the propagation speed of the surface acoustic wave. When λ is constant, the thinner the piezoelectric substrate 12 is, the larger V and F are. According to the change of substrate thickness and the change of F frequency, λ, i.e., the influence coefficient of the spacing L1 of the IDT electrode 14 on the frequency, the relationship between △V and substrate thickness can be calculated as △F S =ΔV / λ, ΔV is the propagation velocity of the surface acoustic wave in the piezoelectric substrate 12, and λ is the influence coefficient of the interval L1 of the IDT electrodes 14 on the frequency.

[0039] △F IDT is a constant value, determined according to the IDT electrode 14 that has been formed. Since the photolithography development equipment is stable and unchanged, ΔF IDT For example, when the IDT electrode 14 is a three-layer stacked structure of Ti / AlCu / Ti, the thicknesses of Ti / AlCu / Ti are 30nm, 135nm, and 15nm respectively, the doping ratio of Al and Cu is 98.5:1.5, and the IDT angle of the photolithography development equipment is controlled between 70°±10°, then △F IDT The value is -2.019. When the IDT electrode 14 is a three-layer stacked structure of Ti / AlCu / Ti, the thicknesses are 30nm, 160nm, and 15nm respectively, the Al and Cu doping ratios are 98.5:1.5, and the IDT angle of the photolithography development equipment is controlled between 70°±10°, then △F IDT It is -1.4186.

[0040] A is the sensitivity coefficient of the product, which is a constant term determined based on the chip product. The value fluctuates within the range of 0.5 to 0.6.

[0041] In some embodiments, the material of the frequency modulation dielectric layer 16 includes SiO2. Further, when the material of the frequency modulation dielectric layer 16 is SiO2, formula (1) can be transformed into formula (2), which is as follows: H1 = {F1-[F2+(H2-1.540) / 0.064]-2.019} / A, H2 is the thickness of the piezoelectric substrate 12, and A = 0.535±10% (i.e., 0.4815-0.5885), so as to accurately control the final thickness of the frequency modulation dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield.

[0042] See also Figures 2 to 5 , Figures 2 to 5 It is a schematic diagram of the structure of the filter chip shown in Figure 1 at various stages in the manufacturing process. A method for manufacturing the filter chip shown in Figure 1 is disclosed below.

[0043] First, if Figure 2As shown, a thicker support substrate 10 is provided, and the support substrate 10 can be a substrate made of silicon carbide, aluminum oxide, aluminum nitride, sapphire, silicon nitride, silicon, spinel, magnesium oxide, etc. Then, a thinner piezoelectric substrate 12 is formed on the support substrate 10, and the thickness H2 of the piezoelectric substrate 12 is measured, and the thickness H2 of the piezoelectric substrate 12 can be 0.5-5 μm.

[0044] Secondly, if Figure 3 As shown, an IDT electrode 14 is formed on a piezoelectric substrate 12. The IDT electrode 14 is made of a metal material, such as Ti, Al, Cu, Pt, Au, Ag or Pd, or an alloy containing at least two of the aforementioned metals. After the IDT electrode 14 is formed, the first electrical data measurement is performed to obtain an initial frequency F2. In addition, the spacing L1 of the IDT electrode 14 is measured to confirm the influence coefficient λ of the spacing L1 of the IDT electrode 14 on the frequency.

[0045] Then, if Figure 4 As shown, a frequency-modulated dielectric layer 16 is formed on the piezoelectric substrate 12 and the IDT electrode 14. The frequency-modulated dielectric layer 16 covers the piezoelectric substrate 12 and the IDT electrode 14. The frequency-modulated dielectric layer 16 can be made of SiO2.

[0046] Finally, if Figure 5 As shown, the final thickness of the frequency modulated dielectric layer 16 is determined according to the thickness H2 of the piezoelectric substrate 12, the spacing L1 of the IDT electrode 14 and the deposition thickness of the frequency modulated dielectric layer 16. For example, the final thickness of the frequency modulated dielectric layer 16 in each region is determined by formula (1), and the frequency modulated dielectric layer 16 is plasma bombarded and etched by gas to obtain the final thickness H1, so as to achieve precise control of the frequency modulated dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield. The gas used can be an inert gas, such as Ar, He, etc.; the parameter conditions can be as follows: gas flow rate is 2 to 10 sccm; ACC voltage is 300 to 1000V; Beam current is 10 to 50mA; Beam voltage is 1000 to 2000V; Trimming angle is 90 to 150°C; RF Power is 50 to 500W.

[0047] The above is only a disclosed method for manufacturing the filter chip shown in FIG. 1 , and the present invention is not limited thereto. It is only used to illustrate a method for manufacturing the filter chip.

[0048] Please combine Figures 2 to 5 See also Figure 6 , Figure 61 is a flow chart of a filter chip preparation method provided by an embodiment of the present invention. An embodiment of the present invention also provides a filter chip preparation method, as shown in the figure, the filter chip preparation method comprises the following steps:

[0049] S100: IDT electrodes 14 are formed on the piezoelectric substrate 12. Then, the first electrical data measurement is performed to obtain F2, and the spacing L1 of the IDT electrodes 14 is measured to confirm the influence coefficient λ of the spacing L1 of the IDT electrodes 14 on the frequency. Prior to this, the thickness H2 of the piezoelectric substrate 12 can be measured first.

[0050] S200 : depositing a frequency tuning dielectric layer 16 on the piezoelectric substrate 12 and the IDT electrode 14 .

[0051] S300: Adjust the frequency modulated dielectric layer 16 according to the thickness H2 of the piezoelectric substrate 12, the spacing L1 of the IDT electrodes 14, and the deposition thickness of the frequency modulated dielectric layer 16 to obtain the final thickness of the frequency modulated dielectric layer 16 in each region. Subsequently, the frequency modulated dielectric layer 16 is plasma bombarded and etched using argon gas to achieve precise control of the frequency modulated dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield.

[0052] The final thickness of the frequency modulated dielectric layer 16 on the IDT electrode 14 and the piezoelectric substrate 12 can be determined by formula (1), which is as follows: H1 = [F1-(F2+ΔF S +△F IDT )] / A. H1 is the final thickness of the frequency modulated dielectric layer 16. The remaining thickness of the frequency modulated dielectric layer 16 after etching the frequency modulated dielectric layer 16 according to H1 is the final thickness. F1 is the target frequency of the frequency modulated dielectric layer 16, that is, the target frequency that the filter chip needs to achieve. F2 is the electrical frequency measurement value of the piezoelectric substrate 12 after the IDT electrode 14 is deposited. △F S is the electrical frequency affected by the piezoelectric substrate 12. IDT is the frequency compensation value of the IDT electrode 14 process, and A is the sensitivity coefficient.

[0053] △F S =△V / λ, △V is the propagation speed of the surface acoustic wave in the piezoelectric substrate 12, and λ is the influence coefficient of the spacing L1 of the IDT electrode 14 on the frequency. △F IDT is a constant value, which is determined according to the formed IDT electrode 14. A is the sensitivity coefficient of the product, which is a constant term determined according to the chip product, and the value fluctuates within the range of 0.5 to 0.6.

[0054] Furthermore, when the material of the frequency-modulated dielectric layer 16 is SiO2, formula (1) can be transformed into formula (2), which is as follows: H1 = {F1-[F2+(H2-1.540) / 0.064]-2.019} / A, H2 is the thickness of the piezoelectric substrate 12, and A = 0.535±10%, so as to accurately control the final thickness of the frequency-modulated dielectric layer 16, so that the filter chip can more accurately reach the required target frequency, adapt to product requirements, improve the electrical stability of the filter chip, and ensure product yield.

[0055] Tables 1 and 2 below are comparison tables of the old algorithm and the new algorithm using the above embodiment. As can be seen from the table, the filter chip prepared using the method of the present invention has a significant improvement in both yield and product performance compared to the filter chip prepared using the traditional algorithm. Regarding the influence of key electrical measurement parameters, the overall frequency converges by about 25%; the product yield is improved by about 4%.

[0056] Table 1

[0057]

[0058] Table 2

[0059]

[0060] like Figure 7 and Figure 8 As shown in the comparison, the frequency distribution diagram of the wafer of the traditional algorithm has obvious ring distribution, which is strongly related to the substrate thickness, which will deteriorate the frequency convergence and cause some point electrical measurement data to exceed the specification, thereby affecting the product yield. However, the filter chip prepared by the method of the present invention has no obvious distribution characteristics in its wafer diagram, and the frequency uniformity PPM within the chip converges about 25% compared with the old algorithm, and the yield is improved by about 4.2%.

[0061] A filter chip and a preparation method thereof provided in one embodiment of the present invention determine the final thickness of the frequency modulation dielectric layer 16 based on the thickness H2 of the piezoelectric substrate 12, the spacing L1 of the IDT electrode 14 and the deposition thickness of the frequency modulation dielectric layer 16. The final thickness of the frequency modulation dielectric layer 16 can be adjusted more accurately, so that the filter chip can reach the required target frequency more accurately, adapt to product requirements, improve the electrical stability of the filter chip, ensure product yield, and improve the problem of low product yield caused by traditional algorithm deviation.

[0062] See also Fig. 9 , Fig. 9 Schematic diagram of a cross-sectional view of a filter device implemented according to the present invention. Fig. 9 As shown, the filter device includes a wiring substrate 22, a plurality of bumps 24, a filter chip 1 and a sealing portion 26. The bumps 24 are electrically connected to the main surface ( Fig. 9 The bump 24 is also electrically connected to the wiring substrate 22. The filter chip 1 is bonded to the wiring substrate 22 via the bump 24. The sealing portion 26 is provided on the wiring substrate 22 and covers the filter chip 1.

[0063] The wiring substrate 22 may be a multi-layer substrate made of resin, or a low temperature co-fired ceramic (LTCC) multi-layer substrate formed of multiple dielectric layers. The bumps 24 may be gold bumps, for example, and the height of the bumps 24 may be between 20 μm and 50 μm.

[0064] The specific design of the filter chip 1 may refer to the detailed description of the filter chip in the above-mentioned embodiment.

[0065] In addition, those skilled in the art should understand that, although there are many problems in the prior art, each embodiment or technical solution of the present invention can be improved in only one or several aspects, without having to solve all the technical problems listed in the prior art or background technology at the same time. Those skilled in the art should understand that the content not mentioned in a claim should not be used as a limitation on the claim.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A filter chip, characterized in that: The filter chip comprises: Piezoelectric substrate; IDT electrodes are arranged on the piezoelectric substrate at intervals; A frequency modulated dielectric layer covering the piezoelectric substrate and the IDT electrode; The final thickness of the frequency modulated dielectric layer on the IDT electrode and the piezoelectric substrate is determined by formula (1), which is as follows: H1=[F1-(F2+△F S +△F IDT )] / A (1) H1 is the final thickness of the frequency modulated dielectric layer, F1 is the target frequency of the frequency modulated dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrode is deposited, △F S is the electrical frequency affected by the piezoelectric substrate, ΔF IDT is the frequency compensation value of the IDT electrode process, and A is the sensitivity coefficient.

2. The filter chip according to claim 1, characterized in that: △F S =△V / λ, △V is the propagation speed of the surface acoustic wave in the piezoelectric substrate, and λ is the influence coefficient of the spacing of the IDT electrodes on the frequency.

3. The filter chip according to claim 1, characterized in that: The value range of A is 0.5~0.

6.

4. The filter chip according to claim 1, characterized in that: The material of the piezoelectric substrate includes lithium tantalate or lithium niobate.

5. The filter chip according to claim 1, characterized in that: The material of the frequency modulation dielectric layer includes SiO2.

6. The filter chip according to claim 5, characterized in that: When the material of the frequency modulation dielectric layer is SiO2, the formula (1) is transformed into the formula (2), and the formula (2) is as follows: H1 = {F1 - [F2 + (H2 - 1.540) / 0.064] - 2.019} / A, H2 is the thickness of the piezoelectric substrate, and A = 0.535 ± 10%.

7. A filter chip, characterized in that: The filter chip comprises: Piezoelectric substrate; IDT electrodes are arranged on the piezoelectric substrate at intervals; A frequency modulated dielectric layer covering the piezoelectric substrate and the IDT electrode; The final thickness of the frequency modulation dielectric layer is determined according to the thickness of the piezoelectric substrate, the spacing between the IDT electrodes and the deposition thickness of the frequency modulation dielectric layer.

8. The filter chip according to claim 7, characterized in that: The final thickness of the frequency modulated dielectric layer is determined by formula (1), which is as follows: H1=[F1-(F2+△F S +△F IDT )] / A (1) H1 is the final thickness of the frequency modulated dielectric layer, F1 is the target frequency of the frequency modulated dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrode is deposited, △F S is the electrical frequency affected by the piezoelectric substrate, ΔF IDT is the frequency compensation value of the IDT electrode process, and A is the sensitivity coefficient.

9. The filter chip according to claim 8, characterized in that: △F S =△V / λ, △V is the propagation speed of the surface acoustic wave in the piezoelectric substrate, and λ is the influence coefficient of the spacing of the IDT electrodes on the frequency.

10. The filter chip according to claim 8, characterized in that: The value range of A is 0.5~0.

6.

11. A method for preparing a filter chip, characterized in that: The preparation method of the filter chip comprises the following steps: forming IDT electrodes spaced apart on a piezoelectric substrate; depositing a frequency-tuned dielectric layer on the piezoelectric substrate and the IDT electrode; The frequency modulated dielectric layer is adjusted according to the thickness of the piezoelectric substrate, the interval between the IDT electrodes and the deposition thickness of the frequency modulated dielectric layer to obtain a final thickness of the frequency modulated dielectric layer.

12. The method for preparing a filter chip according to claim 11, characterized in that: The final thickness of the frequency modulated dielectric layer is determined by formula (1), which is as follows: H1=[F1-(F2+△F S +△F IDT )] / A (1) H1 is the final thickness of the frequency modulated dielectric layer, F1 is the target frequency of the frequency modulated dielectric layer, F2 is the measured value of the electrical frequency of the piezoelectric substrate after the IDT electrode is deposited, △F S is the electrical frequency affected by the piezoelectric substrate, ΔF IDT is the frequency compensation value of the IDT electrode process, and A is the sensitivity coefficient.

13. The method for preparing a filter chip according to claim 12, characterized in that: △F S =△V / λ, △V is the propagation speed of the surface acoustic wave in the piezoelectric substrate, and λ is the influence coefficient of the spacing of the IDT electrodes on the frequency.

14. The method for preparing a filter chip according to claim 12, characterized in that: The value range of A is 0.5~0.

6.

15. The method for preparing a filter chip according to claim 11, characterized in that: The material of the piezoelectric substrate includes lithium tantalate or lithium niobate.

16. The method for preparing a filter chip according to claim 11, characterized in that: The material of the frequency modulation dielectric layer includes SiO2.

17. A filter device, characterized in that: The filter device includes the filter chip according to any one of claims 1 to 10, wherein the filter chip is an elastic wave chip.

18. The filter device according to claim 17, characterized in that: The filter device further includes a wiring substrate and a sealing portion, the filter chip is disposed on the wiring substrate, and the sealing portion seals the filter chip.

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