Capacitor structure, preparation method thereof and semiconductor structure
By removing hanging bonds on the surfaces of the dielectric layer and the anti-reflective layer of the metal capacitor MIM and forming a charge barrier layer, the problem of charge accumulation of the dielectric layer is solved, the TDDB performance is improved, and the chip life is extended.
Patent Information
- Application Number
- CN202411574696.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2024-12-31
AI Technical Summary
When preparing metal capacitor MIM, charges are easily accumulated on the surface of the dielectric layer and the side walls of the trench, resulting in poor TDDB performance, affecting chip life and normal operation.
By removing hanging bonds on the exposed surfaces of the anti-reflective layer and the first dielectric layer, and forming a charge barrier layer thereon, a high-density plasma chemical vapor deposition process is used to form the second dielectric layer to avoid plasma charge accumulation. Finally, The through holes are etched to connect the electrode layer.
It effectively improves the TDDB performance of the capacitance structure, prevents charge accumulation, extends the device life and ensures normal operation.
Smart Images
Figure CN119233750A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a capacitor structure and a preparation method thereof, and a semiconductor structure. Background Art
[0002] With the development of integrated circuits and the improvement of chip integration, the size of devices has been reduced, and the electric field strength inside the devices has become higher and higher, making breakdown more likely. Time-dependent dielectric breakdown (TDDB) is the main failure mechanism that affects the life of chips and long-term normal operation. TDDB is caused by the generation and accumulation of defects inside the dielectric layer during the application of electrical stress.
[0003] Currently, in analog circuits and RF circuits, metal capacitors MIM (Metal Insulator Metal) are usually made on interconnects to overcome the defects of large parasitic capacitance and significant decrease in device performance as the circuit frequency increases. In the process of preparing metal capacitor MIM, charges are easily accumulated on the surface of the dielectric layer and the sidewalls of the trench, resulting in a weakening of the dielectric layer performance, which in turn leads to a deterioration of the TDDB performance of the device. Summary of the invention
[0004] Based on this, it is necessary to provide a capacitor structure and a preparation method thereof, and a semiconductor structure that can improve the TDDB performance of the capacitor structure.
[0005] In order to achieve the above object, on the one hand, the present invention provides a method for preparing a capacitor structure, comprising:
[0006] Providing a substrate, the substrate comprising a substrate and a first electrode layer, a first dielectric layer, a second electrode layer and an anti-reflection layer sequentially formed on the substrate;
[0007] Etching the anti-reflection layer, the second electrode layer and a portion of the first dielectric layer to form a capacitor trench;
[0008] Performing a dangling bond removal process on the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove;
[0009] forming a charge blocking layer on the exposed surfaces of the anti-reflection layer and the first dielectric layer, wherein the charge blocking layer is used to combine with the plasma to achieve blocking of the plasma charges;
[0010] Forming a second dielectric layer on the charge blocking layer by using a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process;
[0011] The second dielectric layer, the charge blocking layer and the substrate are etched to form a through hole.
[0012] In one embodiment, the step of removing dangling bonds from the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove includes:
[0013] Under preset temperature conditions, preset pressure conditions, and preset power conditions, subjecting the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove to nitrous oxide atmosphere treatment;
[0014] Wherein, under the preset temperature condition, the preset pressure condition and the preset power condition, the nitrous oxide is ionized to generate oxygen ions, and the oxygen ions are combined with the dangling bonds.
[0015] In one embodiment, forming a charge blocking layer on the exposed surfaces of the anti-reflection layer and the first dielectric layer comprises:
[0016] Silicon-rich oxide is deposited on the exposed surfaces of the anti-reflection layer and the first dielectric layer to form the charge blocking layer.
[0017] In one embodiment, etching the second dielectric layer, the charge blocking layer and the substrate to form a through hole comprises:
[0018] Etching the second dielectric layer, the charge blocking layer and the anti-reflection layer to form a first through hole;
[0019] The second dielectric layer, the charge blocking layer, the anti-reflection layer, the second electrode layer and the first dielectric layer are etched to form a second through hole.
[0020] In one embodiment, the method further comprises:
[0021] Before forming the first electrode layer, depositing a first barrier layer material on the substrate to form a first barrier layer;
[0022] Before forming the first dielectric layer, a second barrier layer material is deposited on the first electrode layer to form a second barrier layer.
[0023] In one embodiment, the first dielectric layer includes silicon nitride, and the anti-reflection layer includes silicon oxynitride.
[0024] In one embodiment, the charge blocking layer has a thickness of 100 angstroms to 200 angstroms.
[0025] In a second aspect, the present application also provides a capacitor structure, including:
[0026] substrate;
[0027] A first electrode layer, located on the substrate;
[0028] A first dielectric layer, located on the first electrode layer;
[0029] a second electrode layer, located on a portion of the first dielectric layer; wherein a thickness of a portion of the first dielectric layer covered by the second electrode layer relative to the first electrode layer is greater than a thickness of a portion of the first dielectric layer not covered by the second electrode layer;
[0030] an anti-reflection layer, located on the second electrode layer;
[0031] A charge blocking layer, located on the exposed surfaces of the anti-reflection layer and the first dielectric layer;
[0032] a second dielectric layer, located on the charge blocking layer;
[0033] a first through hole, penetrating the second dielectric layer, the charge blocking layer and the anti-reflection layer;
[0034] The second through hole penetrates the second dielectric layer, the charge blocking layer, the anti-reflection layer, the second electrode layer and the first dielectric layer.
[0035] In one embodiment, the capacitor structure further includes:
[0036] a first barrier layer, located between the substrate and the first electrode layer;
[0037] The second barrier layer is located between the first electrode layer and the first dielectric layer.
[0038] In a third aspect, the present application further provides a semiconductor structure, including a capacitor structure prepared by the preparation method provided by any of the above embodiments, or including a capacitor structure provided by any of the above embodiments.
[0039] In the above capacitor structure and its preparation method, and semiconductor structure, a substrate including a substrate and a first electrode layer, a first dielectric layer, a second electrode layer, and an anti-reflection layer formed sequentially on the substrate is provided, and the anti-reflection layer, the second electrode layer, and a portion of the first dielectric layer are etched to form a capacitor groove. Further, the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove are subjected to a dangling bond removal process to avoid the accumulation of charges on the exposed surfaces of the anti-reflection layer and the first dielectric layer in subsequent process steps. Afterwards, a charge blocking layer is formed on the exposed surfaces of the anti-reflection layer and the first dielectric layer, and a second dielectric layer is formed on the charge blocking layer using a high-density plasma chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process. The charge blocking layer can be combined with the plasma generated by the high-density plasma chemical vapor deposition process or the plasma-enhanced chemical vapor deposition process to achieve the blocking of plasma charges and avoid the accumulation of plasma charges on the surface of the anti-reflection layer and the surface of the first dielectric layer. Finally, the second dielectric layer, the charge blocking layer, and the substrate are etched to form a through hole for connecting the first electrode layer and the second electrode layer. Since the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove are treated to remove dangling bonds, and a charge blocking layer is provided to block plasma charges, charge accumulation on the surfaces of the first dielectric layer and the anti-reflection layer is avoided, thereby improving the TDDB performance of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0041] Figure 1 is a flow chart of a method for preparing a capacitor structure provided in an embodiment;
[0042] Figure 2 A schematic diagram of a cross-sectional structure of a structure obtained in step S200 in a method for preparing a capacitor structure provided in an embodiment;
[0043] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained in step S500 in a method for preparing a capacitor structure provided in an embodiment;
[0044] Figure 4 A schematic diagram of a cross-sectional structure of a structure obtained in step S600 in a method for preparing a capacitor structure provided in an embodiment;
[0045] FIG5( a ) is a TEM image of the first dielectric layer without the previous dangling bond treatment;
[0046] Figure 5(b) is the EDS (energy spectrum) analysis diagram of Si element in Figure 5(a);
[0047] Figure 5 (c) is the EDS (energy spectrum) analysis diagram of the N element in Figure 5 (a);
[0048] FIG6 (a) is a TEM image of the first dielectric layer after the dangling bond removal treatment;
[0049] Figure 6 (b) is the EDS (energy spectrum) analysis diagram of Si element in Figure 6 (a);
[0050] Figure 6 (c) is the EDS (energy spectrum) analysis diagram of the N element in Figure 6 (a);
[0051] Figure 6 (d) is the EDS (energy spectrum) analysis diagram of the O element in Figure 6 (a);
[0052] FIG7( a ) is a TEM image of an antireflection layer without the previous dangling bond treatment;
[0053] Figure 7(b) is the EDS (energy spectrum) analysis diagram of Si element in Figure 5(a);
[0054] Figure 7(c) is the EDS (energy spectrum) analysis diagram of the O element in Figure 7(a);
[0055] Figure 7 (d) is the EDS (energy spectrum) analysis diagram of the N element in Figure 7 (a);
[0056] Figure 8 (a) is a TEM image of the antireflection layer after the dangling bond removal treatment;
[0057] Figure 8 (b) is the EDS (energy spectrum) analysis diagram of Si element in Figure 8 (a);
[0058] Figure 8 (c) is the EDS (energy spectrum) analysis diagram of the O element in Figure 8 (a);
[0059] Figure 8 (d) is the EDS (energy spectrum) analysis diagram of the N element in Figure 8 (a);
[0060] Fig. 9 A schematic diagram of the cross-sectional structure of a structure obtained by a method for preparing a capacitor structure provided in another embodiment.
[0061] Description of reference numerals:
[0062] 100-substrate, 200-first electrode layer, 300-first dielectric layer, 400-second electrode layer, 500-anti-reflection layer, 600-capacitor groove, 700-charge blocking layer, 800-second dielectric layer, 900-through hole, 910-first through hole, 920-second through hole, 1000-first blocking layer, 1100-second blocking layer. DETAILED DESCRIPTION
[0063] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0065] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below may be represented as a second element, component, region, layer or part; for example, the first electrode layer may be referred to as the second electrode layer, and similarly, the second electrode layer may be referred to as the first electrode layer; the first electrode layer and the second electrode layer are electrodes with different capacitor structures.
[0066] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0067] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0068] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.
[0069] At present, in analog circuits and RF circuits, metal capacitors MIM (Metal Insulator Metal) are usually made on interconnects to overcome the defects of large parasitic capacitance and significant decrease in device performance as the circuit frequency increases. When preparing metal capacitor MIM according to the traditional process, it is easy to cause etching damage to the bottom of the capacitor groove during the process of etching to form the metal capacitor groove, and it is easy to accumulate charges on the surface of the film layer when the dielectric layer is subsequently deposited in the capacitor groove and on the electrode. In addition, due to the presence of dangling bonds in the capacitor dielectric layer, it is easy to accumulate charges on the side walls of the capacitor dielectric layer during the process of etching to form a through hole for connecting the upper plate and the lower plate. These situations will lead to the weakening of the TDDB performance of the metal capacitor MIM.
[0070] Based on this, Figure 1 As shown, the present application proposes a method for preparing a capacitor structure, including steps S100-S600.
[0071] S100, providing a substrate, wherein the substrate includes a substrate and a first electrode layer, a first dielectric layer, a second electrode layer and an anti-reflection layer sequentially formed on the substrate.
[0072] like Figure 2As shown, a deposition process such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma deposition (HDP) can be used to sequentially form a first electrode layer 200, a first dielectric layer 300, a second electrode layer 400 and an anti-reflection layer 500 on a substrate 100. The first electrode layer 200 and the second electrode layer 400 can be used as the upper and lower electrode plates of the capacitor, the first dielectric layer 300 can be used as an insulating medium between the two electrode plates, and the anti-reflection layer 500 can absorb light passing through the photoresist when the second electrode layer 400 is subsequently patterned, thereby reducing the influence of the standing wave effect.
[0073] The substrate material may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as aluminum oxide, quartz or glass substrates, etc., which are not limited in this embodiment. The substrate 100 may include an interconnection structure. The materials of the first electrode layer 200 and the second electrode layer 400 may be metal materials such as aluminum and copper, the material of the first dielectric layer 300 may be silicon nitride, and the material of the anti-reflection layer 500 may be silicon oxynitride or the like.
[0074] S200, etching the anti-reflection layer, the second electrode layer 4 and a portion of the first dielectric layer to form a capacitor trench.
[0075] Please continue reading Figure 2 The anti-reflection layer 500 , the second electrode layer 400 and a portion of the first dielectric layer 300 may be etched by an etching process to form a capacitor trench 600 .
[0076] S300, performing a dangling bond removal process on the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove.
[0077] It can be understood that there are dangling bonds in the anti-reflection layer 500 and the first dielectric layer 300. These dangling bonds will cause charges to accumulate on the surfaces of the anti-reflection layer 500 and the first dielectric layer 300 when the dielectric layer is subsequently deposited. Therefore, it is necessary to remove the dangling bonds from the exposed surface of the anti-reflection layer 500 and the surface of the first dielectric layer 300 exposed by the capacitor groove 600.
[0078] S400, forming a charge blocking layer on the exposed surfaces of the anti-reflection layer and the first dielectric layer, wherein the charge blocking layer is used to combine with the plasma to achieve blocking of plasma charges.
[0079] like Figure 3 As shown, the charge blocking layer 700 may be formed on the exposed surfaces of the anti-reflection layer 500 and the first dielectric layer 300 by chemical vapor deposition (CVD).
[0080] S500, forming a second dielectric layer on the charge blocking layer by using a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.
[0081] Please continue reading Figure 3 The second dielectric layer 800 may be formed on the charge blocking layer 700 by using a high density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. The second dielectric layer 800 may serve as an insulating layer between the second electrode layer 400 and other metal layers formed subsequently.
[0082] It can be understood that, in the process of forming the second dielectric layer 800 on the charge blocking layer 700 by using the high-density plasma chemical vapor deposition process, the charge blocking layer 700 can be combined with the plasma generated by the high-density plasma chemical vapor deposition process to prevent the plasma from accumulating on the surfaces of the first dielectric layer 300 and the anti-reflection layer 500. Alternatively, in the process of forming the second dielectric layer 800 on the charge blocking layer 700 by using the plasma-enhanced chemical vapor deposition process, the charge blocking layer 700 can be combined with the plasma generated by the plasma-enhanced chemical vapor deposition process to prevent the plasma from accumulating on the surfaces of the first dielectric layer 300 and the anti-reflection layer 500.
[0083] S600, etching the second dielectric layer, the charge blocking layer and the substrate to form a through hole.
[0084] like Figure 4 As shown, the through holes can be used to lead out the first electrode layer 200 and the second electrode layer 400 to connect with other structures.
[0085] In an embodiment of the present application, a substrate including a substrate 100 and a first electrode layer 200, a first dielectric layer 300, a second electrode layer 400 and an anti-reflection layer 500 sequentially formed on the substrate 100 is provided, the anti-reflection layer 500, the second electrode layer 400 and a portion of the first dielectric layer 300 are etched to form a capacitor groove 600, and further, a dangling bond removal treatment is performed on the exposed surface of the anti-reflection layer 500 and the surface of the first dielectric layer 300 exposed by the capacitor groove 600 to avoid charge accumulation on the exposed surfaces of the anti-reflection layer 500 and the first dielectric layer 300 in subsequent process steps. Afterwards, a charge blocking layer 700 is formed on the exposed surfaces of the anti-reflection layer 500 and the first dielectric layer 300, and a second dielectric layer 800 is formed on the charge blocking layer 700 by using a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process. The charge blocking layer 700 can be combined with the plasma generated by the high-density plasma chemical vapor deposition process or the plasma enhanced chemical vapor deposition process to achieve the blocking of plasma charges and prevent the plasma charges from accumulating on the surfaces of the anti-reflection layer 500 and the first dielectric layer 300. Finally, the second dielectric layer 800, the charge blocking layer 700 and the substrate are etched to form a through hole for connecting the first electrode layer 200 and the second electrode layer 400. Since the exposed surface of the anti-reflection layer 500 and the surface of the first dielectric layer 300 exposed by the capacitor groove 600 are subjected to a dangling bond removal process, and the charge blocking layer 700 is provided to block the plasma charges, the accumulation of charges on the surfaces of the first dielectric layer 300 and the anti-reflection layer 500 is prevented, thereby improving the TDDB performance of the capacitor structure.
[0086] In one embodiment, the exposed surface of the anti-reflective layer and the surface of the first dielectric layer exposed by the capacitor groove are subjected to a dangling bond removal treatment, including the step of subjecting the exposed surface of the anti-reflective layer and the surface of the first dielectric layer exposed by the capacitor groove to a nitrous oxide atmosphere treatment under preset temperature conditions, preset pressure conditions, and preset power conditions.
[0087] Exemplarily, the preset temperature condition may be 350°C-400°C, for example, 350°C, 360°C, 370°C, 380°C, 390°C or 400°C. The preset pressure condition may be 1.2torr-5torr, for example, 1.2torr, 3 torr, 4torr or 5 torr, etc. The preset power condition may be 600W-3000W, for example, 600W, 1200W, 2400W or 3000W, etc. The reaction time may be 30s-60s, for example, 30s, 40s, 50s or 60s, etc. The preset temperature condition, the preset pressure condition, the preset power condition and the reaction time may be reasonably set according to the actual business scenario, and the embodiments of the present application are not limited here.
[0088] Under the preset temperature, pressure and power conditions, nitrous oxide ionizes to form oxygen ions, which can combine with dangling bonds. Nitrous oxide ionizes in the plasma state to form N2, NO, NO - Ions and O - ions, among which O - The ions can combine with the dangling bonds on the exposed surface of the anti-reflection layer 500 and the exposed surface of the first dielectric layer 300, thereby achieving the purpose of removing the dangling bonds. In addition, the N2 and NO generated by the ionization of nitrous oxide can also be used to remove impurities remaining on the surface of the first dielectric layer 300 when etching to form the capacitor groove 600.
[0089] Taking the first dielectric layer 300 as a silicon nitride film as an example, FIG5(a) is a TEM image (transmission electron microscope scanning image) of the first dielectric layer 300 (silicon nitride film) without the dangling bond treatment, FIG5(b) is an EDS (energy spectrum) analysis image of the Si element in FIG5(a), and FIG5(c) is an EDS (energy spectrum) analysis image of the N element in FIG5(a). FIG6(a) is a TEM image of the first dielectric layer 300 after the dangling bond removal treatment. FIG6(b) is an EDS (energy spectrum) analysis image of the Si element in FIG6(a), FIG6(c) is an EDS (energy spectrum) analysis image of the N element in FIG6(a), and FIG6(d) is an EDS (energy spectrum) analysis image of the O element in FIG6(a). It can be seen from FIG5(a)-FIG5(c) and FIG6(a)-FIG6(d) that there is a thin oxide layer on the surface of the silicon nitride film. There are some Si-H dangling bonds and NH dangling bonds in the silicon nitride film. The O - The ions can combine with Si atoms and N atoms in the silicon nitride film to form Si-O bonds and Si-N bonds, replacing the positions of Si-H dangling bonds and NH dangling bonds, thereby improving the stability of the silicon nitride film. In addition, after nitrous oxide is introduced into the exposed surface of the first dielectric layer 300, a thin oxide layer is formed on the surface of the first dielectric layer 300. This thin oxide layer can reduce etching damage in subsequent etching processes and further reduce the accumulation of plasma charges on the surface of the first dielectric layer 300 during the subsequent deposition of film layers using a high-density plasma chemical vapor deposition process or a plasma-enhanced chemical vapor deposition process.
[0090] Taking the anti-reflection layer 500 as a silicon oxynitride film as an example, FIG7 (a) is a TEM image of the anti-reflection layer without the previous dangling bond treatment, FIG7 (b) is an EDS (energy spectrum) analysis image of the Si element in FIG7 (a), FIG7 (c) is an EDS (energy spectrum) analysis image of the O element in FIG7 (a), and FIG7 (d) is an EDS (energy spectrum) analysis image of the N element in FIG7 (a). FIG8 (a) is a TEM image of the anti-reflection layer after the dangling bond removal treatment. FIG8 (b) is an EDS (energy spectrum) analysis image of the Si element in FIG8 (a), FIG8 (c) is an EDS (energy spectrum) analysis image of the O element in FIG8 (a), and FIG8 (d) is an EDS (energy spectrum) analysis image of the N element in FIG8 (a). It can be seen from FIG7 (a) to FIG7 (d) and FIG8 (a) to FIG8 (d) that the O element in the silicon oxynitride film is obviously increasing. There are a small amount of Si-NO dangling bonds in the silicon oxynitride film. After nitrous oxide is introduced into the anti-reflection layer 500, the O generated by the ionization of nitrous oxide is stronger than that of Si-N. - The ions can combine with the Si-O bonds in the silicon oxynitride film, thereby compensating for the dangling bonds in the silicon oxynitride film, enhancing the Si-O bond energy, and improving the stability of the silicon oxynitride film.
[0091] In one embodiment, forming a charge blocking layer on the exposed surfaces of the anti-reflection layer and the first dielectric layer includes the step of depositing silicon-rich oxide on the exposed surfaces of the anti-reflection layer and the first dielectric layer to form the charge blocking layer.
[0092] Exemplarily, a chemical vapor deposition process may be used to deposit silicon-rich oxide on the exposed surfaces of the anti-reflection layer 500 and the first dielectric layer 300 to form the charge blocking layer 700. The temperature condition for forming the charge blocking layer 700 by the chemical vapor deposition process is 350°C-400°C, for example, 350°C, 360°C, 370°C, 380°C, 390°C or 400°C. The pressure condition may be 1.2torr-4torr, for example, 1.2torr, 3 torr or 4 torr, etc. The power condition may be 200W-1200W, for example, 200W, 400W, 600W, 800W, 1000W or 1200W, etc. The reaction gas may be silane (SiH 4 ) and nitrous oxide (N 2O), wherein the flow rate of silane can be 60sccm-300sccm, for example, 60sccm, 120sccm, 180sccm, 240sccm or 300sccm, etc., and the flow rate of nitrous oxide can be 2000sccm-6000sccm, for example, 2000sccm, 3000sccm, 4000sccm, 5000sccm or 6000sccm, etc. The specific type and flow rate of the reaction gas, temperature conditions, pressure conditions and power conditions can be reasonably set according to actual business needs, and the embodiments of the present application are not limited here.
[0093] The redundant Si bonds in the silicon rich oxide (SRO) can combine with the plasma generated when the second dielectric layer 800 is subsequently formed on the charge blocking layer 700 using a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, thereby blocking the plasma charge and avoiding the accumulation of charges on the first dielectric layer 300 and the anti-reflection layer 500.
[0094] In some embodiments, the thickness of the charge blocking layer 700 may be 100 angstroms to 200 angstroms, such as 100 angstroms, 120 angstroms, 140 angstroms, 160 angstroms, 180 angstroms, or 200 angstroms.
[0095] In one embodiment, etching the second dielectric layer, the charge blocking layer and the substrate to form a through hole includes the steps of etching the second dielectric layer, the charge blocking layer and the anti-reflection layer to form a first through hole, and etching the second dielectric layer, the charge blocking layer, the anti-reflection layer, the second electrode layer and the first dielectric layer to form a second through hole.
[0096] Please continue to refer to Figure 4 , the first through hole 910 can be used to lead out the second electrode layer 400, and the second through hole 920 can be used to lead out the first electrode layer 200. Exemplarily, a photoresist layer can be deposited on the second dielectric layer 800 first, the photoresist layer can be patterned, and the second dielectric layer 800, the charge blocking layer 700 and the anti-reflection layer 500 can be etched based on the patterned photoresist layer to form the first through hole 910, and the second dielectric layer 800, the charge blocking layer 700, the anti-reflection layer 500, the second electrode layer 400 and the first dielectric layer 300 can be etched based on the patterned photoresist layer to form the second through hole 920. In this process, the anti-reflection layer 500 can absorb the light passing through the photoresist layer, reduce the reflected light, and reduce the influence of the standing wave effect.
[0097] In one embodiment, the method for preparing the capacitor structure of the present application further includes steps S700 - S800 .
[0098] S700, before forming the first electrode layer, depositing a first barrier layer material on the substrate to form a first barrier layer.
[0099] like Fig. 9 As shown, the first barrier layer material can be a titanium-containing compound, such as titanium (Ti), titanium nitride (TiN) or a combination thereof. The first barrier layer 1000 can prevent the material of the first electrode layer 200 from diffusing with the material of the substrate 100, thereby preventing the electromigration of the first electrode layer 200.
[0100] S800, before forming the first dielectric layer, depositing a second barrier layer material on the first electrode layer to form a second barrier layer.
[0101] Please continue reading Fig. 9 The second barrier layer material may be a titanium-containing compound, such as titanium (Ti), titanium nitride (TiN) or a combination thereof. The second barrier layer 1100 may prevent the material of the first electrode layer 200 from interdiffusion with the material of the first dielectric layer 300, thereby preventing electromigration of the first electrode layer 200. In addition, in the subsequent etching process to form a through hole, the second barrier layer 1100 may also serve as an etching barrier layer.
[0102] It should be understood that although Figure 1 The steps in the flowchart are shown in the order shown, but these steps are not necessarily executed in this order. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0103] Please continue reading Figure 4The present application also provides a capacitor structure, including a substrate 100, a first electrode layer 200, a first dielectric layer 300, a second electrode layer 400, an anti-reflection layer 500, a charge blocking layer 700, a second dielectric layer 800, a first through hole, and a second through hole. The first electrode layer 200 is located on the substrate 100, the first dielectric layer 300 is located on the first electrode layer 200, and the second electrode layer 400 is located on a portion of the first dielectric layer 300. The thickness of the portion of the first dielectric layer 300 covered by the second electrode layer 400 relative to the first electrode layer 200 is greater than the thickness of the second dielectric layer 800 not covered by the second electrode layer. The anti-reflection layer 500 is located on the second electrode layer 400. The charge blocking layer 700 is located on the exposed surfaces of the anti-reflection layer 500 and the first dielectric layer 300, and the second dielectric layer 800 is located on the charge blocking layer 700. The first through hole penetrates the second dielectric layer 800 , the charge blocking layer 700 and the anti-reflection layer 500 , and the second through hole penetrates the second dielectric layer 800 , the charge blocking layer 700 , the anti-reflection layer 500 , the second electrode layer 400 and the first dielectric layer 300 .
[0104] In the embodiment of the present application, during the formation of the capacitor structure, the anti-reflection layer 500 and the first dielectric layer 300 are subjected to a dangling bond removal process, so that the anti-reflection layer 500 and the first dielectric layer 300 have high stability. In addition, a charge blocking layer 700 is provided to block the plasma charge when the second dielectric layer 800 is formed, further reducing the charge accumulation on the surface of the anti-reflection layer 500 and the first dielectric layer 300, improving the stability of the anti-reflection layer 500 and the first dielectric layer 300, and improving the TDDB performance of the capacitor structure.
[0105] In one embodiment, Fig. 9 As shown, the capacitor structure further includes a first barrier layer 1000 and a second barrier layer 1100 .
[0106] The first barrier layer 1000 is located between the substrate 100 and the first electrode layer 200 , and can prevent the materials of the first electrode layer 200 and the substrate 100 from diffusing into each other, thereby preventing the first electrode layer 200 from electromigration.
[0107] The second barrier layer 1100 is located between the first electrode layer 200 and the first dielectric layer 300 to prevent the mutual diffusion of the materials of the first electrode layer 200 and the first dielectric layer 300 and prevent the electromigration of the first electrode layer 200. It can also serve as an etching barrier when forming the second through hole.
[0108] In one embodiment, the present application further provides a semiconductor structure, which includes a capacitor structure prepared by the capacitor structure preparation method provided by any of the above embodiments.
[0109] In one embodiment, the present application further provides a semiconductor structure, which includes the capacitor structure provided by any of the above embodiments.
[0110] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0111] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0112] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a capacitor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a first electrode layer, a first dielectric layer, a second electrode layer and an anti-reflection layer sequentially formed on the substrate; Etching the anti-reflection layer, the second electrode layer and a portion of the first dielectric layer to form a capacitor trench; Performing a dangling bond removal process on the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove; forming a charge blocking layer on the exposed surfaces of the anti-reflection layer and the first dielectric layer, wherein the charge blocking layer is used to combine with the plasma to achieve blocking of the plasma charges; Forming a second dielectric layer on the charge blocking layer by using a high-density plasma chemical vapor deposition process or a plasma enhanced chemical vapor deposition process; The second dielectric layer, the charge blocking layer and the substrate are etched to form a through hole.
2. The method according to claim 1, characterized in that Performing a dangling bond removal process on the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove, comprising: Under preset temperature conditions, preset pressure conditions, and preset power conditions, subjecting the exposed surface of the anti-reflection layer and the surface of the first dielectric layer exposed by the capacitor groove to nitrous oxide atmosphere treatment; Wherein, under the preset temperature condition, the preset pressure condition and the preset power condition, the nitrous oxide is ionized to generate oxygen ions, and the oxygen ions are combined with the dangling bonds.
3. The method according to claim 1, characterized in that Forming a charge blocking layer on the exposed surfaces of the anti-reflection layer and the first dielectric layer, comprising: Silicon-rich oxide is deposited on the exposed surfaces of the anti-reflection layer and the first dielectric layer to form the charge blocking layer.
4. The method according to claim 1, characterized in that: The etching of the second dielectric layer, the charge blocking layer and the substrate to form a through hole comprises: Etching the second dielectric layer, the charge blocking layer and the anti-reflection layer to form a first through hole; The second dielectric layer, the charge blocking layer, the anti-reflection layer, the second electrode layer and the first dielectric layer are etched to form a second through hole.
5. The method according to claim 1, characterized in that The method further comprises: Before forming the first electrode layer, depositing a first barrier layer material on the substrate to form a first barrier layer; Before forming the first dielectric layer, a second barrier layer material is deposited on the first electrode layer to form a second barrier layer.
6. The method according to claim 1, characterized in that The first dielectric layer includes silicon nitride, and the anti-reflection layer includes silicon oxynitride.
7. The method according to claim 1, characterized in that The charge blocking layer has a thickness of 100 angstroms to 200 angstroms.
8. A capacitor structure, characterized in that: include: substrate; A first electrode layer, located on the substrate; A first dielectric layer, located on the first electrode layer; a second electrode layer, located on a portion of the first dielectric layer; wherein a thickness of a portion of the first dielectric layer covered by the second electrode layer is greater than a thickness of a portion of the first dielectric layer not covered by the second electrode layer; an anti-reflection layer, located on the second electrode layer; A charge blocking layer, located on the exposed surfaces of the anti-reflection layer and the first dielectric layer; a second dielectric layer, located on the charge blocking layer; a first through hole, penetrating the second dielectric layer, the charge blocking layer and the anti-reflection layer; The second through hole penetrates the second dielectric layer, the charge blocking layer, the anti-reflection layer, the second electrode layer and the first dielectric layer.
9. The capacitor structure according to claim 8, characterized in that: The capacitor structure further includes: a first barrier layer, located between the substrate and the first electrode layer; The second barrier layer is located between the first electrode layer and the first dielectric layer.
10. A semiconductor structure, characterized in that: A capacitor structure comprising the method according to any one of claims 1 to 7, or a capacitor structure according to any one of claims 8 to 9.