Quantum bit leakage removal

Abstract

The invention provides a method, a system and a device for transmitting data quantum bit leakage. In one aspect, an apparatus includes, for a data qubit that has been operated by a quantum computing system to place the data qubit in a first state, where the first state encodes logical information: preparing, by the quantum computing system, a secondary qubit in a known initial state; and performing, by the quantum computing system, a leak transfer operation on the data qubit and the secondary qubit using one or more dual qubit gates to transfer leaks from the data qubit to the secondary qubit.

Description

Background Art

[0001] This specification relates to quantum computing.

[0002] Classical computers have a memory composed of bits, each of which can represent zero or one. Quantum computers maintain a sequence of quantum bits, called qubits, each of which can represent zero, one, or any quantum superposition of zero and one. Quantum computers operate by setting the qubits to an initial state and controlling the qubits, for example, according to a sequence of quantum computing operations, such as single-qubit gates, entanglement gates, and measurements. These quantum computing operations can cause qubits to fill non-computational levels, creating a need for protocols that can remove leakage populations from these non-computational levels without adversely affecting performance. Summary of the invention

[0003] This specification describes techniques for removing leakage from qubits.

[0004] Generally speaking, one innovative aspect of the subject matter described in this specification can be implemented in a method for transmitting leakage in a quantum computing system, the method comprising: for a data qubit that has been operated by a quantum computing system to place the data qubit in a first state, wherein the first state encodes logical information: preparing, by the quantum computing system, an auxiliary qubit in a known initial state; and performing, by the quantum computing system, a leakage transmission operation on the data qubit and the auxiliary qubit using one or more two-qubit gates to transfer the leakage from the data qubit to the auxiliary qubit.

[0005] Other implementations of this aspect include corresponding classical or quantum computer systems, devices, and computer programs recorded on one or more computer storage devices, each computer program being configured to perform the actions of these methods. A system of one or more computers may be configured to perform specific operations or actions by means of software, firmware, hardware, or a combination thereof installed on the system, which software, firmware, hardware, or a combination thereof causes the system to perform actions in operation. One or more computer programs may be configured to perform specific operations or actions by means of including instructions, which, when executed by a data processing device, cause the device to perform actions.

[0006] The foregoing and other implementations can each optionally include one or more of the following features, alone or in combination. In some implementations, the two-qubit gate includes a non-adiabatic CZ gate.

[0007] In some implementations, the data qubits include low-frequency qubits and the auxiliary qubits include high-frequency qubits.

[0008] In some implementations, the known initial state includes a state.

[0009] In some implementations, preparing an auxiliary qubit in a known initial state includes preparing an auxiliary qubit in a zero state; and applying a Pauli-X gate to the auxiliary qubit.

[0010] In some implementations, the one or more two-qubit gates include at least two two-qubit gates.

[0011] In some implementations, for each pair of consecutive two-qubit gates, applying at least two two-qubit gates includes: executing a first two-qubit gate included in the pair of two-qubit gates; and applying a second two-qubit gate included in the pair of two-qubit gates after a predetermined delay time has elapsed.

[0012] In some implementations, the predetermined delay time is calibrated using one or more tunable parameters to increase the likelihood of a successful leakage transmission.

[0013] In some implementations, the tunable parameters include one or more of a delay time between a data qubit and an auxiliary qubit, a CZ gate strength, or a detuning.

[0014] In some implementations, the method further includes performing, by the quantum computing system, a reset operation on the auxiliary quantum bit.

[0015] In some implementations, the method is performed i) in response to the quantum computing system completing a predetermined sequence of operations or ii) at regular intervals during quantum computing.

[0016] In some implementations, the predetermined sequence of operations includes a set of stable sub-measurements.

[0017] In general, another innovative aspect of the subject matter described in this specification can be implemented in a method for transmitting leakage from a first qubit to a second qubit, the method comprising: determining a frequency distance calibrated to implement a two-qubit gate; tuning an operating frequency of the first qubit by a quantum computing system; tuning the operating frequency of the second qubit by the quantum computing system to an operating frequency that is the determined frequency distance away from the operating frequency of the first qubit; determining a pulse that, when applied to a coupler that couples the first qubit to the second qubit, causes a predetermined rotation of the first qubit and the second qubit, wherein the predetermined rotation is half of the rotation required to implement a non-adiabatic CZ gate; and applying the pulse to the coupler by the quantum computing system.

[0018] Other implementations of this aspect include corresponding classical or quantum computer systems, devices, and computer programs recorded on one or more computer storage devices, each computer program being configured to perform the actions of these methods. A system of one or more computers may be configured to perform specific operations or actions by means of software, firmware, hardware, or a combination thereof installed on the system, which software, firmware, hardware, or a combination thereof causes the system to perform actions in operation. One or more computer programs may be configured to perform specific operations or actions by means of including instructions, which, when executed by a data processing device, cause the device to perform actions.

[0019] The foregoing and other implementations may each optionally include one or more of the following features, alone or in combination. In some implementations, before applying the pulse to the coupler, the first qubit is in a quantum state with an uncorrectable leakage population and the second qubit is in a zero state.

[0020] In some implementations, after applying the pulse to the coupler, the first qubit is in a quantum state with a correctable Pauli error and the second qubit is in a one state.

[0021] In some implementations, the method further includes correcting Pauli errors using quantum error correction.

[0022] In some implementations, the first qubit comprises a data qubit that encodes logical information, and the second qubit comprises an auxiliary qubit.

[0023] In some implementations, the first qubit comprises a high-frequency qubit and the second qubit comprises a low-frequency qubit.

[0024] In some implementations, the method is performed i) in response to the quantum computing system completing a predetermined sequence of operations or ii) at regular intervals during quantum computing.

[0025] In some implementations, the predetermined sequence of operations includes a round of quantum error correction operations.

[0026] In some implementations, the method also includes performing a reset operation on the second quantum bit.

[0027] The subject matter described in this specification can be implemented in a specific way to achieve one or more of the following advantages.

[0028] A system implementing any of the techniques described in this specification can remove leakage states on a data qubit without resetting the data qubit and without destroying the quantum information encoded in the state of the data qubit.

[0029] Therefore, the techniques described in the present invention are particularly suitable for fault-tolerant quantum computing devices that implement quantum error correction (QEC). In such QEC applications, the techniques described in the present invention can achieve a significant reduction in the steady-state leakage population P|2> (compared to the application of QEC that does not implement the techniques described in the present invention), for example, as little as 1 / 10 of the steady-state leakage population P|2>.

[0030] Furthermore, the techniques described herein can efficiently remove data qubit leakage, for example, achieving up to 95% |12> to |30> conversion rates (where |12> indicates |1> on the auxiliary / measurement qubit and |2> on the data qubit).

[0031] In addition, the techniques described herein can be implemented using existing hardware and control processes, such as hardware and control processes used to implement CZ gates. These techniques do not require additional hardware or architectural changes. However, these techniques can also be implemented using different types of hardware and control processes, such as those that may be available in the future. For example, these techniques are compatible with hardware with different device connectivity (the number of other qubits that each qubit can be coupled to), hardware with different types of coupling, or hardware using different types of qubits.

[0032] Furthermore, the techniques described in the present invention can be implemented with a relatively small time cost, which is important because the target computation state suffers from errors as the gate time increases.

[0033] Furthermore, the techniques described in the present invention do not require additional hardware logic. Some alternative conventional methods require fast hardware to perform feed forward after a leaky state is detected. This requirement adds more complexity on top of the existing problems. Using the techniques described in the present invention avoids these requirements and the additional complexity.

[0034] The details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 An example system 100 for data qubit leakage removal is depicted.

[0036] Figure 2A is a circuit diagram showing a first example leaky pump gate.

[0037] Figure 2B is a circuit diagram showing a second example leaky pump gate.

[0038] Figure 3Ais a circuit diagram showing the ideal operation of a first example leakage pumping gate in the absence of data qubit leakage.

[0039] Figure 3B is a circuit diagram illustrating the ideal action of a first example leakage pumping gate in the presence of data qubit leakage.

[0040] Figure 3C is a circuit diagram showing the ideal action of a second example leakage pumping gate in the presence of data qubit leakage.

[0041] Figure 4 is a flow chart of an example process for removing data qubit leakage using a leakage pump gate.

[0042] Figure 5 is a graph showing the data qubit 2-state population with varying CZ-CZ delay times.

[0043] Figure 6 A graph of the data qubit leakage population at each step of a quantum error correction process without a leaky pump gate and a graph of the data qubit leakage population at each step of a quantum error correction process with a leaky pump gate are shown.

[0044] Fig. 7A is a circuit diagram of example operations performed on data qubits and measurement qubits during a round of quantum error correction.

[0045] Figure 7B is a circuit diagram of example operations performed on data qubits and measurement qubits during a round of quantum error correction including the leaky i SWAP gate described in the present invention.

[0046] Figure 7C is a circuit diagram of example operations performed on data qubits and measurement qubits during a round of quantum error correction including the leaky i SWAP gate and measurement qubit reset described in the present invention.

[0047] Figure 8 is a flow chart of an example process for leaking from a first qubit to a second qubit using a leaky i SWAP gate

[0048] Fig. 9 Two diagrams showing example frequency traces of a data qubit, a measurement qubit, and a coupler are shown.

[0049] Fig. 10A is a flow chart of an example process for calibrating a leaky i SWAP gate.

[0050] Fig. 10B is a graph showing data qubit leakage population for varying coupling strength and qubit resonance.

[0051] Fig.11 Two graphs comparing quantum error correction errors during different numbers of quantum error correction rounds are shown.

[0052] Fig.12 A graph showing the data qubit leakage population at each step of the quantum error correction process with the leaky i SWAP gate described in the present invention is shown.

[0053] Fig.13 Depicted are example systems for performing the classical and quantum computations described herein. DETAILED DESCRIPTION

[0054] In quantum computing, operations are usually performed on qubits in the computational basis, such as between zero excitation and single excitation manifolds. However, since physical qubits are not perfect two-level systems and there are higher energy levels corresponding to additional excitations, there is a possibility of leaving the computational basis and entering those higher states. This process is called leakage. Leakage can introduce errors into quantum computing. Specifically, leakage is troublesome for quantum error correction because it can cause correlated errors, breaking the basic assumptions of error correction.

[0055] Existing techniques remove leakage by resetting qubits, which, however, also results in the destruction of the quantum information encoded in the basis of computation. These techniques can improve quantum error correction performance because they can be applied to measurement qubits, which encode only temporary information in each round and can be reset. However, this is incompatible with data qubits in quantum error correction, which must remain encoded at all times.

[0056] This specification describes two methods for solving this problem. Each method selectively exchanges the leakage state on the data qubit into the corresponding auxiliary qubit, while keeping the computational basis of the data qubit undisturbed. Once this is achieved, the auxiliary qubit can be reset, removing the unwanted excitation from the system. The leakage in the data qubit then manifests as an error in the computational basis, which can be easily corrected by an error correction protocol.

[0057] The first method exploits leakage transport, which is intrinsic to the two-qubit entanglement gates used to perform quantum computations. Leakage transport converts a leakage state |2> on a data qubit into a higher leakage state |3> on the corresponding ancillary qubit, which can then be reset. The effect of the two-qubit gate on the computational basis of the data qubit is deterministic and can be reversed if desired. The leakage transport process is efficient, resulting in up to 95% |2> to |3> conversion rates.

[0058] The second approach is based on a new quantum gate, referred to herein as the leaky-i SWAP gate. The leaky-i SWAP gate is based on a modification of the two-qubit gate and is implemented so as to achieve a unidirectional conversion of the leakage state |2> on the data qubit to the |1> state on the corresponding auxiliary qubit. Implementation of this gate results in a very high |2> to |1> conversion rate of over 99%. In addition, resetting |1> on the auxiliary qubit can be done much easier than higher leakage states such as |3>, making this protocol particularly attractive.

[0059] Example operating environment

[0060] Figure 1 An example system 100 for data qubit leakage removal is depicted. Example system 100 is an example of a system implemented as part of a quantum computing device in which the systems, components, and techniques described herein may be implemented.

[0061] System 100 includes a two-qubit subsystem 102 in communication with control electronics 104. Two-qubit subsystem 102 includes a first qubit 106 coupled to a second qubit 108. In some implementations, first qubit 106 may be a data qubit. A data qubit is a qubit that participates in a quantum computation performed by system 100 and stores quantum information corresponding to the quantum computation. That is, the state of the data qubit encodes logical information for the quantum computation. In some implementations, second qubit 108 is an auxiliary qubit (also referred to herein as a measurement qubit). A measurement qubit is a qubit used to determine the result of a computation performed by a data qubit. For example, during a computation, an unknown state of a data qubit may be entangled with the state of a measurement qubit using a suitable physical operation, after which the measurement qubit may be measured.

[0062] First qubit 106 and second qubit 108 may each be in a respective quantum state occupying one or more levels. These levels include: two computational levels, such as level 0 and level 1; and one or more non-computational levels, each of which is higher in energy (or equivalently, higher in frequency) than a computational qubit level, such as level 2 and level 3. The population of higher non-computational qubit levels may introduce errors in algorithmic operations or quantum computations performed using the qubits. For example, the occupation of qubit levels outside of the computational subspace may hinder or prevent the implementation of quantum error correction operations.

[0063] The first qubit 106 may be coupled to the second qubit 108 via a coupler. The coupler may in principle be any type of coupler, such as a capacitive or inductive coupler. The coupler that couples the first qubit 106 to the second qubit 108 may be controllable. For example, the strength of the coupler may be frequency controllable.

[0064] In some implementations, first qubit 106 and second qubit 108 may be superconducting qubits or semiconductor qubits. For example, first qubit 106 and second qubit 108 may be part of a linear chain of capacitively coupled Xmon qubits included in a quantum computing device. However, in other cases, these qubits may include flux qubits, phase qubits, or qubits with frequency interactions. In general, a qubit may be any physical system with multiple energy levels, including two levels of computational subspaces and at least one level of non-computational subspace.

[0065] First qubit 106 and second qubit 108 may be manipulated by adjusting qubit frequencies, for example, by applying pulses to the qubits generated by control electronics 104. In the case where first qubit 106 and second qubit 108 are Xmon qubits, the qubit frequencies may be placed at a predetermined distance from each other and in a zigzag position relative to other qubits that may be included in the quantum computing device.

[0066] Control electronics 104 includes control devices, such as arbitrary waveform generators, that can operate first qubit 106 and second qubit 108. For example, control electronics 104 may include control devices that tune the operating frequencies of first qubit 106 and second qubit 108 by applying control signals (e.g., voltage pulses) to the qubits through corresponding control lines. Control electronics 104 may also include control devices that tune the frequency of a coupler that couples first qubit 106 to second qubit 108.

[0067] System 100 can program control electronics 104 to selectively transfer leakage from first qubit 106 to second qubit 108 while leaving the computational basis of first qubit 106 undisturbed. For example, system 100 can program control electronics 104 to apply leakage pump gate 110 to first qubit 106 and second qubit 108. Figure 6 1 and 2. For another example, system 100 may program control electronics 104 to apply leakage i SWAP gate 112 to first qubit 106 and second qubit 108. Fig.12An example leaky i SWAP gate is described in more detail.

[0068] Hardware programming: Leak pump via leak transmission

[0069] Figure 2A 2 is a circuit diagram showing a first example leakage pump gate 200. Auxiliary qubit 202 is prepared in an initial state, such as a 0 state. Data qubit 204 is in a certain quantum state encoding logical information. Ideally, data qubit 204 is in a quantum state of superposition of computational states 0 and 1, i.e., a quantum state in the computational basis. However, in some implementations, data qubit 204 may be in a quantum state that has leaked into a non-computational state, such as 2, 3, etc.

[0070] Leakage pump gate 206 is applied to auxiliary qubit 202 and data qubit 204. Application of leakage pump gate 206 transfers leakage from data qubit 204 to auxiliary qubit 202. Leakage pump gate 206 can be decomposed into Figure 2A The sequence of quantum gates shown on the right hand side. That is, the leakage pump gate 206 includes a Pauli-X gate 208 applied to the auxiliary quantum bit 202 and a CZ gate applied to the auxiliary quantum bit 202 and the data quantum bit 204. In some implementations, the CZ gate can be a non-adiabatic CZ gate. Non-adiabatic CZ gates can be used because they use interactions with higher states, and these interactions can be used to execute the protocols described in the present invention. Adiabatic gates are designed not to interact with or fill higher states, although they can do so due to non-idealities or competitive performance considerations. The effects of the CZ gates on the quantum states in the computational basis are symmetrical and are given in the following table:

[0071]

[0072]

[0073] However, the effect of the CZ gate on the leakage states is asymmetric, and one qubit (e.g., the higher frequency qubit) receives leakage from the other qubit:

[0074] Input |a>|b> Output |a>|b> |1>|2> |3>|0> |2>|2> |3>|1>

[0075] Therefore, the application of Pauli-X gate 208 and CZ gate 210 transfers the leakage from data qubit 204 to auxiliary qubit 202, such as Figure 3A and Figure 3B After the leakage has been transferred, a reset operation 212 may be performed on the auxiliary qubit 202 to remove the transferred leakage and place the auxiliary qubit in the 0 state.

[0076] In some implementations, a Z gate may be applied to qubit 204 after applying CZ gate 210. Applying the Z gate to qubit 204 acts as a correction and ensures that the computational state of qubit 204 remains unchanged.

[0077] Figure 2B 2 is a circuit diagram showing a second example leakage pump gate 250. Auxiliary qubit 252 is prepared in an initial state, such as a 0 state. Data qubit 254 is in a certain quantum state encoding logical information. Ideally, data qubit 254 is in a quantum state of superposition of computational states 0 and 1, i.e., a quantum state in the computational basis. However, in some implementations, data qubit 254 may be in a quantum state that has leaked into a non-computational state, such as 2, 3, etc.

[0078] A leakage pump gate 256 is applied to the auxiliary qubit 252 and the data qubit 254. The application of the leakage pump gate 256 transfers the leakage from the data qubit 254 to the auxiliary qubit 252. The leakage pump gate 256 can be decomposed into Figure 2B The sequence of quantum gates shown on the right hand side. That is, the leakage pump gate 256 includes the Pauli-X gate 208 applied to the auxiliary qubit 252 and the plurality of CZ gates 260, 262 applied to the auxiliary qubit 252 and the data qubit 254. In some implementations, the plurality of CZ gates 260, 262 may be non-adiabatic CZ gates. The application of the Pauli-X gate 258 and the CZ gates 260, 262 transfers the leakage from the data qubit 254 to the auxiliary qubit 252, as Figure 3C shown.

[0079] The second CZ gate 262 is not applied immediately after the first CZ gate 260 is applied. Instead, the application of the first CZ gate 260 and the second CZ gate 262 are separated by a CZ-CZ delay time 264. The delay time can achieve constructive interference between the transmissions of the first CZ gate and the second CZ gate, thereby enhancing the overall leakage transmission. The delay time 264 can be calibrated to optimize the action of the leakage pump gate 256, for example, to increase the percentage of leakage that is successfully pumped from the data qubit state to the auxiliary qubit, as described below with reference to Figure 5 described.

[0080] In some implementations, alternatives to adjusting the delay time between CZ gates can be implemented. For example, one (or both) qubit frequencies can be offset in a controlled manner to induce a phase shift. This strategy can produce an equally efficient leakage pumping action.

[0081] After the leakage has been transferred, a reset operation 266 may be performed on the auxiliary qubit 252 to remove the transferred leakage and place the auxiliary qubit in a 0 state. In some implementations, the second example leakage pump gate 250 may be more efficient than the first example leakage pump gate 200, e.g., the second example leakage pump gate 250 may successfully pump a higher percentage of leakage from the data qubit state to the auxiliary qubit than the first example leakage pump gate 200. This is because the slight shift in the qubit frequency allows for tuning of the constructive interference between the two gates. However, the second example leakage pump gate 250 requires more quantum gates to be implemented and a longer execution time, which increases the computational cost associated with executing the second example leakage pump gate 250. Therefore, in some implementations, it may be more advantageous to implement the first example leakage pump gate 200. In this example, it is not necessary to apply a Z gate to the data qubit because the application of multiple CZ gates may more accurately transfer the leakage, making correction unnecessary.

[0082] Figure 3A is a circuit diagram 300 showing the ideal operation of a first example leakage pump gate in the absence of data qubit leakage. Figure 2A As described, the auxiliary qubit is prepared to be in the 0 state, while the data qubit is in the quantum state 302 in the computational basis, i.e., a quantum state without leakage. After applying the Pauli-X gate to the auxiliary qubit, the auxiliary qubit is in the 1 state. After applying the CZ gate to the auxiliary qubit and the data qubit, the auxiliary qubit remains in the 1 state, and the quantum state of the data qubit remains in the computational basis. After applying the reset operation to the auxiliary qubit, the auxiliary qubit returns to the 0 state. In some implementations, a Z gate may be applied to the data qubit after applying the CZ gate. Applying the Z gate to the data qubit plays a corrective role and can ensure that the computational state of the data qubit remains unchanged.

[0083] Figure 3B 320 is a circuit diagram showing the ideal action of the first example leakage pump gate in the presence of data qubit leakage. In this example, the auxiliary qubit is prepared in the 0 state, and the data qubit is in a quantum state 322, which has leaked out of the computational basis to become a 2 state, i.e., a quantum state with leakage. After the Pauli-X gate is applied to the auxiliary qubit, the auxiliary qubit is in the 1 state. After the CZ gate is applied to the auxiliary qubit and the data qubit, the leakage is transmitted from the data qubit to the auxiliary qubit, so that the auxiliary qubit is in the 3 state. The data qubit is then in the 0 state. After applying a reset operation to the auxiliary qubit, the auxiliary qubit returns to the 0 state. In some implementations, a Z gate may be applied to the data qubit after the CZ gate is applied. Applying the Z gate to the data qubit acts as a correction and can ensure that the computational state of the data qubit remains unchanged.

[0084] Figure 3C 340 is a circuit diagram showing the ideal action of a second example leakage pump gate in the presence of data qubit leakage. In this example, the auxiliary qubit is prepared in the 0 state, and the data qubit is in a quantum state 342, which has leaked out of the computational basis to become a 2 state, i.e., a quantum state with leakage. After applying the Pauli-X gate to the auxiliary qubit, the auxiliary qubit is in the 1 state. After applying multiple CZ gates to the auxiliary qubit and the data qubit, the leakage is transmitted from the data qubit to the auxiliary qubit, so that the auxiliary qubit is in the 3 state. The data qubit is then in the 0 state. After applying a reset operation to the auxiliary qubit, the auxiliary qubit returns to the 0 state. In this example, it is not necessary to apply a Z gate to the data qubit because the application of multiple CZ gates can more accurately transmit the leakage, so that no correction is required.

[0085] Figure 4 is a flow chart of an example process 400 for removing data qubit leakage using a leakage pump gate. For convenience, process 400 will be described as being performed by quantum hardware in communication with control electronics located at one or more locations. For example, a properly programmed according to the present specification Figure 1 The quantum computing system 100 may perform process 400 .

[0086] For a data qubit that has been operated by the quantum computing system to place the data qubit in a first state, wherein the first state encodes logical information, the system prepares an auxiliary qubit in a known initial state (step 402). For example, the system may initialize the auxiliary qubit to a 0 state, such as by performing a reset operation, and apply a Pauli-X gate to the auxiliary qubit to place the auxiliary qubit in a 1 state.

[0087] The system performs a leakage transfer operation on the data qubit and the auxiliary qubit using one or more two-qubit gates to transfer leakage from the data qubit to the auxiliary qubit (step 404). In some implementations, the one or more two-qubit gates are CZ gates. The CZ gate can be a non-adiabatic CZ gate. In implementations where the system applies multiple two-qubit gates (e.g., two or more), the system may apply a two-qubit gate with a predetermined delay time between each consecutive two-qubit gate. For example, for each pair of consecutive two-qubit gates, the system may execute a first two-qubit gate included in the pair, and after reaching a predetermined delay time, apply a second two-qubit gate included in the pair.

[0088] The delay time may be pre-calibrated using one or more tunable parameters to increase the likelihood of successful leakage transmission. For example, for each of a plurality of calibration experiments with a fixed number of two-qubit gates, the system may perform steps 402 and 404 for corresponding values ​​of one or more tunable parameters and measure the data qubits to obtain a measurement result representing the remaining data qubit 2 population. The system may then use the measurement result to identify the value of one or more tunable parameters that produces the best leakage removal (e.g., achieving the lowest remaining 2 population). Example tunable parameters include the delay time between the data qubit and the auxiliary qubit, the CZ gate strength, or the detuning.

[0089] Figure 5 5 is a graph 500 showing the data qubit 2-state population with varying CZ-CZ delay times. Graph 500 shows that a delay time of about 4.4 ns between CZ gates produces optimal leakage removal, e.g., up to 95% leakage removal. Other parameters may be used instead of or in addition to the delay time. For example, in an implementation where the operating frequency of the data qubit and the auxiliary qubit can be adjusted, the system may vary the detuning of one of these qubits between applications of a two-qubit gate, e.g., with a fixed delay time, to identify the detuning frequency that produces the best leakage removal.

[0090] Back to Figure 4 In some implementations, after the leakage has been transferred from the data qubit to the auxiliary qubit, the system can perform a reset operation on the auxiliary qubit to remove the transferred leakage (step 406).

[0091] In some implementations, the example process 600 can be performed when the system completes a predetermined sequence of operations during quantum computation (e.g., a sequence of operations that puts an auxiliary qubit into a known state). For example, in quantum error correction, the example process 600 can be performed when the system completes a set of stabilizer measurements, because after a set of stabilizer measurements, the auxiliary qubit (measurement qubit) is measured and reset, which puts the auxiliary qubit into a known initial state, as described above at step 402. In other implementations, the example process can be performed at regular time intervals during quantum computation.

[0092] Figure 6Two graphs of data qubit leakage population at each step of the quantum error correction process are shown. Graph 600 shows the data qubit leakage population at each step of the quantum error correction process without the leakage pump gate described in the present invention. The x-axis represents the steps or moments of the quantum error correction process. These steps are shown above graph 600 and include: applying a Hadamard gate 602 to an auxiliary qubit, applying a Pauli-Z gate 604 to an auxiliary qubit, applying two CZ gates 606, 608 to an auxiliary qubit and a data qubit, applying a Hadamard gate 610 to an auxiliary qubit, applying a Pauli-X gate 612 to a data qubit, measuring 614 an auxiliary qubit, and resetting 616 an auxiliary qubit. As shown, during the quantum error correction process, the data qubit leakage population is stable and remains between about 0.0025 and 0.0035. The auxiliary qubit leakage population increases slowly and steadily until the auxiliary qubit is reset.

[0093] Graph 650 shows the data qubit leakage population at each step of the quantum error correction process with the leakage pump gate described in the present invention. The x-axis represents the step or time of the quantum error correction process. These steps are shown above graph 650 and are the same as those shown in graph 600, except that after the reset operation 616 is applied to the auxiliary qubit, the leakage pump gate 652 is also applied to the data qubit and the auxiliary qubit. As shown, during the quantum error correction process, the data qubit leakage population is also stable and remains between about 0.0095 and 0.002 - about 1 / 2 of that shown in graph 600.

[0094] Hardware programming: Leaky reset via leaky i SWAP gate

[0095] Another method for removing leakage from data qubits is based on a new quantum gate that selectively converts a leakage state (e.g., a 20 state) into a correctable quantum state (e.g., an 11 state) (where 20 represents a 2 state on the data qubit and a 0 state on the auxiliary / measurement qubit). This gate is referred to herein as a leakage i SWAP gate and is described below. The leakage i SWAP gate is particularly suitable for implementation during a round of quantum error correction and is primarily described in this setting, however, this is a non-limiting example and the leakage i SWAP gate can be applied to other settings, for example, any setting that facilitates selectively exchanging a leakage state from one qubit to another qubit.

[0096] Fig. 7A700 is a circuit diagram of example operations performed on data qubits and measurement qubits during a round of quantum error correction. A parity check operation 706 is performed on data qubits 702 and measurement qubits 704 to diagnose correctable errors in the state of the data qubits. After the parity check operation 706, the data qubits are idle 708, and the state of the measurement qubit is read out 710 to obtain the result of the parity check operation 706. The measurement qubit is then reset 712.

[0097] After the quantum error correction operation, the measurement qubit 704 is in the 0 state, and the data qubit 702 is in the quantum state corresponding to the quantum computation performed by the quantum computer. Ideally, the quantum state will be the surface code state 714 in the computation basis. However, in some cases, the quantum state may include some leakage population, such as leakage 716. Leakage 716 may occur during quantum computation or during a round of error correction.

[0098] Figure 7B 720 is a circuit diagram of example operations performed on data qubits and measurement qubits during a round of quantum error correction including a leaky i SWAP gate as described herein. Fig. 7A As described above, a parity check operation 706 is performed on the data qubit 702 and the measurement qubit 704 to diagnose correctable errors in the state of the data qubit. After the parity check operation 706, the data qubit is idle 708, and the state of the measurement qubit is read out 710 to obtain the result of the parity check operation 706. Then, the measurement qubit is reset 712.

[0099] A leaky i SWAP gate 722 of the present invention is applied to the data qubit 702 and the measurement qubit 704. The application of the leaky i SWAP gate 722 removes the leaky population 716 of the data qubit 702 by selectively transferring the leaky population 716 to the measurement qubit 704. Therefore, after the quantum error correction operations 706, 708, 710, 712, and 722, the measurement qubit 704 is in the 1 state, and the data qubit 702 is in a quantum state including the surface code state 714 and the correctable Pauli error 724. That is, the application of the leaky i SWAP gate 722 rotates the |20> state to |11> without affecting the surface code state 714. Unlike the leaky population |2>, the remaining correctable Pauli error 724∈|1> can be effectively corrected by quantum error correction.

[0100] Figure 7C 730 is a circuit diagram of example operations performed on data qubits and measurement qubits during a round of quantum error correction including the leaky i SWAP gate and measurement qubit reset described in the present invention. Figure 7BAs described, a parity check operation 706 is performed on the data qubit 702 and the measurement qubit 704 to diagnose correctable errors in the state of the data qubit. After the parity check operation 706, the data qubit is idle 708, and the state of the measurement qubit is read out 710 to obtain the result of the parity check operation 706. Then, the measurement qubit is reset 712, and a leakage i SWAP gate 722 is applied to the data qubit 702 and the measurement qubit 704. A second reset operation 726 is applied to the measurement qubit 704 to place the measurement qubit in the 0 state.

[0101] After quantum error correction operations 706, 708, 710, 712 have been performed, the data qubit includes a 2-state leakage population, and the measurement qubit is in the 0 state. After the leakage i SWAP gate 722 has been performed, the data qubit includes a 1-state Pauli error, and the measurement qubit is in the 1 state. After the second reset operation 726, the data qubit includes a 1-state Pauli error, and the measurement qubit is in the 0 state.

[0102] Figure 8 is a flow chart of an example process 800 for leaking from a first qubit to a second qubit using a leaky i SWAP gate. In the example process 800, the first qubit may be a data qubit encoding logical information, and the second qubit may be an auxiliary qubit (measurement qubit). For convenience, process 800 will be described as being performed by quantum hardware in communication with control electronics located at one or more locations. For example, a device appropriately programmed according to the present specification Figure 1 The quantum computing system 100 may perform process 800 .

[0103] The system determines the frequency distance calibrated to implement the two-qubit gate (step 802). Fig. 9 As shown, in some implementations, the frequency distance may represent a frequency distance between an operating frequency of a first qubit and an operating frequency of a second qubit, wherein the operating frequency of the first qubit is set relative to the interaction frequency, and the operating frequency of the second qubit is set relative to the operating frequency of the first qubit. In some implementations, the system may retrieve data representing the frequency distance from a database storing recent calibration values ​​of frequency distances, pulse intensities, etc. In other implementations, the system may perform multiple experiments to determine the calibrated frequency distance, as described below with reference to Fig. 10A and Fig. 10B Describe in more detail.

[0104] The system tunes an operating frequency of the first qubit and an operating frequency of the second qubit to operating frequencies that are a determined frequency distance from the operating frequency of the first qubit (step 804).

[0105] The system determines a pulse that, when applied to a coupler that couples the first qubit with the second qubit, causes a rotation of the first qubit and the second qubit (step 806). This rotation is half of the rotation required to implement a non-adiabatic CZ gate. Application of a pulse calibrated for a CZ gate causes the two-qubit 11 state to rotate to the 20 state and then back to the 11 state (with a conditional phase). Therefore, the pulse determined by the system at step 806 can be considered to be half of the pulse required to implement a CZ gate because the two-qubit 11 state then rotates to the 20 state (and does not rotate back to the 11 state). The determined pulse is similar to the pulse required to perform a CZ gate, but is defined by different parameter values. An example pulse shape is shown in Fig. 9 In terms of parameters (and for frequency tunable couplers), a pulse can be defined as a pulse that moves the qubits to the appropriate frequency distance from each other and then drops the frequency of the coupler towards the qubits in a trapezoidal pulse shape. The main parameters may include the length and depth of this trapezoidal pulse - they tune the amount and strength of the interaction respectively. These parameters can be adjusted to effectively transmit leakage.

[0106] In some implementations, the system may primarily use CZ gates as dual qubits for performing quantum computations, and therefore already have hardware and routines for performing CZ gates. The same hardware and routines (with different parameter values) may be used to determine and apply pulses for data qubit leakage removal, which may reduce the hardware complexity and control complexity required to perform data qubit leakage removal.

[0107] In some implementations, the system may retrieve data representing the pulse from a database storing the most recently calibrated values ​​of frequency distance, pulse strength, etc. In other implementations, the system may perform multiple experiments to calibrate the pulse, as described below with reference to Fig. 10A and Fig. 10B Describe in more detail

[0108] The system applies a pulse to the coupler (step 808). Prior to applying the pulse to the coupler, the first qubit may be in a quantum state with an uncorrectable leakage population, and the second qubit may be in a zero state. The application of the pulse causes the selective transfer of the leakage population from the data qubit to the measurement qubit, as described above with reference to Figure 7B and Figure 7C Thus, after applying the pulse to the coupler, the first qubit is in a quantum state with a correctable Pauli error and the second qubit is in a state.

[0109] In some implementations, the system can use quantum error correction to correct the Pauli error.Alternatively or in addition, the system can perform a reset operation on the second qubit.

[0110] In some implementations, the example process 800 can be performed when the system completes a predetermined sequence of operations during quantum computing, such as when the system completes a round of quantum error correction operations. In other implementations, the example process can be performed at regular time intervals during quantum computing.

[0111] Fig. 9 Two diagrams are shown of example frequency trajectories of a data qubit, a measurement qubit, and a coupler during an example process 800. In the first diagram 900, the data qubit is a higher frequency qubit (compared to the measurement qubit). The operating frequencies of the data qubit and the measurement qubit are tuned such that the operating frequencies are separated by a predetermined distance 902 (approximately the interaction frequency f int ). For example, the operating frequency of the data qubit may first be tuned relative to the interaction frequency, and then the operating frequency of the measurement qubit may be tuned relative to the operating frequency of the data qubit to separate the operating frequencies of the data qubit and the measurement qubit by the correct distance.

[0112] The coupler is pulsed 904 to cause the data qubit and the measurement qubit to interact. The pulses are calibrated to cause a rotation of the data qubit and the measurement qubit that is half of the rotation required to implement a non-adiabatic CZ gate.

[0113] In the second illustration 906, the data qubit is a lower frequency qubit (compared to the measurement qubit). As in graph 900, the operating frequencies of the data qubit and the measurement qubit are tuned so that the operating frequencies are separated by a predetermined distance 902 (approximately the interaction frequency f int ). Because the data qubit is a lower frequency qubit in this illustration, tuning the operating frequency of the measurement qubit relative to the data qubit causes the frequency of the measurement qubit to cross over with the frequency of the data qubit. Therefore, in some implementations, it may be more advantageous to set the data qubit as a higher interaction qubit.

[0114] The coupler is pulsed 904 to cause the data qubit and the measurement qubit to interact. The pulses are calibrated to cause a rotation of the data qubit and the measurement qubit that is half of the rotation required to implement a non-adiabatic CZ gate.

[0115] Fig. 10A is a flow chart of an example process 1000 for calibrating a leaky i SWAP gate. For convenience, process 1000 will be described as being performed by quantum hardware in communication with control electronics located at one or more locations. For example, a properly programmed according to the present specification Figure 1 The system 100 may perform the process 1000 .

[0116] The system performs a plurality of data qubit leakage removal operations (step 1002). Each data qubit leakage removal operation may be performed using the example process 1000 described above, wherein each data qubit leakage removal operation corresponds to a distance between a data qubit operating frequency and a measurement qubit operating frequency and a corresponding value of a qubit coupling strength. Fig. 10B 1008 is a graph showing data qubit leakage population for varying coupling strengths and qubit resonances. The x-axis represents the tunable resonance condition, which can be adjusted to change the frequency distance between the operating frequency of the data qubit and the measurement qubit. The y-axis represents the coupling strength between the data qubit and the measurement qubit. Each pixel in the graph shows the data qubit leakage population for implementing a leaky i SWAP gate using corresponding values ​​of coupling strength and qubit resonance. In this example, the lowest data qubit leakage population is represented by the darker shaded area, such as area 1010.

[0117] return Fig. 10A , the system identifies an optimal value of coupling strength and an optimal value of frequency distance based on the data qubit leakage population corresponding to the data qubit leakage removal operation (step 1004). For example, the system identifies the coupling strength value and frequency distance that produce the lowest data qubit leakage population. Fig. 10B The lowest data qubit leakage population is produced by a coupling strength of about -16 MHz and a frequency distance of about 0.8 volts. Fig. 10B In , the "dacamp offset" is the offset from the natural frequency distance, which is assumed to be separated by a nonlinearity (e.g., about 270MHz in this example). The frequency distance can be fine-tuned by adjusting the dacamp offset, which allows the gate to be adjusted on a single MHz level.

[0118] The system stores the optimal value of the coupling strength and the optimal value of the frequency distance in a suitable database as calibration values ​​for implementing the leaky i SWAP gate (step 1006).

[0119] Fig.11Two graphs 1100, 1102 comparing quantum error correction errors during different numbers of quantum error correction rounds are shown. Graph 1100 shows quantum error correction errors during different numbers of quantum error correction rounds without the leaky i SWAP gate described in the present invention. The y-axis of graph 1100 represents the detection fraction, i.e., the proportion of stable sub-measurements indicating errors. The x-axis of graph 1100 represents each round of quantum error correction. Different lines represent corresponding measurement qubits in the error correction code, and the marks (hollow / solid, circle / square) represent the responsibilities of each measurement qubit, for example, a square indicates that the measurement qubit has 4 data qubit neighbors, a circle indicates 2 data qubit neighbors, a hollow mark indicates a measurement Z error, and a solid mark indicates a measurement X error. An increase in the detection fraction of each line (which increases rapidly between 0 and 10 rounds, and then stabilizes or gradually increases between 10 and 30 rounds) indicates leakage.

[0120] Graph 1102 shows the case where the leakage i SWAP and reset gate described in the present invention are provided (eg, Figure 7C 1100 ). Similarly, the y-axis of graph 1102 represents the detection fraction, and the x-axis of graph 1102 represents each round of quantum error correction. Graph 1102 shows that implementing the leaky i SWAP gate of the present invention prevents the slow increase in the detection fraction shown in graph 1100. In addition, the amount of detection fraction is low and remains stable after the first round of error correction, indicating that quantum error correction is not disturbed by the addition of the leaky i SWAP gate.

[0121] Fig.12 A graph 1200 is shown of the data qubit leakage population at each step of a quantum error correction process with a leaky i SWAP gate as described herein. The x-axis represents the steps or moments of the quantum error correction process. The steps are shown at the top of the graph 1200 and include: applying a parity operation 1202 to the data qubit and the ancillary qubit, measuring 1204 the ancillary qubit, resetting 1206 the ancillary qubit, and applying a leaky i SWAP gate 1208 to the data qubit and the ancillary qubit. Fig.12 In the figure, the data corresponding to the dashed lines replace the leakage removal instant with the equivalent waiting time of qubit inactivity. These dashed lines are included to improve the ease of analysis / comparison.

[0122] As shown, the techniques described in the present invention achieve a substantial reduction in the steady-state P|2> at the beginning of a QEC round. The reduction at the beginning of a QEC round is of particular interest because the presence of leakage is arguably most destructive at the beginning of a QEC round, when many CZs are executed. Each CZ has the potential to transmit and enhance leakage between the two qubits it acts on. By starting with low leakage at the beginning of a round, the potential for this undesirable leakage to grow is minimized.

[0123] Fig.13 An example system 1300 for performing classical and quantum computations described herein is depicted. Example system 1300 is an example of a system implemented as classical and quantum computer programs on one or more classical computers and quantum computing devices in one or more locations in which the systems, components, and techniques described herein may be implemented.

[0124] Example system 1300 includes example quantum computing device 1302. According to some implementations, quantum computing device 1302 can be used to perform quantum computing operations described in this specification. Quantum computing device 1302 is intended to represent various forms of quantum computing devices. The components shown here, their connections and relationships, and their functions are only exemplary and do not limit the implementation of the present invention described and / or claimed in this document.

[0125] Example quantum computing device 1302 includes qubit assembly 1352 and control and measurement system 1304. The qubit assembly includes a plurality of qubits, such as qubit 1306, which are used to perform algorithmic operations or quantum computations. Fig.13 The qubits are shown arranged in a rectangular array, but this is a schematic depiction and is not intended to be limiting. Qubit assembly 1352 also includes a plurality of adjustable coupling elements, such as couplers 1308, which allow interaction between coupled qubits. Fig.13 In the schematic depiction of , each qubit is adjustably coupled to each of its four neighboring qubits through a corresponding coupling element. However, this is an example arrangement of qubits and couplers, and other arrangements are possible, including non-rectangular arrangements, arrangements that allow coupling between non-adjacent qubits, and arrangements that include adjustable coupling between more than two qubits.

[0126] Each qubit can be a physical two-level quantum system or device with a level representing logical values ​​0 and 1. The specific physical implementation of multiple qubits and how they interact with each other depends on various factors, including the type of quantum computing device included in the example system 1300, or the type of quantum computing being performed by the quantum computing device. For example, in an atomic quantum computer, a qubit can be implemented via an atom, a molecule, or a solid-state quantum system (e.g., a hyperfine atomic state). As another example, in a superconducting quantum computer, a qubit can be implemented via a superconducting qubit or a semiconductor qubit (e.g., a superconducting transporter (t ransmon) state). As another example, in an NMR quantum computer, a qubit can be implemented via a nuclear spin state.

[0127] In some implementations, quantum computations may be performed by initializing qubits in a selected initial state and applying a sequence of unitary operators to the qubits. Applying unitary operators to quantum states may include applying a corresponding sequence of quantum logic gates to the qubits. Example quantum logic gates include single-qubit gates such as Pauli-X, Pauli-Y, Pauli-Z (also referred to as X, Y, Z), Hadamard gates, S gates, rotations; two-qubit gates such as controlled X gates, controlled Y gates, controlled Z gates (also referred to as CX, CY, CZ), controlled NOT gates (also referred to as CNOT), controlled exchange gates (also referred to as CSWAP); and gates involving three or more qubits such as Toffol i gates. Quantum logic gates may be implemented by applying control signals 1310 generated by the control and measurement system 1304 to the qubits and couplers.

[0128] For example, in some implementations, the qubits in qubit assembly 1352 may be frequency tunable. In these examples, each qubit may have an associated operating frequency that can be adjusted by applying a voltage pulse via one or more drive lines coupled to the qubit. Example operating frequencies include qubit idle frequency, qubit hold frequency, qubit interaction frequency, and qubit readout frequency. Different frequencies correspond to different operations that can be performed by qubits. For example, setting the operating frequency to the corresponding idle frequency can place the qubit in a state in which it does not strongly interact with other qubits and can be used to perform a single qubit gate. For example, in the case where qubits interact via a coupler with a fixed coupling, the qubits may be configured to interact with each other by setting their respective operating frequencies to a certain gate-related frequency that is detuned from their common interaction frequency. In other cases, for example, when qubits interact via a tunable coupler, the qubits may be configured to interact with each other by setting the parameters of their respective couplers to enable interaction between qubits and then by setting the corresponding operating frequencies of the qubits to a certain gate-related frequency that is detuned from their common interaction frequency. Such interactions can be performed in order to execute multi-qubit gates.

[0129] The type of control signal 1310 used depends on the physical implementation of the qubit. For example, the control signal may include RF or microwave pulses in NMR or superconducting quantum computer systems, or light pulses in atomic quantum computer systems.

[0130] Quantum computations can be accomplished by measuring the state of a qubit (e.g., using a quantum observable, such as X or Z) using a corresponding control signal 1310. The measurement causes a readout signal 1312 representing the measurement result to be transmitted back to the measurement and control system 1304. The readout signal 1312 may include an RF, microwave, or optical signal, depending on the physical scheme of the quantum computing device and / or qubit. For convenience, Fig.13 The control signals 1310 and readout signals 1312 shown are depicted as addressing only selected elements of the qubit component (ie, the top and bottom rows), but during operation, the control signals 1310 and readout signals 1312 may address every element in the qubit component 1352.

[0131] Control and measurement system 1304 is an example of a classical computer system that can be used to perform various operations on qubit assembly 1352 described above, as well as other classical subroutines or computations. Control and measurement system 1304 includes one or more classical processors (e.g., classical processor 1314), one or more memories (e.g., memory 1216), and one or more I / O units (e.g., I / O unit 1318) connected via one or more data buses. Control and measurement system 1304 can be programmed to transmit a sequence of control signals 1310 to a qubit assembly, for example, to perform a series of selected quantum gate operations, and to receive a sequence of readout signals 1312 from a qubit assembly, for example, as part of performing a measurement operation.

[0132] The processor 1314 is configured to process instructions for execution within the control and measurement system 1304. In some implementations, the processor 1314 is a single-threaded processor. In other implementations, the processor 1314 is a multi-threaded processor. The processor 1314 is capable of processing instructions stored in the memory 1316.

[0133] The memory 1316 stores information within the control and measurement system 1304. In some implementations, the memory 1316 includes a computer-readable medium, a volatile memory unit, and / or a non-volatile memory unit. In some cases, the memory 1316 may include a storage device capable of providing mass storage for the system 1304, such as a hard disk device, an optical disk device, a storage device shared by multiple computing devices on a network (e.g., a cloud storage device), and / or some other mass storage device.

[0134] Input / output devices 1318 provide input / output operations for control and measurement system 1304. Input / output devices 1318 may include D / A converters, A / D converters, and RF / microwave / optical signal generators, transmitters, and receivers, thereby transmitting control signals 1310 to and receiving readout signals 1312 from qubit components, as appropriate for the physical scheme of a quantum computer. In some implementations, input / output devices 1318 may also include one or more network interface devices (e.g., Ethernet cards), serial communication devices (e.g., RS-232 ports), and / or wireless interface devices (e.g., 802.11 cards). In some implementations, input / output devices 1318 may include driver devices configured to receive input data and transmit output data to other external devices (e.g., keyboards, printers, and display devices).

[0135] Although the example control and measurement system 1304 has been shown Fig.13However, the subject matter and implementation of the functional operations described in this specification may be implemented in other types of digital electronic circuits or in computer software, firmware or hardware, including the structures disclosed in this specification and their structural equivalents or a combination of one or more of them.

[0136] The example system 1300 includes an example classical processor 1350. The classical processor 1350 can be used to perform the classical computing operations described in this specification according to some implementations (e.g., the classical machine learning methods described herein).

[0137] The digital and / or quantum subject matter and implementation of digital functional operations and quantum operations described in this specification can be implemented in digital electronic circuits, suitable quantum circuits, or more generally in quantum computing systems, in tangibly embodied digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of them. The term "quantum computing system" may include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0138] The implementation of the digital and / or quantum subject matter described in this specification may be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions for execution by a data processing device or for controlling the operation of the data processing device, encoded on a tangible non-transitory storage medium. The digital and / or quantum computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, one or more quantum bits, or a combination of one or more of them. Alternatively or in addition, the program instructions may be encoded on an artificially generated propagation signal capable of encoding digital and / or quantum information, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode digital and / or quantum information for transmission to a suitable receiver device for execution by the data processing device.

[0139] The terms quantum information and quantum data refer to information or data carried, stored or stored by a quantum system, wherein the smallest non-trivial system is a quantum bit, i.e., a system that defines a unit of quantum information. It should be understood that the term "quantum bit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems may include multi-level systems, e.g., having two or more energy levels. For example, such systems may include atoms, electrons, photons, ions, or superconducting quantum bits. In many implementations, the computational basis states are identified by the ground state and the first excited state, however it should be understood that other arrangements in which the computational states are identified by higher-order excited states are possible.

[0140] The term "data processing device" refers to digital and / or quantum data processing hardware, and covers all types of devices, equipment and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers, and combinations thereof. The device may also be or also include a dedicated logic circuit, such as an FPGA (field programmable gate array), an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing device designed to simulate or generate information about a specific quantum system. Specifically, a quantum simulator is a dedicated quantum computer that does not have the ability to perform general quantum computations. In addition to the hardware, the device may optionally include code that creates an execution environment for a digital and / or quantum computer program, for example, code that constitutes a processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0141] A digital computer program, which may also be referred to or described as a program, software, software application, module, software module, script or code, may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a digital computing environment. A quantum computer program, which may also be referred to or described as a program, software, software application, module, software module, script or code, may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and translated into a suitable quantum programming language, or may be written in a quantum programming language (e.g., QCL or Quipper).

[0142] A digital and / or quantum computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that stores other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordination files (e.g., files storing one or more modules, subroutines, or code portions). A digital and / or quantum computer program may be deployed to be executed on a digital computer or a quantum computer or on multiple digital and / or quantum computers, which are located at a site or distributed on multiple sites and interconnected by a digital and / or quantum data communication network. A quantum data communication network is understood to be a network that can send quantum data using a quantum system (e.g., a qubit). Generally speaking, a digital data communication network cannot send quantum data, however, a quantum data communication network can send both quantum data and digital data.

[0143] The processes and logic flows described in this specification may be performed by one or more programmable digital and / or quantum computers operating in conjunction with one or more digital and / or quantum processors, where appropriate, executing one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows may also be performed by dedicated logic circuits, and the apparatus may also be implemented as dedicated logic circuits, such as FPGAs or ASICs or quantum simulators, or by a combination of dedicated logic circuits or quantum simulators and one or more programmed digital and / or quantum computers.

[0144] For a system of one or more digital and / or quantum computers to be "configured to" perform specific operations or actions, it is meant that the system has installed thereon software, firmware, hardware, or a combination thereof that, in operation, causes the system to perform those operations or actions. For one or more digital and / or quantum computer programs to be configured to perform specific operations or actions, it is meant that the one or more programs include instructions that, when executed by a digital and / or quantum data processing device, cause the device to perform those operations or actions. A quantum computer may receive instructions from a digital computer that, when executed by a quantum computing device, cause the device to perform an operation or action.

[0145] A digital and / or quantum computer suitable for executing a digital and / or quantum computer program may be based on a general or special purpose digital and / or quantum processor or both, or any other type of central digital and / or quantum processing unit. In general, the central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read-only memory, a random access memory, or a quantum system suitable for sending quantum data (e.g. photons), or a combination thereof.

[0146] The basic elements of a digital and / or quantum computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory may be supplemented by or incorporated into a dedicated logic circuit or quantum simulator. Generally speaking, a digital and / or quantum computer will also include one or more large-capacity storage devices for storing digital and / or quantum data, or be operably coupled to receive digital and / or quantum data from the large-capacity storage device or transmit digital and / or quantum data to the large-capacity storage device, such as a magnetic disk, a magneto-optical disk, an optical disk, or a quantum system suitable for storing quantum information. However, a digital and / or quantum computer need not have such a device.

[0147] Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks; and quantum systems, such as trapped atoms or electrons. It should be understood that quantum memory is a device that can store quantum data for a long time and with high fidelity and efficiency, such as a light-matter interface, where light is used for transmission and matter is used to store and preserve quantum features of quantum data, such as superposition or quantum coherence.

[0148] The control of the various systems or parts thereof described in this specification may be implemented in a digital and / or quantum computer program product, which includes instructions stored on one or more non-transitory machine-readable storage media and can be executed on one or more digital and / or quantum processing devices. The systems or parts thereof described in this specification may each be implemented as an apparatus, method or system that may include one or more digital and / or quantum processing devices and a memory storing executable instructions for performing the operations described in this specification.

[0149] Although this specification contains many implementation details, these details should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular implementation. Certain features described in this specification in the context of separate implementations may also be implemented in a single implementation in combination. Conversely, individual features described in the context of a single implementation may also be implemented in multiple implementations, either individually or in any suitable subcombination. In addition, although features are described above as acting in certain combinations and even initially claimed, one or more features from a claimed combination may be separated from the combination in some cases, and a claimed combination may be directed to a subcombination or a change in a subcombination.

[0150] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired result. In some contexts, multitasking and parallel processing can be advantageous. In addition, the separation of various system modules and components in the implementation described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products.

[0151] Specific implementations of the subject matter have been described. Other implementations are within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or ordered sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method for transmitting leakage in a quantum computing system, comprising: For a data qubit that has been operated by a quantum computing system to place the data qubit in a first state, wherein the first state encodes logical information: Preparing an auxiliary quantum bit in a known initial state by the quantum computing system; as well as A leakage transfer operation is performed on the data qubit and the auxiliary qubit by the quantum computing system using one or more two-qubit gates to transfer leakage from the data qubit to the auxiliary qubit.

2. The method of claim 1, wherein the two-qubit gate comprises a non-adiabatic CZ gate.

3. The method of claim 1 or claim 2, wherein the data qubits comprise low-frequency qubits and the auxiliary qubits comprise high-frequency qubits.

4. The method of any one of claims 1 to 3, wherein the known initial state comprises a state.

5. The method of claim 4, wherein preparing the auxiliary qubit in the known initial state comprises: preparing the auxiliary qubit in a zero state; as well as A Pauli-X gate is applied to the auxiliary qubit.

6. The method of any one of claims 1 to 5, wherein the one or more two-qubit gates comprises at least two two-qubit gates.

7. The method of claim 6, wherein for each pair of consecutive two-qubit gates, applying the at least two two-qubit gates comprises: executing a first two-qubit gate included in the pair of two-qubit gates; as well as After a predetermined delay time is reached, a second two-qubit gate included in the pair of two-qubit gates is applied.

8. The method of claim 7, wherein the predetermined delay time is calibrated using one or more tunable parameters to increase the likelihood of a successful leakage transmission.

9. The method of claim 8, wherein the tunable parameters include one or more of a delay time, a CZ gate strength, or a detuning between the data qubit and the ancillary qubit.

10. The method of any one of claims 1 to 9, further comprising performing a reset operation on the auxiliary qubit by the quantum computing system.

11. A method as claimed in any one of claims 1 to 10, wherein the method is i) in response to the quantum computing system completing a predetermined sequence of operations or ii) performed at regular intervals during quantum computing.

12. The method of claim 11, wherein the predetermined sequence of operations comprises a set of stable sub-measurements.

13. An apparatus comprising: One or more classical processors; as well as quantum computing hardware in data communication with the one or more classical processors, The apparatus is configured to perform the method according to any one of claims 1 to 12.

14. A method for transferring leakage from a first qubit to a second qubit, comprising: Determine the frequency distance calibrated to implement a two-qubit gate; Tuning the operating frequency of the first quantum bit by a quantum computing system; tuning, by the quantum computing system, an operating frequency of the second quantum bit to an operating frequency that is a determined frequency distance away from the operating frequency of the first quantum bit; determining a pulse that, when applied to a coupler coupling the first qubit with the second qubit, causes a predetermined rotation of the first qubit and the second qubit, wherein the predetermined rotation is half of a rotation required to implement a non-adiabatic CZ gate; and The pulse is applied to the coupler by the quantum computing system.

15. The method of claim 14, wherein prior to applying the pulse to the coupler, the first qubit is in a quantum state with an uncorrectable leakage population and the second qubit is in a zero state.

16. The method of claim 15, wherein after applying the pulse to the coupler, the first qubit is in a quantum state having a correctable Pauli error and the second qubit is in a one state.

17. The method of claim 16, further comprising correcting the Pauli error using quantum error correction.

18. The method of any one of claims 14 to 17, wherein the first qubit comprises a data qubit encoding logical information and the second qubit comprises an auxiliary qubit.

19. The method of any one of claims 14 to 18, wherein the first qubit comprises a high-frequency qubit and the second qubit comprises a low-frequency qubit.

20. A method as claimed in any one of claims 14 to 19, wherein the method is performed i) in response to the quantum computing system completing a predetermined sequence of operations or ii) at regular intervals during quantum computing.

21. The method of claim 20, wherein the predetermined sequence of operations comprises a round of quantum error correction operations.

22. The method of any one of claims 14 to 21, further comprising performing a reset operation on the second qubit.

23. An apparatus comprising: One or more classical processors; as well as quantum computing hardware in data communication with the one or more classical processors, The apparatus is configured to perform the method as claimed in any one of claims 14 to 22.

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