Semiconductor device

Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a base die having a first power supply circuit generating a first voltage, a first die having a second power supply circuit generating a second voltage by being supplied with the first voltage, and a second die having a functional circuit operating by being supplied with the second voltage. The first die and the second die include a first through electrode and a second through electrode. The first die is disposed on the base die. The second die is provided so as to be in contact with an upper layer or a lower layer of the first die. The base die and the first die are electrically connected through a first through electrode. The first die and the second die are electrically connected through the second through electrode.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and the like.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, more specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, driving methods of these devices or manufacturing methods of these devices can be cited. Background Art

[0003] In recent years, research and development on a structure in which a plurality of bare chips (eg, silicon bare chips) including circuits having different functions such as SRAM cells and DRAM cells are three-dimensionally stacked has been actively conducted (eg, Non-Patent Documents 1 and 2).

[0004] The stacked dies use technologies such as TSV (Through Silicon Via) that use through-electrodes or Cu-Cu (copper-copper) direct bonding technologies to reduce wiring load, thereby achieving low power consumption and high speed (low latency). In a semiconductor device formed by stacking dies with different functional circuits, clock signal management and power management in the Z direction (the direction in which the dies are stacked) are very important. [Prior technical literature] [Non-patent literature]

[0005] [Non-patent document 1] W. Gomes et al., ISSCCDig. Tech. Papers, pp. 42-43, 2022. [Non-patent document 2] M. Parketal., ISSCCDig.Tech.Papers, pp.444-445, 2022. Summary of the invention Technical problem to be solved by the invention

[0006] When a power circuit is provided on a base die (a die in which a plurality of dies are provided in a stacked manner), the voltage drop has a significant effect in a structure in which the power voltage is supplied to an upper die that is farther from the base die. Therefore, there is a concern that the voltage supplied by the power circuit cannot be kept uniform in power management in the Z direction.

[0007] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which a plurality of dies are stacked three-dimensionally on a base die, and the uniformity of the voltage supplied to the functional circuits of the plurality of dies is excellent. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which a plurality of dies are stacked three-dimensionally on a base die, and low power consumption in a power supply circuit is achieved. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which a plurality of dies are stacked three-dimensionally on a base die, and the influence of heat generation in a power supply circuit can be reduced. Another purpose of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

[0008] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purposes do not prevent the existence of other purposes. Other purposes refer to purposes other than those mentioned above to be described in the following description. Those skilled in the art can derive and appropriately extract purposes not mentioned above from the description of the specification or drawings, etc. Note that one embodiment of the present invention achieves at least one of the above-mentioned purposes and / or other purposes. Solutions to technical problems

[0009] One embodiment of the present invention is a semiconductor device, comprising: a base die having a first power supply circuit for generating a first voltage; a first die having a second power supply circuit for generating a second voltage by being supplied with the first voltage; and a second die having a functional circuit that operates by being supplied with the second voltage, wherein the first die and the second die include a first through electrode and a second through electrode, the first die is disposed on the base die, the second die is disposed in contact with an upper layer or a lower layer of the first die, the base die is electrically connected to the first die via the first through electrode, and the first die is electrically connected to the second die via the second through electrode.

[0010] In the semiconductor device according to one embodiment of the present invention, preferably, the first power supply circuit is a switching regulator.

[0011] In the semiconductor device according to one embodiment of the present invention, preferably, the second power supply circuit is a series regulator.

[0012] In the semiconductor device of one embodiment of the present invention, the functional circuit is preferably a circuit having one or more functions of a calculation circuit, a peripheral circuit, a storage circuit, and a driver circuit.

[0013] The semiconductor device according to one embodiment of the present invention preferably includes a heat dissipation layer provided between the first die and the second die.

[0014] In the semiconductor device according to one embodiment of the present invention, preferably, the first through-electrode and the second through-electrode provided on different bare chips are electrically connected via a metal bump.

[0015] In the semiconductor device according to one embodiment of the present invention, preferably, the second bare chip includes a layer including a transistor including an oxide semiconductor in a channel formation region, and the layer including the transistor is provided in a stacked manner.

[0016] In the semiconductor device according to one embodiment of the present invention, the oxide semiconductor preferably includes In, Ga, and Zn.

[0017] One embodiment of the present invention is a semiconductor device, comprising: a base die having a first power supply circuit for generating a first voltage; a first die having a second power supply circuit for generating a second voltage by being supplied with the first voltage; and a second die and a third die having a functional circuit that operates by being supplied with the second voltage, wherein the first die, the second die, and the third die include through electrodes, the first die is arranged on the base die, the second die is arranged in contact with a lower layer of the first die, the third die is arranged in contact with an upper layer of the first die, the base die is electrically connected to the first die through the first through electrode, and the first die, the second die, and the third die are electrically connected through the second through electrode.

[0018] In the semiconductor device according to one embodiment of the present invention, preferably, the first power supply circuit is a switching regulator.

[0019] In the semiconductor device according to one embodiment of the present invention, preferably, the second power supply circuit is a series regulator.

[0020] In the semiconductor device according to one embodiment of the present invention, the functional circuit is preferably a circuit having one or more functions of a calculation circuit, a peripheral circuit, a storage circuit, and a driver circuit.

[0021] A semiconductor device according to one embodiment of the present invention includes a heat dissipation layer provided between the first die and the second die and between the first die and the third die.

[0022] In the semiconductor device according to one embodiment of the present invention, preferably, the first through-electrode and the second through-electrode provided on different bare chips are electrically connected via a metal bump.

[0023] In the semiconductor device according to one embodiment of the present invention, preferably, the second bare chip and the third bare chip include a layer including a transistor including an oxide semiconductor in a channel formation region, and the layer including the transistor is provided in a stacked manner.

[0024] In the semiconductor device according to one embodiment of the present invention, the oxide semiconductor preferably includes In, Ga, and Zn.

[0025] Note that other aspects of the present invention are described in the description and drawings of the embodiment modes described below. Effects of the Invention

[0026] One embodiment of the present invention can provide a semiconductor device with a novel structure in which a plurality of bare chips are stacked three-dimensionally on a base bare chip, and the uniformity of the voltage supplied to the functional circuits of the plurality of bare chips is excellent. In addition, one embodiment of the present invention can provide a semiconductor device with a novel structure in which a plurality of bare chips are stacked three-dimensionally on a base bare chip, and low power consumption in a power supply circuit can be achieved. In addition, one embodiment of the present invention can provide a semiconductor device with a novel structure in which a plurality of bare chips are stacked three-dimensionally on a base bare chip, and the influence of heat generation in a power supply circuit can be reduced. In addition, one embodiment of the present invention can provide a semiconductor device with a novel structure.

[0027] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1A , Figure 1B A diagram illustrating a structural example of a semiconductor device. Figure 2A , Figure 2B A diagram illustrating a structural example of a semiconductor device. Figure 3A and Figure 3B A diagram illustrating a structural example of a semiconductor device. Figure 4A and Figure 4B A diagram illustrating a structural example of a semiconductor device. Figure 5A , Figure 5B A diagram illustrating a structural example of a semiconductor device. Fig. 6A and Figure 6B A diagram illustrating a structural example of a semiconductor device. Fig. 7A , Figure 7B , Figure 7C A diagram illustrating a structural example of a semiconductor device. Fig. 8A and Figure 8B A diagram illustrating a structural example of a semiconductor device. 9A to 9D A diagram illustrating a structural example of a semiconductor device. Fig.10 A diagram illustrating a structural example of a semiconductor device. FIG. 11A to FIG. 11C A diagram illustrating a structural example of a semiconductor device. Fig.12 It is a diagram for explaining a configuration example of a storage unit. Fig.13A It is a diagram for explaining a structural example of a storage layer. Fig. 13B is a diagram illustrating an equivalent circuit of a storage layer. Fig.14 It is a diagram for explaining a configuration example of a storage unit. Fig.15A It is a diagram for explaining a structural example of a storage layer. Fig. 15B is a diagram illustrating an equivalent circuit of a storage layer. Fig.16A and Fig. 16B This is a diagram showing an example of an electronic component. Fig.17A and Fig. 17B is a diagram showing an example of an electronic device, FIG. 17C to FIG. 17E This is a diagram showing an example of a large computer. Fig.18 is a diagram showing an example of space equipment. Fig.19 This is a diagram showing an example of a storage system that can be used in a data center. Modes for Carrying Out the Invention

[0029] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0030] In addition, in the accompanying drawings, for the convenience of clear description, the size, thickness of the layer or the area are sometimes exaggerated. Therefore, the present invention is not necessarily limited to the above-mentioned dimensions. In addition, the accompanying drawings schematically show ideal examples, so the present invention is not limited to the shapes or numerical values ​​shown in the accompanying drawings.

[0031] In addition, in this specification, unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also called the non-conducting state or the blocking state). In an n-channel transistor, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage Vth (In a p-channel transistor, V gs Higher than V th ) status.

[0032] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor may refer to a transistor containing a metal oxide or an oxide semiconductor.

[0033] (Implementation Method 1) In this embodiment, a configuration example of a semiconductor device is described. The semiconductor device described in one embodiment of the present invention is used as a SoC (System on a Chip) having a plurality of functional circuits such as a memory circuit and a peripheral circuit in addition to a logic circuit.

[0034] Figure 1A FIG1 is a block diagram for explaining a semiconductor device according to one embodiment of the present invention. FIG1 is a schematic diagram for explaining a semiconductor device according to one embodiment of the present invention.

[0035] Figure 1A The semiconductor device 10 shown includes a power supply circuit 21 , a power supply circuit 31 , and a plurality of functional circuits 32 . Figure 1A The semiconductor device 10 shown in the figure includes a power circuit 21 , a power circuit 31 and a plurality of functional circuits 32 disposed on a stacked die. Figure 1B A schematic diagram showing a die (hereinafter referred to as a basic die 20 ) on which a plurality of die (taking 30_1 to 30_3 as an example) are arranged is shown. Figure 1B The Z direction in φ represents a direction perpendicular to the surface of the base die 20 or a direction in which the dies 30_1 to 30_3 are arranged in a manner of being stacked on the base die 20 .

[0036] exist Figure 1B In the structure of the present invention, the die stacked on the base die 20 are represented as 30_1 to 30_3. For example, the die of the nth layer can be represented as die 30_n as a die stacked on the base die 20. Note that in this embodiment and the like, when describing matters related to the entire n-layer die composed of the die 30_1 to 30_n or matters common to each layer of the die 30, sometimes it is simply described as "die 30".

[0037] The power supply circuit 21 is a circuit that generates a constant voltage Vin and a reference voltage Vref based on a reference voltage V_BASE. The power supply circuit 21 is disposed on the base die 20. For example, the power supply circuit 21 is preferably a switching regulator. The switching regulator can efficiently generate a constant voltage Vin and a reference voltage Vref based on the reference voltage V_BASE. The switching regulator requires larger electronic components such as inductors and capacitors. Compared with the die 30_1 to 30_3, the base die 20 has a larger area, so larger electronic components such as external inductors and diodes can be configured. Note that the constant voltage Vin and the reference voltage Vref are sometimes referred to as the first voltage. In addition, the power supply circuit 21 is sometimes referred to as the first power supply circuit.

[0038] Note that the base die 20 provided with the power supply circuit 21 may include functional circuits such as a clock generation circuit, arithmetic circuits such as a CPU core, and a memory circuit in addition to the power supply circuit 21 .

[0039] The power supply circuit 31 is a circuit that generates a constant voltage Vout based on a constant voltage Vin and a reference voltage Vref. In order to generate a plurality of different constant voltages Vout, a plurality of power supply circuits 31 may be provided. The power supply circuit 31 is preferably a series regulator such as a low dropout regulator (LDORegulator). The series regulator may be composed of an amplifier circuit and a transistor for output voltage control, so the series regulator may be applied to the power supply circuits of the dies 30_1 to 30_3 stacked on the base die 20 without using electronic components such as inductors and diodes. Note that the constant voltage Vout is sometimes referred to as the second voltage. In addition, the power supply circuit 31 is sometimes referred to as the second power supply circuit. In addition, the die 30_2 provided with the power supply circuit 31 is sometimes referred to as the first die.

[0040] In a structure in which a plurality of dies (e.g., 30_1 to 30_3) are three-dimensionally stacked on a base die 20, by providing a die 30_2 having a power circuit 31, a constant voltage Vout can be supplied from the power circuit 31 possessed by the die 30_2 which is farther from the base die 20 to the functional circuit 32 possessed by the dies 30_1 and 30_3 which are adjacent to the die 30_2. Therefore, it is possible to reduce the influence of a voltage drop of the voltage supplied to the functional circuit 32. Therefore, in power management in the Z direction, it is possible to easily ensure the uniformity of the voltage supplied by the power circuit.

[0041] The base die 20 and the die 30_1 to 30_3 include transistors (Si transistors) whose semiconductor layers have channel formation regions and contain silicon. By including Si transistors, a structure in which a power circuit and a functional circuit are formed using a CMOS circuit (Si CMOS circuit) can be realized. By adopting this structure, the power circuit and the functional circuit of the Si CMOS circuit can be arranged in each layer. Since the power circuit and the functional circuit can be formed by a CMOS circuit, high-speed operation can be performed.

[0042] In addition, the semiconductor layer including the channel formation region of the Si transistor can use one or a combination of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor material is not limited to silicon, for example, germanium can also be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide or nitride semiconductors can also be used.

[0043] Note that the base die 20 and the die 30_1 to 30_3 including Si transistors can realize stacked element layers by connecting the substrates using a through electrode technology such as TSV (Through Silicon Via) or a Cu-Cu (copper-copper) direct bonding technology (a technology that connects Cu (copper) pads to each other to make them electrically conductive). Note that the connection between the die including the through electrode can be made by a metal bump (sometimes called a micro bump).

[0044] The constant voltage Vin and the reference voltage Vref are supplied from the power circuit 21 of the base die 20 to the power circuit 31 of the die 30_2 through the through-electrode 41A provided in the plurality of dies (e.g., 30_1 to 30_3) on the base die 20. In addition, the constant voltage Vout is supplied from the power circuit 31 of the die 30 to the functional circuit 32 of the dies 30_1 and 30_3 through the through-electrode 41B provided in the plurality of dies (e.g., 30_1 to 30_3) on the base die 20. By adopting the above structure, the power circuit 31 supplying the constant voltage Vout and the functional circuit 32 supplied with the constant voltage Vout can be provided close to each other while supplying the constant voltage Vin and the reference voltage Vref to the die far from the base die.

[0045] The functional circuit 32 is a circuit that works by being supplied with a constant voltage Vout. The functional circuit 32 is preferably a circuit having one or more functions of an operation circuit, a peripheral circuit, a storage circuit, and a drive circuit. By adopting a structure in which synchronous circuits such as an operation circuit, a peripheral circuit, a storage circuit, and a drive circuit are provided on the bare chips 30_1 to 30_3 stacked on the base bare chip 20, a plurality of synchronous circuits can be arranged closely and the timing of the clock signal can be easily adjusted, so the power consumption required for distributing the clock signal can be reduced. In addition, since a plurality of functional circuits can be arranged per unit area, the high functionality of the semiconductor device can be achieved. In addition, the bare chip 30_1 or the bare chip 30_3 provided with the functional circuit 32 is sometimes referred to as the first bare chip.

[0046] The bare chips 30_1 and 30_3 including the functional circuit 32 supplied with the constant voltage Vout are preferably provided in contact with the upper or lower layer of the bare chip 30_2 including the power circuit 31. With this structure, the functional circuit 32 supplied with the constant voltage Vout can be arranged at a uniform distance from the power circuit 31.

[0047] In addition, the arithmetic circuit is a functional circuit such as a CPU or GPU having arithmetic functions. In addition, the storage circuit is a storage circuit including Si transistors such as DRAM or SRAM, or a storage circuit including a transistor (OS transistor) whose semiconductor layer having a channel formation region includes an oxide semiconductor such as DOSRAM or NOSRAM to be described later. In addition, the drive circuit is a circuit used to drive other circuits such as the storage circuit. In addition, the peripheral circuit is a circuit such as LAN (Local Area Network), USB (Universal Serial Bus), PCI (Peripheral Component Interconnect), etc. that can perform processing at a lower speed than the arithmetic circuit. In addition, circuits such as interfaces and bridge circuits can be used as functional circuits.

[0048] As described above, the semiconductor device 10 of one embodiment of the present invention includes a base die 20 having a power circuit 21 that generates a constant voltage Vin and a reference voltage Vref, a die 30_2 having a power circuit 31 that generates a constant voltage Vout by being supplied with the constant voltage Vin and the reference voltage Vref, and die 30_1 and 30_3 having a functional circuit 32 that operates by being supplied with the constant voltage Vout. The die 30_1 to 30_3 include through electrodes 41A and 41B. The die 30_2 is provided on the base die, and the die 30_1 and 30_3 are provided in a manner of contacting the upper layer or the lower layer of the die 30_2. The base die 20 and the die 30_2 are electrically connected through the through electrode 41A. The die 30_2 is electrically connected to the die 30_1 and 30_3 through the through electrode 41B.

[0049] In a semiconductor device of one embodiment of the present invention, in a structure in which a plurality of bare chips are three-dimensionally stacked on a base bare chip, the uniformity of the voltage supplied by the power supply circuit can be easily ensured in the power supply management in the Z direction. In addition, the power supply circuit can be provided close to the functional circuit while the voltage required to generate the constant voltage is supplied to the bare chip far from the base bare chip. In addition, the plurality of functional circuits 32 can be arranged at a uniform distance from the power supply circuit 31, so that a semiconductor device having excellent uniformity of the voltage supplied to each functional circuit 32 can be realized.

[0050] Notice, Figure 1B Although the structure in which the functional circuit 32 is provided in the upper and lower dies 30_1 and 30_3 of the die 30_2 including the power supply circuit 31 is shown, the functional circuit 32 may be provided in any one of the upper and lower dies 30_1 and 30_3 of the die 30_2. Figure 2A As in the semiconductor device 10A shown in the figure, a structure in which the functional circuit 32 is not provided in the bare chip 30_1 may be adopted.

[0051] Notice, Figure 1B The structure in which the electrical connection of the functional circuit 32 provided in the upper and lower dies 30_1 and 30_3 of the die 30_2 including the power supply circuit 31 is performed through the through electrode 41B is shown, but other structures may be adopted. Figure 2B As shown in the semiconductor device 10B, a structure can be adopted in which the functional circuit 32 and the power circuit 31 included in the upper die 30_3 are connected through the through electrode 41B, and the functional circuit 32 and the power circuit 31 included in the lower die 30_1 are connected through the through electrode 41C. Figure 2B As shown, a structure in which the power supply circuit 31 included in the bare chip 30_2 is provided for each functional circuit 32 may be adopted.

[0052] in addition, Figure 2B The structure is excellent in improving the accuracy of the voltage supplied to the functional circuit 32. FIG. 3A to FIG. 4B An example of the structure of the power supply circuit 31 and the advantage of arranging the power supply circuit 31 near the functional circuit 32 will be described.

[0053] Figure 3A is a diagram showing a circuit structure of a low-dropout regulator that can be used for the power supply circuit 31. As described above, in a structure in which a plurality of bare chips are stacked three-dimensionally on a base bare chip, the power supply circuit 31 includes an amplifier circuit 33 and a transistor 34 that is a p-channel Si transistor. The transistor 34 is a transistor for output voltage control. The voltage Vin and the reference voltage Vref are supplied from the power supply circuit 21 included in the base bare chip 20, and a constant voltage Vout is supplied. The voltage of the wiring that supplies the constant voltage Vout is fed back to the amplifier circuit 33. The amplifier circuit 33 can control the gate voltage of the transistor 34 according to the fed-back voltage and supply the desired constant voltage Vout. Note that in Figure 3A The constant voltage Vout fed back to the amplifier circuit 33 is input as a voltage divided from the GND potential.

[0054] exist Figure 3A In the structure of the power supply circuit, the wiring for supplying the constant voltage Vout to the functional circuit 32 included in the upper die 30_3 (or the lower die 30_1) generates a voltage drop due to the resistance 35A of the through electrode 41B and the resistance 35B of the wiring of the die 30_3 including the functional circuit 32 ( Figure 3B ). So, if Figure 3B As shown, the constant voltage Vout output by the power supply circuit 31 is used as the voltage Vout-V TSV (V TSV The voltage drop of the resistor 35A and the resistor 35B is supplied to the functional circuit 32. That is, in the amplifier circuit 33 of the power supply circuit 31 included in the bare chip 30_2, there is a voltage Vout-V TSV Concerns about not being able to respond.

[0055] When the power supply circuit 31 and the functional circuit 32 are far apart, the voltage drop of the structure in which the desired voltage is not fed back to the amplifier circuit 33 is more obvious. Figure 4A As shown, when the power supply circuit 31 is provided on the base die 20, and the die 30 having the functional circuit 32 supplied with the constant voltage Vout is provided on the uppermost die 30_N (N is an integer greater than or equal to 2), the voltage drop is significant due to the resistors 35A and 35B of the through electrode 41B provided in each die of the N layer. Specifically, Figure 4A As shown, the constant voltage Vout output by the power supply circuit 31 is supplied to the functional circuit 32 as a voltage Vout-N×VTSV That is, in the amplifier circuit 33 of the power circuit 31 included in the bare chip 30_2, the difference between the voltage Vout fed back and the voltage Vout-N×V supplied to the functional circuit 32 cannot be ignored. TSV difference.

[0056] In the structure of one embodiment of the present invention, the bare chip 30_2 including the power supply circuit 31 that generates the constant voltage Vout by being supplied with the constant voltage Vin and the reference voltage Vref and the bare chips 30_1 and 30_3 including the functional circuit 32 that operates by being supplied with the constant voltage Vout can be arranged close to each other in a manner of contacting each other in the upper layer or the lower layer. Therefore, the difference between the voltage Vout fed back and the voltage supplied to the functional circuit 32 can be reduced.

[0057] Specifically, if Figure 4B As shown in the schematic diagram of the circuit diagram shown in FIG. 1 , the input terminals of the functional circuit 32 and the amplifier circuit 33 can be arranged close to each other, and the voltage can be fed back to the amplifier circuit 33 through the through electrode 41D different from the through electrode 41B. Although the voltage to be fed back has a voltage drop corresponding to the resistance 35C of the through electrode 41D, the voltage drop corresponding to the resistance 35B required for the lead of the bare chip 30_3 is reduced. Therefore, a voltage close to the constant voltage Vout supplied to the functional circuit 32 can be fed back to the amplifier circuit 33.

[0058] Figure 1A Although the power supply circuit 31 that supplies the constant voltage Vout based on the constant voltage Vin and the reference voltage Vref is shown, a configuration may be adopted in which a plurality of power supply circuits 31 are provided and a plurality of constant voltages are supplied to the functional circuits.

[0059] Figure 5A 1 is a block diagram of a semiconductor device 10C including a power supply circuit 31A that supplies a constant voltage Vout1 to a functional circuit 32A based on a constant voltage Vin and a reference voltage Vref, and a power supply circuit 31B that supplies a constant voltage Vout2 to a functional circuit 32B based on a constant voltage Vin and a reference voltage Vref.

[0060] like Figure 5B As shown in the schematic diagram, Figure 5A The components of can be configured in multiple dies (for example, 30_1 to 30_6) on the base die 20. Figure 5B In the structure, a die 30_2 including a power supply circuit 31A is provided, and a constant voltage Vout1 is supplied from the power supply circuit 31 included in the die 30_2 which is far from the base die 20 to the functional circuit 32A included in the die 30_1 and 30_3 which are adjacent to the die 30_2. Figure 5BIn the structure, a die 30_5 including a power supply circuit 31B is provided, and a constant voltage Vout2 is supplied from the power supply circuit 31 included in the die 30_5 far from the base die 20 to the functional circuit 32B included in the die 30_4 and 30_6 adjacent to the die 30_5. The base die 20, the die 30_2 and the die 30_5 are electrically connected through the through electrode 41A. The die 30_2 is electrically connected to the die 30_1 and 30_3 through the through electrode 41B_1. The die 30_5 is electrically connected to the die 30_4 and 30_6 through the through electrode 41B_2.

[0061] By adopting Figure 5A and Figure 5B In the structure in which a plurality of bare chips are stacked three-dimensionally on a base bare chip, the uniformity of the voltage supplied by the power circuit can be easily ensured in the power management in the Z direction. In addition, the power circuit can be provided close to the functional circuit while the voltage required for generating a constant voltage is supplied to the bare chip far from the base bare chip. In addition, since the plurality of functional circuits 32A and 32B can be arranged at a uniform distance from the power circuits 31A and 31B, a semiconductor device having excellent uniformity of the voltage supplied to each functional circuit 32A and 32B can be realized.

[0062] Fig. 6A , Figure 6B An example of an integrated circuit (also referred to as an IC chip) including the above-described semiconductor device 10 is shown. The semiconductor device 10 can be made into one IC chip by mounting a plurality of bare chips on a package substrate. Fig. 6A and Figure 6B An example of this structure is shown.

[0063] Fig. 6A The schematic cross-sectional view of the IC chip 100A shown shows a semiconductor device 10 including a base die 20 on a package substrate 101, and as an example, three layers of die 30_1 to 30_3 are stacked on the base die 20. The package substrate 101 is provided with solder balls 102 for connecting the IC chip 100A to a printed circuit board or the like. The die 30_1 to 30_3 can be connected to the base die 20 using through electrodes 41A and 41B provided through the die 30_1 to 30_3. In addition, the layers can be electrically connected through metal bumps 42 (also referred to as micro bumps) between the through electrodes 41A and 41B provided through the layers.

[0064] Note that the bare chips 30_1 to 30_3 may have a structure without using the metal bumps 42. In this case, a structure in which the bare chips are bonded to each other and the electrodes provided in a manner exposed on the surface are electrically connected may be used. As a technique for electrically connecting different layers using electrodes provided in a manner exposed on the surface, Cu-Cu bonding may be used. Cu-Cu bonding is a technique for electrically connecting Cu (copper) pads by connecting them to each other.

[0065] Furthermore, as another example, Figure 6B The schematic cross-sectional view of the IC chip 100B shown is as follows: Fig. 6A In the structure of stacked dies 30_1 to 30_3 shown, a heat diffusion layer 50 is provided between die 30_1 and die 30_2 and between die 30_2 and die 30_3, and a heat dissipation layer 52 is provided on the upper layer of the dies 30_1 to 30_3. Metal bumps and through-electrode connections are preferably used between the heat diffusion layer 50 and the heat dissipation layer 52 to improve thermal conductivity.

[0066] The heat diffusion layer 50 and the heat dissipation layer 52 are preferably made of a material having excellent thermal conductivity, for example, a metal layer or a layer containing an organic material. In addition, it is preferred to provide a heat sink or the like on the upper layer of the heat dissipation layer to improve heat dissipation. The heat dissipation layer 52 is preferably a layer having excellent adhesion to the heat sink or the like.

[0067] In addition, compared with the switching regulator, the series regulator that can be used for the power supply circuit 31 can be miniaturized, but the conversion efficiency is reduced. Therefore, it is easy to generate heat in the process of generating the constant voltage Vout. Therefore, by using the heat diffusion layer 50 and the heat dissipation layer 52 to promote heat dissipation, a semiconductor device and IC chip with excellent reliability can be realized.

[0068] As described above, in one embodiment of the present invention, in a structure in which a plurality of bare chips are three-dimensionally stacked on a base bare chip, the uniformity of the voltage supplied by the power supply circuit in the Z direction can be easily ensured. In addition, the power supply circuit can be provided close to the functional circuit while supplying the voltage required to generate a constant voltage to a bare chip that is farther from the base bare chip. In addition, the plurality of functional circuits can be arranged at a uniform distance from the power supply circuit, so that a semiconductor device having excellent uniformity of the voltage supplied to each functional circuit 32 can be realized.

[0069] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0070] (Implementation Method 2) In this embodiment, a modified example of the semiconductor device described in the above embodiment is described. Note that the same reference numerals are used for portions that overlap with those described in the above embodiment 1, and description thereof is omitted.

[0071] Fig. 7A 1 is a cross-sectional view for explaining a modified example of a die that can be stacked on a base die included in the semiconductor device 10. Figure 7B and Figure 7C Yes Fig. 7A The structure is used in Fig. 6A A schematic cross-sectional view of a semiconductor device 10 mounted on an IC chip is a schematic cross-sectional view of a semiconductor device.

[0072] Fig. 7A The bare chip 30S shown shows a structure in which the element layers 40_1 to 40_4 including the OS transistor 48 are provided on the base bare chip 20S including the Si transistor 49. In addition, the electrode 47 for electrically connecting the base bare chip 20S and the element layers 40_1 to 40_4 can be provided in the process of manufacturing the Si transistor 49 or the OS transistor 48. Note that in this embodiment, etc., the number of element layers represented by the element layers 40_1 to 40_4 is not limited to four layers, and two or more layers are sufficient. Note that when there are common items in each layer of the element layers 40_1 to 40_4, sometimes it is simply recorded as "element layer 40".

[0073] Fig. 7A The structure may be a monolithic structure in which the connection between the base die 20S including the Si transistor 49 and the element layers 40_1 to 40_4 including the OS transistor does not utilize a technology using a through electrode such as TSV or a Cu-Cu direct bonding technology. The element layers 40_1 to 40_4 on the base die 20S may have a structure in which wiring provided together with the OS transistor 48 included in the element layers 40_1 to 40_4 is used as an electrode 47 for connecting an upper or lower element layer.

[0074] Compared with through-electrodes used in TSV or Cu-Cu direct bonding technology, the spacing of wiring provided together with the OS transistor 48 can be finely processed. Fig. 7A In the structure of the bare chip 30S shown, the number of electrodes used to connect the upper or lower element layers can be increased. Therefore, the number of wirings (number of signal lines) of the functional circuits provided in the element layers 40_1 to 40_4 and the functional circuits provided in the base bare chip 20S can be increased. In other words, the number of channels between the functional circuits can be increased. Therefore, the transmission amount (bandwidth) of the signals sent and received between the functional circuits can be increased. By increasing the bandwidth, the amount of data transmission per unit time can be increased.

[0075] Metal oxides used for OS transistors include, for example, indium oxide, gallium oxide, and zinc oxide. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, antimony, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0076] In particular, as the metal oxide, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin and zinc (also referred to as ITZO) is preferably used. Alternatively, an oxide containing indium, gallium, tin and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also referred to as IAGZO) is preferably used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn) and tin (Sn) (also referred to as IGZTO) is preferably used.

[0077] In addition, the metal oxide used for the OS transistor may include two or more metal oxide layers with different compositions. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto provided on the first metal oxide layer may be appropriately used.

[0078] Alternatively, for example, a stacked-layer structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO may be used.

[0079] In addition, the metal oxide used for the OS transistor preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC (c-axis-aligned crystalline)-OS and nc (nanocrystalline)-OS. By using crystalline oxide semiconductors, a semiconductor device with high reliability can be provided.

[0080] In addition, the OS transistor operates stably even in a high temperature environment, and the characteristics vary little. For example, even in a high temperature environment, the off-state current hardly increases. Specifically, even in an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high temperature environment, the on-state current is not easily reduced. Therefore, a memory cell with an OS transistor can operate stably in a high temperature environment and has high reliability.

[0081] As a functional circuit that can be provided in the element layer 40 including the OS transistor, a memory circuit is preferably used. As a memory cell that can be used for the memory circuit, NOSRAM is preferably used. NOSRAM (registered trademark) is an abbreviation of "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)". The memory cell of NOSRAM is a two-transistor type (2T) or three-transistor type (3T) gain cell.

[0082] When the OS transistor is turned off, the current flowing between the source and the drain, i.e., the leakage current, is extremely small. NOSRAM can be used as a non-volatile memory by using the extremely small leakage current to retain the charge corresponding to the data in the storage cell. In particular, NOSRAM can read out the data without destroying it (non-destructive reading), so it is suitable for arithmetic processing that only repeats the data reading operation multiple times.

[0083] Figure 7B It is a combination Fig. 7A FIG. 1 is a schematic cross-sectional view of a configuration example of an IC chip 100C including a bare chip 30S and a power supply circuit 31 described in the first embodiment.

[0084] exist Figure 7B In the IC chip 100C shown, the structure applied to the bare chips 30S_1 and 30S_2 is a monolithic structure that does not use a through-electrode technology such as TSV or Cu-Cu direct bonding technology in the element layer, thereby enabling micro-processing of the wiring provided in the element layer. Figure 7B In the structure of the IC chip 100C shown, the number of electrodes for connecting to the upper or lower element layer can be increased in the bare chips 30S_1 and 30S_2 provided with the functional circuits, so that the transmission amount (bandwidth) of the signals sent and received between the functional circuits can be increased and the data transmission amount per unit time can be increased.

[0085] in addition, Figure 7B The structure of the IC chip shown can be used Figure 7C An example of the structure of an IC chip 100D is shown. Figure 7CThe die 30S_2 disposed on the upper layer and the die 30S_1 disposed on the lower layer are symmetrically arranged with the die 30 as the boundary. Specifically, the configuration is shown in which the base die 20S disposed on the lower layer (die 30S_1), the element layers 40_1 to 40_4 disposed on the lower layer (die 30S_1), the die 30, the element layers 40_1 to 40_4 disposed on the upper layer (die 30S_2), and the base die 20S disposed on the upper layer (die 30S_2) are sequentially stacked. By adopting this structure, the uniformity of the voltage supplied by the power supply circuit 31 can be improved for the functional circuits included in each of the die 30S_1 and 30S_2.

[0086] Next, a configuration example of a functional circuit 32M serving as a memory circuit using a NOSRAM that can be used in the element layers 40_1 to 40_4 including OS transistors as a memory cell will be described.

[0087] Fig. 8A The functional circuit 32M shown includes a memory cell array 60 and a peripheral circuit 65. The peripheral circuit 65 includes a control circuit 61, a row circuit 62, a column circuit 63, and an input / output circuit 64.

[0088] The memory cell array 60 includes a memory cell 66, a word line RWL, a word line WWL, a bit line RBL, a bit line WBL, a source line SL, and a wiring BGL. In addition, the word line RWL is sometimes referred to as a read word line. In addition, the wiring WWL is sometimes referred to as a write word line. The wiring RBL is sometimes referred to as a read bit line. The wiring WBL is sometimes referred to as a write bit line.

[0089] The control circuit 61 controls writing and reading of data and processes command signals from the outside (for example, a chip enable signal, a write enable signal, etc.) to generate control signals for other circuits of the peripheral circuit 65 .

[0090] The row circuit 62 has a function of selecting a row to be accessed. For example, the row circuit 62 includes a row decoder and a word line driver. The column circuit 63 has a function of precharging the bit lines WBL and RBL, a function of writing data to the bit line WBL, a function of amplifying the data of the bit line RBL, a function of reading data from the bit line RBL, etc. The input / output circuit 64 has a function of holding the written data and a function of holding the read data, etc.

[0091] The configuration of the peripheral circuit 65 is appropriately changed according to the configuration of the memory cell array 60 , the reading method, the writing method, etc. In addition, a part of the peripheral circuit 65 is preferably provided in the base die 20S.

[0092] Figure 8BAn example of a circuit structure of a memory cell 66 is shown. Here, the memory cell 66 is a two-transistor type (2T) gain cell. The memory cell 66 includes transistors MW1, MR1 and a capacitor CS1. The transistor MW1 is a write transistor, and the transistor MR1 is a read transistor. The back gates of the transistors MW1 and MR1 are electrically connected to the wiring BGL.

[0093] Since the write transistor is composed of an OS transistor, the memory cell 66 does not consume power when holding data. Therefore, the memory cell 66 is a low-power memory cell that can hold data for a long time, and the functional circuit 32M can be used as a nonvolatile memory device.

[0094] Reference 9A to 9D Other structural examples of the storage unit will be described.

[0095] Fig. 9A The memory cell 66A shown is a 3T-type gain cell and includes transistors MW2, MR2, MS2 and a capacitor element CS2. Transistors MW2, MR2, and MS2 are respectively a write transistor, a read transistor, and a select transistor. The back gates of transistors MW2, MR2, and MS2 are electrically connected to wiring BGL. The memory cell 66A is electrically connected to word lines RWL, WWL, bit lines RBL, WBL, capacitor line CDL, and power line PL2. For example, the capacitor line CDL and the power line PL2 are input with voltage GND (low-level side power supply voltage).

[0096] Fig. 9B 2T-type gain unit. Fig. 9B In the illustrated memory cell 66B, the readout transistor is formed of an OS transistor that does not include a back gate.

[0097] Fig. 9C Other structural examples of 3T-type gain cells are shown. Fig. 9C In the memory cell 66C shown, the read transistor and the select transistor are formed of OS transistors that do not include a back gate.

[0098] In the above-mentioned gain unit, a bit line serving also as the bit line RBL and the bit line WBL may be provided.

[0099] In addition, as a structure that can be applied to the memory cell 66, NOSRAM is used as an example to explain, but other structures can be used as long as the memory cell can be formed using OS transistors. For example, DOSRAM, which is a memory circuit including OS transistors, can also be used. DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor RAM (dynamic oxide semiconductor random access memory)", and refers to a RAM including 1T (transistor) 1C (capacitor) type memory cells. DOSRAM is a DRAM formed using OS transistors, and DOSRAM is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current characteristic of OS transistors.

[0100] Fig.9D An example of a 1T1C (capacitor) type memory cell is shown. Fig.9D The memory cell 66D shown is electrically connected to the word line WL, the bit line BL, the capacitor line CDL, and the wiring BGL. The memory cell 66D includes a transistor MW3 and a capacitor CS3. The back gate of the transistor MW3 is electrically connected to the wiring BGL.

[0101] When the memory cell 66 is a NOSRAM or a DOSRAM, it is preferable that the transistor ( Figure 8B The word line WWL of the gate of the transistor MW1 applies a voltage that turns off the transistor and performs power gating on other parts. By adopting this structure, the supply of power supply voltage can be stopped when the memory cell 66 stores data.

[0102] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0103] (Implementation 3) In this embodiment, a transistor structure applicable to the semiconductor device described in the above embodiment is described. As an example, a structure in which transistors having different electrical characteristics are stacked is described. By adopting this structure, the degree of freedom in designing the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the integration of the semiconductor device can be increased.

[0104] Fig.10 A partial cross-sectional structure of a semiconductor device is shown. Fig.10 The semiconductor device shown includes a transistor 550 , a transistor 500 , and a capacitor 600 . Fig.11A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 11B is a cross-sectional view of the transistor 500 in the channel width direction, Fig. 11C2 is a cross-sectional view in the channel width direction of the transistor 550. For example, the transistor 500 corresponds to the OS transistor described in the above embodiment, and the transistor 550 corresponds to the Si transistor.

[0105] exist Fig.10 In the embodiment, the transistor 500 is disposed above the transistor 550 , and the capacitor 600 is disposed above the transistor 550 and the transistor 500 .

[0106] The transistor 550 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a portion of the substrate 311, and low resistance regions 314a and 314b functioning as source regions or drain regions.

[0107] like Fig. 11C As shown, in the transistor 550, the conductor 316 covers the top surface and the side surface in the channel width direction of the semiconductor region 313 via the insulator 315. In this way, by making the transistor 550 have a Fin-type structure, the effective channel width increases, thereby improving the on-state characteristics of the transistor 550. In addition, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristics of the transistor 550 can be improved.

[0108] Furthermore, transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0109] The channel formation region of the semiconductor region 313, the region near it, the low resistance region 314a and the low resistance region 314b used as the source region or the drain region, etc. preferably contain semiconductors such as silicon-based semiconductors, and more preferably contain single crystal silicon. In addition, it can also be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenic), etc. Silicon that applies stress to the lattice to change the interplanar spacing to control the effective mass can be used. In addition, the transistor 550 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0110] The low resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0111] As the conductor 316 serving as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0112] In addition, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferred in terms of heat resistance.

[0113] Alternatively, the transistor 550 may be formed using a SOI (Silicon on Insulator) substrate or the like.

[0114] In addition, as SOI substrates, there can be used: SIMOX (Separation by Implanted Oxygen) substrates formed by forming an oxide layer in a region at a certain depth from the surface and eliminating defects generated in the surface layer after oxygen ion implantation in a mirror-polished thin slice, and SOI substrates formed by the smart peeling method or ELTRAN method (registered trademark: Epitaxial Layer Transfer) in which a semiconductor substrate is split by growing tiny gaps formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate includes a single crystal semiconductor in a channel formation region.

[0115] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 550 .

[0116] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0117] Note that in this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. Note that in this specification, aluminum oxynitride refers to a material containing more oxygen than nitrogen in its composition, and aluminum nitride oxide refers to a material containing more nitrogen than oxygen in its composition.

[0118] The insulator 322 may also be used as a planarization film for planarizing a step caused by the transistor 550 disposed thereunder, etc. For example, in order to improve the planarity of the top surface of the insulator 322, the top surface may be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0119] As the insulator 324 , a film having a barrier property that can prevent hydrogen, impurities, and the like from diffusing from the substrate 311 , the transistor 550 , or the like into a region where the transistor 500 is provided is preferably used.

[0120] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 550. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0121] The amount of hydrogen released can be analyzed by, for example, thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in the TDS analysis is in the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 1×10 16 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following will do.

[0122] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0123] In addition, conductors 328 and 330 connected to capacitor 600 and transistor 500 are embedded in insulators 320, 322, 324, and 326. In addition, conductors 328 and 330 have the function of plugs or wiring. Note that the same symbol is sometimes used to represent multiple conductors having the function of plugs or wiring. In addition, in this specification, wiring and a plug connected to the wiring can also be one component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0124] As the material of each plug and wiring (conductor 328, conductor 330, etc.), a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, preferably tungsten. Alternatively, it is preferred to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0125] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.10In the embodiment of the present invention, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed between the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function of a plug or wiring connected to the transistor 550. The conductor 356 can be made of the same material as the conductor 328 and the conductor 330.

[0126] In addition, similar to the insulator 324, the insulator 350 preferably uses an insulator having a barrier property to hydrogen, for example. In addition, the conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 350 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0127] Note that as a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is preferably used. Furthermore, by stacking tantalum nitride and tungsten having high conductivity, it is possible to maintain the conductivity as a wiring and suppress the diffusion of hydrogen from the transistor 550. At this time, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

[0128] Alternatively, a wiring layer may be provided on the insulator 354 and the conductor 356. Fig.10 In the embodiment, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function of a plug or wiring. In addition, the conductor 366 can use the same material as the conductor 328 and the conductor 330.

[0129] In addition, similar to the insulator 324, the insulator 360 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 360 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0130] Alternatively, a wiring layer may be provided on the insulator 364 and the conductor 366. Fig.10 In the embodiment, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function of a plug or wiring. In addition, the conductor 376 can use the same material as the conductor 328 and the conductor 330.

[0131] In addition, similar to the insulator 324, the insulator 370 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 370 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0132] Alternatively, a wiring layer may be provided on the insulator 374 and the conductor 376. Fig.10 In the embodiment, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 has a function of a plug or wiring. In addition, the conductor 386 can use the same material as the conductor 328 and the conductor 330.

[0133] In addition, similar to the insulator 324, the insulator 380 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 380 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, so that the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0134] In the above description, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described, but the semiconductor device according to the present embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

[0135] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. As any of the insulators 510, 512, 514, and 516, a substance having a barrier property against oxygen, hydrogen, and the like is preferably used.

[0136] For example, as the insulator 510 and the insulator 514, a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided is preferably used. Therefore, the insulator 510 and the insulator 514 can use the same material as the insulator 324.

[0137] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 550. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0138] In addition, for example, as a film having a barrier property against hydrogen, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide are preferably used for the insulator 510 and the insulator 514 .

[0139] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from penetrating. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0140] In addition, for example, the insulator 512 and the insulator 516 can use the same material as the insulator 320. In addition, by using a material with a low dielectric constant for the insulator, the parasitic capacitance generated between the wirings can be reduced. For example, the insulator 512 and the insulator 516 can use a silicon oxide film or a silicon oxynitride film.

[0141] In addition, a conductor 518 and a conductor (for example, conductor 503) constituting the transistor 500 are embedded in the insulators 510, 512, 514, and 516. The conductor 518 is used as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be made of the same material as the conductors 328 and 330.

[0142] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. With this structure, the transistor 550 can be separated from the transistor 500 by a layer having a barrier property to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 550 into the transistor 500.

[0143] The transistor 500 is disposed above the insulator 516 .

[0144] like Fig.11A and Fig. 11BAs shown, transistor 500 includes a conductor 503 configured in a manner embedded in an insulator 514 and an insulator 516, an insulator 520 configured on the insulator 516 and the conductor 503, an insulator 522 configured on the insulator 520, an insulator 524 configured on the insulator 522, an oxide 530a configured on the insulator 524, an oxide 530b configured on the oxide 530a, a conductor 542a and a conductor 542b configured separately from each other on the oxide 530b, an insulator 580 configured on the conductors 542a and 542b and forming an opening in a manner overlapping between the conductors 542a and 542b, an insulator 545 configured on the bottom and side surfaces of the opening, and a conductor 560 configured on the formation surface of the insulator 545.

[0145] In addition, if Fig.11A and Fig. 11B As shown in FIG. 5 , an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Fig.11A and Fig. 11B As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 545 and a conductor 560b disposed in a manner embedded inside the conductor 560a. Fig.11A and Fig. 11B As shown, an insulator 574 is preferably arranged on the insulator 580 , the conductor 560 , and the insulator 545 .

[0146] Note that in this specification and the like, the oxide 530 a and the oxide 530 b may be collectively referred to as an oxide 530 .

[0147] In the transistor 500, two layers of oxide 530a and oxide 530b are stacked in the channel forming region and its vicinity, but the present invention is not limited thereto. For example, the oxide 530b may have a single layer structure or a stacked structure of three or more layers.

[0148] In addition, in the transistor 500, the conductor 560 has a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 560 may also have a single-layer structure or a stacked structure of three or more layers. Note that Fig.10 and Fig.11A The structure of the transistor 500 shown is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure, driving method, etc.

[0149] Here, the conductor 560 is used as the gate electrode of the transistor, and the conductor 542a and the conductor 542b are used as the source electrode or the drain electrode. As described above, the conductor 560 is set in a manner embedded in the opening of the insulator 580 and in the area sandwiched between the conductor 542a and the conductor 542b. The configuration of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner according to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be configured in a self-aligned manner between the source electrode and the drain electrode. Thus, the conductor 560 can be formed in a manner without providing room for alignment, so that the occupied area of ​​the transistor 500 can be reduced. Thus, miniaturization and high integration of semiconductor devices can be achieved.

[0150] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not include a region overlapping with the conductor 542a or the conductor 542b. Thus, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be increased, so that the transistor 500 can have high frequency characteristics.

[0151] Conductor 560 is sometimes used as a first gate (also called a top gate) electrode. Conductor 503 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by independently changing the potential supplied to conductor 503 without linking it with the potential supplied to conductor 560. In particular, by supplying a negative potential to conductor 503, the threshold voltage of transistor 500 can be made to exceed 0V to reduce the off-state current. Therefore, compared with when no negative potential is applied to conductor 503, when a negative potential is applied to conductor 503, the drain current when the potential applied to conductor 560 is 0V can be reduced.

[0152] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated by the conductor 560 and the electric field generated by the conductor 503 are connected to each other, and a channel formation region formed in the oxide 530 can be covered.

[0153] In this specification, etc., the structure of a transistor in which the electric field of the first gate electrode electrically surrounds the channel forming region is called a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. has a structure different from the Fin-type structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can also be regarded as a type of Fin-type structure. In this specification, etc., the Fin-type structure refers to a structure in which the gate electrode is configured in a manner surrounding at least two or more surfaces of the channel (specifically, two surfaces, three surfaces or four surfaces, etc.). By adopting the Fin-type structure and the S-channel structure, a transistor with improved resistance to short channel effects can be realized. In other words, a transistor that is not prone to short channel effects can be realized.

[0154] By adopting a transistor having the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. In addition, the S-channel structure can also be said to be substantially equivalent to a GAA (Gate All Around: full surround gate) structure or a LGAA (Lateral Gate All Around: lateral full surround gate) structure because it electrically surrounds the channel formation region. By making the transistor have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be regarded as the entire bulk of the oxide 530. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor will be improved.

[0155] In addition, the conductor 503 has the same structure as the conductor 518, and the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is formed inside. In addition, in the transistor 500, the conductor 503a and the conductor 503b are stacked, but the present invention is not limited to this. For example, the conductor 503 may have a single-layer structure or a stacked structure of three or more layers.

[0156] Here, as the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (not allowing the above oxygen to pass through easily). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0157] For example, by providing the conductor 503a with a function of suppressing the diffusion of oxygen, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.

[0158] In addition, when the conductor 503 also has a wiring function, it is preferable to use a conductive material with high conductivity whose main component is tungsten, copper or aluminum as the conductor 503b. In addition, although the conductor 503 composed of a stack of conductors 503a and 503b is shown in this embodiment, the conductor 503 may also have a single-layer structure.

[0159] The insulator 520 , the insulator 522 , and the insulator 524 serve as a second gate insulating film.

[0160] Here, the insulator 524 in contact with the oxide 530 preferably contains oxygen exceeding the stoichiometric composition. This oxygen is easily released from the film by heating. In this specification, etc., the oxygen released by heating is sometimes referred to as "excess oxygen". That is, it is preferred that a region containing excess oxygen (also referred to as "excess oxygen region") is formed in the insulator 524. By providing the insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : oxygen vacancy), thereby improving the reliability of the transistor 500. In addition, when hydrogen enters the oxygen vacancy of the oxide 530, the defect (hereinafter, sometimes referred to as V O H) is used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, since hydrogen in oxide semiconductors is easily moved due to heat, electric field, etc., when oxide semiconductors contain a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, it is preferred to minimize the V O H and become high purity intrinsic or substantially high purity intrinsic. In this way, in order to obtain such V O To prepare an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as "dehydration" or "dehydrogenation treatment"); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as "oxidation treatment"). O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, and can provide stable electrical characteristics.

[0161] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0162] In addition, one or more of heating treatment, microwave treatment, or RF treatment may be performed in such a manner that the insulator having the excess oxygen region and the oxide 530 are in contact with each other. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 in which VoH bonding is severed, in other words, a “V O H→Vo+H” reaction can be dehydrogenated. A part of the hydrogen generated at this time is sometimes bonded to oxygen and removed from the oxide 530 or the insulator near the oxide 530 as H2O. In addition, a part of the hydrogen is sometimes doped by the conductor 542.

[0163] In addition, as the above-mentioned microwave treatment, for example, it is preferred to use a device including a power supply for generating high-density plasma or a device including a power supply for applying RF to one side of the substrate. For example, by using a gas containing oxygen and a high-density plasma, a high-density oxygen radical can be generated, and by applying RF to one side of the substrate, the oxygen radical generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530. In addition, in the above-mentioned microwave treatment, the pressure is 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, as the gas introduced into the device for microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0164] In addition, in the manufacturing process of transistor 500, it is preferred to perform heat treatment in a state where the surface of oxide 530 is exposed. The heat treatment can be performed, for example, at a temperature of 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thus, oxygen can be supplied to oxide 530 to reduce oxygen vacancies (V O ). In addition, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen or an inert gas, and then the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more to fill the oxygen that has been separated. Alternatively, the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more, and then the heat treatment may be performed continuously in an atmosphere of nitrogen or an inert gas.

[0165] In addition, by performing an oxidation treatment on the oxide 530, the supplied oxygen can fill the oxygen vacancies in the oxide 530. In other words, the reaction of "Vo+O→null" can be promoted. Furthermore, by reacting the hydrogen remaining in the oxide 530 with the supplied oxygen, the hydrogen can be removed as H2O (dehydration). Thus, the hydrogen remaining in the oxide 530 can be suppressed from re-bonding with the oxygen vacancies to form V. O H.

[0166] When the insulator 524 has an excess oxygen region, the insulator 524 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0167] The insulator 522 preferably has a function of suppressing diffusion of oxygen, impurities, and the like, because oxygen included in the oxide 530 does not diffuse toward the insulator 520. In addition, the conductor 503 can be suppressed from reacting with oxygen included in the insulator 524 or the oxide 530.

[0168] As the insulator 522, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are performed, problems such as leakage current sometimes occur due to the thin film of the gate insulating film. By using a high-k material as an insulator used as a gate insulating film, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0169] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material having a function of suppressing the diffusion of impurities and oxygen (not allowing the above oxygen to pass easily). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 522 is formed using such a material, the insulator 522 is used as a layer that suppresses the release of oxygen from the oxide 530 or the entry of impurities such as hydrogen into the oxide 530 from the surrounding part of the transistor 500.

[0170] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. In addition, the insulator may be nitrided. In addition, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0171] In addition, the insulator 520 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure with thermal stability and a high relative dielectric constant can be formed.

[0172] Note that in Figures 11 and Fig. 11B In the transistor 500, the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer stacked structure, but the second gate insulating film may also have a single-layer structure, a two-layer structure, or a stacked structure of four or more layers. In this case, the stacked structure is not limited to being made of the same material, and a stacked structure made of different materials may be used.

[0173] In the transistor 500, a metal oxide that functions as an oxide semiconductor is used as an oxide 530 including a channel formation region. For example, as the oxide 530, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used.

[0174] The metal oxide used as the oxide semiconductor can be formed by a sputtering method or by an ALD (Atomic Layer Deposition) method. Note that the metal oxide used as the oxide semiconductor is described in detail in another embodiment.

[0175] The metal oxide used as the channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0176] In the oxide 530 , when the oxide 530 a is provided below the oxide 530 b , diffusion of impurities from a structure formed below the oxide 530 a to the oxide 530 b can be suppressed.

[0177] In addition, the oxide 530 preferably has a structure of multiple oxide layers in which the atomic number ratios of the metal atoms are different from each other. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530b. In addition, the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530b. In addition, the atomic number ratio of In in the metal oxide used for the oxide 530b is preferably greater than the atomic number ratio of In in the metal oxide used for the oxide 530a.

[0178] In addition, it is preferable that the energy of the conduction band bottom of the oxide 530a is higher than the energy of the conduction band bottom of the oxide 530b. In other words, the electron affinity of the oxide 530a is preferably lower than the electron affinity of the oxide 530b.

[0179] Here, in the junction of oxide 530a and oxide 530b, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of oxide 530a and oxide 530b continuously changes or continuously joins. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0180] Specifically, by making the oxide 530a and the oxide 530b contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0181] At this time, the main path of the carrier is oxide 530b. By making oxide 530a have the above structure, the defect state density at the interface between oxide 530a and oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of transistor 500 can be increased.

[0182] Conductors 542a and 542b serving as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing the above metal elements as components, or alloys combining the above metal elements are preferably used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, and the like are preferably used. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. In addition, metal nitride films such as tantalum nitride have barrier properties against hydrogen or oxygen, so they are more preferred.

[0183] In addition, although Fig.11A Although the single-layer structure of the conductor 542a and the conductor 542b is shown, a stacked structure of two or more layers may be adopted. For example, it is preferable to stack a tantalum nitride film and a tungsten film. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure of stacking an aluminum film on a tungsten film, a two-layer structure of stacking a copper film on a copper-magnesium-aluminum alloy film, a two-layer structure of stacking a copper film on a titanium film, and a two-layer structure of stacking a copper film on a tungsten film may also be adopted.

[0184] In addition, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0185] In addition, if Fig.11A As shown, sometimes, a region 543a and a region 543b are formed as a low resistance region at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. In this case, the region 543a is used as one of the source region and the drain region, and the region 543b is used as the other of the source region and the drain region. In addition, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0186] The oxygen concentration of the region 543a (region 543b) may be reduced by providing the above-mentioned conductor 542a (conductor 542b) in contact with the oxide 530. In addition, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In this case, the carrier density of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.

[0187] The insulator 544 is provided so as to cover the conductors 542 a and 542 b and suppress oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0188] The insulator 544 can be made of a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium. Alternatively, the insulator 544 can be made of silicon nitride oxide or silicon nitride.

[0189] In particular, as the insulator 544, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing oxides of one or both of aluminum and hafnium, are preferably used. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. In addition, insulator 544 does not necessarily need to be provided when conductor 542a and conductor 542b are composed of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed. It can be appropriately designed according to the required transistor characteristics.

[0190] By including the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 into the oxide 530b. In addition, it is possible to suppress the oxidation of the conductor 542 by excess oxygen contained in the insulator 580.

[0191] The insulator 545 is used as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similarly to the insulator 524 described above.

[0192] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0193] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied to the channel formation region of the oxide 530b from the insulator 545. In addition, as with the insulator 524, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 545. The thickness of the insulator 545 is preferably not less than 1 nm and not more than 20 nm.

[0194] In addition, in order to efficiently supply the excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, the amount of excess oxygen supplied to the oxide 530 can be suppressed from decreasing. In addition, the oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0195] In addition, like the second gate insulating film, the insulator 545 may also have a stacked structure. When miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to the thin film of the gate insulating film. Therefore, by using the insulator used as the gate insulating film to have a stacked structure of a high-k material and a material with thermal stability, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a stacked structure with thermal stability and a high relative dielectric constant can be realized.

[0196] exist Fig.11A and Fig. 11B In the embodiment, the conductor 560 serving as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.

[0197] As the conductor 560a, it is preferred to use a conductive material having the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, it is preferred to use a conductive material having the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductor 560a have the function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by the oxidation of the conductor 560b due to the oxygen contained in the insulator 545. As a conductive material having the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium or ruthenium oxide, etc. are preferably used. In addition, as the conductor 560a, an oxide semiconductor that can be applied to the oxide 530 can be used. In this case, by forming the conductor 560b by sputtering, the resistance value of the conductor 560a can be reduced to make it a conductor. It can be called an OC (Oxide Conductor) electrode.

[0198] As the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper or aluminum. Since the conductor 560b is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper or aluminum can be used. The conductor 560b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials can be used.

[0199] The insulator 580 is preferably disposed on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In particular, silicon oxide and silicon oxide with pores are preferred because they are easy to form an excess oxygen region in the subsequent process.

[0200] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 to release oxygen when heated, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 580.

[0201] The opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b. Thus, the conductor 560 is provided so as to be embedded in the opening of the insulator 580 and in the region between the conductor 542a and the conductor 542b.

[0202] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. For this reason, when the thickness of the conductor 560 is increased, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, since the conductor 560 is provided in a manner embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 does not collapse during the process.

[0203] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be formed in the insulator 545 and the insulator 580. Thus, oxygen can be supplied to the oxide 530 from the excess oxygen region.

[0204] For example, as the insulator 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0205] In particular, aluminum oxide has high barrier properties and can inhibit the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can be used as an oxygen supply source while also functioning as a barrier film for impurities such as hydrogen.

[0206] Furthermore, an insulator 581 serving as an interlayer film is preferably provided over the insulator 574. As with the insulator 524 and the like, the concentration of impurities such as water and hydrogen in the insulator 581 is preferably reduced.

[0207] In addition, the conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided so as to face each other via the conductor 560. The conductors 540a and 540b have the same structure as the conductors 546 and 548 described later.

[0208] An insulator 582 is provided on the insulator 581. The insulator 582 is preferably made of a material having a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be made of the same material as the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0209] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from passing through. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0210] Insulator 586 is provided on insulator 582. The same material as insulator 320 can be used as insulator 586. In addition, by using a material with a low dielectric constant as these insulators, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide film, silicon oxynitride film, etc. can be used as insulator 586.

[0211] In addition, the conductor 546 and the conductor 548 are embedded in the insulator 520 , the insulator 522 , the insulator 524 , the insulator 544 , the insulator 580 , the insulator 574 , the insulator 581 , the insulator 582 , and the insulator 586 .

[0212] The conductor 546 and the conductor 548 are used as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be made of the same material as the conductor 328 and the conductor 330.

[0213] In addition, after forming the transistor 500, an opening may be formed around the transistor 500, and an insulator having a high barrier to hydrogen or water may be formed to cover the opening. By wrapping the transistor 500 with the above-mentioned high barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be wrapped with an insulator having a high barrier to hydrogen or water. In addition, in the case of forming an opening around the transistor 500, for example, when an opening is formed to reach the insulator 522 or the insulator 514 and the above-mentioned high barrier insulator is formed in contact with the insulator 522 or the insulator 514, it can also serve as a part of the manufacturing process of the transistor 500, so it is preferred. In addition, as an insulator having a high barrier to hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 can be used.

[0214] Next, a capacitor 600 is provided above the transistor 500 . The capacitor 600 includes a conductor 610 , a conductor 620 , and an insulator 630 .

[0215] Furthermore, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 is used as a plug or wiring connected to the transistor 500. The conductor 610 is used as an electrode of the capacitor 600. Alternatively, the conductor 612 and the conductor 610 may be formed at the same time.

[0216] As the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements as a component (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used.

[0217] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited thereto and they may have a stacked structure of two or more layers. For example, a conductor having high tightness to the conductor having a barrier property and the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.

[0218] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Conductive materials such as metal materials, alloy materials, or metal oxide materials can be used as the conductor 620. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other components such as a conductor, low-resistance metal materials such as Cu (copper) or Al (aluminum) can be used.

[0219] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be made of the same material as the insulator 320. In addition, the insulator 640 can be used as a planarization film that covers the concavo-convex shape thereunder.

[0220] By adopting this structure, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved.

[0221] As a substrate for a semiconductor device that can be used in one embodiment of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (for example, a stainless steel substrate, a substrate containing a stainless steel foil, a tungsten substrate, a substrate containing a tungsten foil, etc.), a semiconductor substrate (for example, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate or a compound semiconductor substrate, etc.), an SOI (SOI: Silicon on Insulator) substrate, etc. can be used. In addition, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment can also be used. As an example of a glass substrate, barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass or soda-lime glass can be cited. In addition, crystallized glass, etc. can also be used.

[0222] In addition, as a substrate, a flexible substrate, a laminated film, paper or a base film containing a fibrous material can be used. As a flexible substrate, a laminated film, a base film, etc., the following examples can be cited. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Or, as an example, synthetic resins such as acrylic resins can be cited. Or, as an example, polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride can be cited. Or, as an example, polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, paper, etc. can be cited. In particular, by using semiconductor substrates, single crystal substrates or SOI substrates to manufacture transistors, it is possible to manufacture transistors with small deviations in characteristics, size or shape, high current capacity and small size. When the above-mentioned transistors are used to form a circuit, low power consumption of the circuit or high integration of the circuit can be achieved.

[0223] In addition, a flexible substrate may be used as a substrate, and transistors, resistors and / or capacitors may be directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistors, resistors and / or capacitors. The peeling layer may be used in a case where a part or all of a semiconductor device is manufactured on the peeling layer, and then the semiconductor device is separated from the substrate and transferred to another substrate. In this case, the transistors, resistors and / or capacitors may be transferred to a substrate with low heat resistance or a flexible substrate. In addition, as the above-mentioned peeling layer, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen may be used.

[0224] That is, after forming a semiconductor device on one substrate, the semiconductor device can be transferred to another substrate. As the substrate to which the semiconductor device is transferred, not only the above-mentioned substrate on which a transistor can be formed can be used, but also paper substrates, glass paper substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cuprammonium, rayon, regenerated polyester)), leather substrates, rubber substrates, etc. can be used. By using such a substrate, it is possible to manufacture a flexible semiconductor device, manufacture a semiconductor device that is not easily damaged, improve heat resistance, and reduce weight or thickness.

[0225] By providing a semiconductor device on a flexible substrate, it is possible to provide a semiconductor device that is less likely to be damaged while suppressing an increase in weight.

[0226] Fig.10 The structure of transistor 550 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure, driving method, etc. For example, when the semiconductor device is a unipolar circuit with only OS transistors (transistors of the same polarity such as only n-channel transistors), transistor 550 can have the same structure as transistor 500.

[0227] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments and examples as appropriate.

[0228] (Implementation 4) In this embodiment, a cross-sectional structure example of a semiconductor device including an OS transistor described in the above embodiment, such as a DOSRAM and a NOSRAM, is described.

[0229] Fig.12 An example of a cross-sectional structure when a circuit structure using DOSRAM is shown. Fig.12An example is shown in which element layers 700 [ 1 ] to 700 [ 4 ] are stacked on the driving circuit layer 701 .

[0230] also, Fig.12 An example of the transistor 550 included in the driver circuit layer 701 is shown. As the transistor 550, the transistor 550 described in the above embodiment mode can be applied.

[0231] also, Fig.12 The transistor 550 shown is just an example, and an appropriate transistor may be used according to the circuit structure or driving method without being limited to the structure.

[0232] A wiring layer including an interlayer film, wiring, and plugs may be provided between the driving circuit layer 701 and the element layer 700 or between the k-th element layer 700 and the k+1-th element layer 700. In addition, in the present embodiment, the k-th element layer 700 is sometimes referred to as the element layer 700[k], and the k+1-th element layer 700 is sometimes referred to as the element layer 700[k+1]. Here, k is an integer greater than 1 and less than N. In addition, in the present embodiment, when referred to as "k+α (α is an integer greater than 1)" or "k-α", the solutions of "k+α" and "k-α" are each integer greater than 1 and less than N.

[0233] In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, a wiring and a plug electrically connected to the wiring may also be one component. That is, a part of a conductor may be used as a wiring, and a part of a conductor may be used as a plug.

[0234] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 550. In addition, a conductor 328 or the like is embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 or the like is embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0235] In addition, the insulator used as the interlayer film can be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 320, planarization can also be achieved by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0236] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.12In the embodiment, an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are sequentially stacked on the insulator 326 and the conductor 330. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 is used as a contact plug or a wiring.

[0237] The insulator 514 included in the element layer 700[1] is provided on the insulator 354. In addition, the conductor 358 is embedded in the insulator 514 and the insulator 354. The conductor 358 is used as a contact plug or wiring. For example, the bit line BL and the transistor 550 are electrically connected through the conductor 358, the conductor 356, and the conductor 330.

[0238] Fig.13A An example of a cross-sectional structure of the element layer 700[k] is shown. Fig. 13B yes Fig.13A Equivalent circuit diagram of . Fig.13A An example is shown in which one bit line BL is electrically connected to two memory cells MC.

[0239] Fig.12 and Fig.13A The memory cell MC shown includes a transistor M1 and a capacitor C. As the transistor M1 , for example, the transistor 500 shown in the above embodiment can be used.

[0240] In this embodiment, a modified example of the transistor 500 is described as the transistor M1 . Specifically, the transistor M1 is different from the transistor 500 in that the conductors 542 a and 542 b extend beyond the end portions of the metal oxide 531 .

[0241] also, Fig.12 and Fig.13A The memory cell MC shown includes a conductor 156 serving as one terminal of the capacitor C, an insulator 153 serving as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) serving as the other terminal of the capacitor C. The conductor 156 is electrically connected to a portion of the conductor 542b. In addition, the conductor 160 is connected to the wiring PL (in Fig.13A (not shown) electrical connection.

[0242] Capacitor C is formed in an opening formed by removing a portion of insulator 574, insulator 580, and insulator 554. Conductor 156, insulator 153, and conductor 160a are formed along the side of the opening and are preferably deposited using ALD, CVD, or the like.

[0243] In addition, as the conductor 156 and the conductor 160, a conductor that can be used for the conductor 505 or the conductor 560 can be used. For example, as the conductor 156, titanium nitride deposited by the ALD method can be used. In addition, as the conductor 160a, titanium nitride deposited by the ALD method can be used, and as the conductor 160b, tungsten deposited by the CVD method can be used. In addition, when the adhesion between tungsten and the insulator 153 is sufficiently high, a single layer film of tungsten deposited by the CVD method can also be used as the conductor 160.

[0244] As the insulator 153, an insulator composed of a high dielectric constant (high-k) material (a material with a relatively high dielectric constant) is preferably used. For example, as an insulator composed of a high dielectric constant material, an oxide, an oxynitride, an oxynitride or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium and gallium can be used. In addition, the above-mentioned oxide, oxynitride, oxynitride or nitride may also contain silicon. In addition, an insulating layer composed of the above-mentioned materials may also be stacked.

[0245] For example, as an insulator composed of a high dielectric constant material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, an oxynitride containing hafnium and zirconium, etc. can be used. By using such a high dielectric constant material, the thickness of the insulator 153 can be increased to a degree that can suppress leakage current, and the electrostatic capacitance of the capacitor element C can be fully ensured.

[0246] In addition, it is preferred to stack an insulating layer composed of the above-mentioned materials, and it is preferred to use a laminated structure of a high dielectric constant material and a material whose insulation tolerance is higher than that of the high dielectric constant material. For example, as an insulator 153, an insulating film stacked with zirconium oxide, aluminum oxide and zirconium oxide can be used. In addition, for example, an insulating film stacked with zirconium oxide, aluminum oxide, zirconium oxide and aluminum oxide can be used. In addition, for example, an insulating film stacked with hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide and aluminum oxide can be used. By stacking an insulator with relatively high insulation tolerance such as aluminum oxide, the insulation tolerance can be improved to suppress the electrostatic destruction of the capacitor element C.

[0247] Fig.14 An example of a cross-sectional structure when a circuit structure of a memory cell using NOSRAM is shown. Fig.14 Too Fig.12 In addition, Fig.15A An example of a cross-sectional structure of the element layer 700[k] is shown. Fig. 15B yes Fig.15A Equivalent circuit diagram of .

[0248] Fig.14 and Fig.15A The illustrated memory cell MC includes a transistor M1, a transistor M2, and a transistor M3 on an insulator 514. In addition, a conductor 215 is provided on the insulator 514. The conductor 215 can be formed simultaneously with the conductor 505 using the same material and the same process.

[0249] also, Fig.14 and Fig.15A The transistor M2 and the transistor M3 shown in the figure share an island-shaped metal oxide 531. In other words, a portion of the island-shaped metal oxide 531 is used as a channel formation region of the transistor M2, and another portion is used as a channel formation region of the transistor M3. In addition, the source of the transistor M2 and the drain of the transistor M3 or the drain of the transistor M2 and the source of the transistor M3 are shared. Therefore, compared with the case where the transistor M2 and the transistor M3 are provided separately, the occupied area of ​​the transistor is small.

[0250] In addition, Fig.14 and Fig.15A In the illustrated memory cell MC, an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287. Furthermore, an insulator 514 of the element layer 700[k+1] is provided on the insulator 287 and the conductor 161.

[0251] exist Fig.14 and Fig.15A In the embodiment, the conductor 215 of the element layer 700[k+1] is used as one terminal of the capacitor C, the insulator 514 of the element layer 700[k+1] is used as a dielectric of the capacitor C, and the conductor 161 is used as the other terminal of the capacitor C. In addition, the other of the source and the drain of the transistor M1 is electrically connected to the conductor 161 through a contact plug, and the gate of the transistor M2 is electrically connected to the conductor 161 through another contact plug.

[0252] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0253] (Implementation method 5) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In addition, in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0254] [OS Transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 Above. Note that, in the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0255] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0256] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0257] In addition, in an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, when V OWhen the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor may have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0258] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0259] In addition, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the appearance of the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0260] Note that the short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0261] In addition, as an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0262] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region in OS transistors and the characteristic length between the drain region and the channel formation region are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with short channel lengths, OS transistors are more suitable than Si transistors.

[0263] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less (junctionless) transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0264] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm because of the short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with short channel lengths. Note that the gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is the width of the bottom surface of the gate electrode in the top view of the transistor.

[0265] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0266] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a short channel length.

[0267] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0268] (Implementation 6) In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0269] [Electronic components] Fig.16A A perspective view of a substrate (circuit board 704 ) on which electronic components 709 are mounted is shown. Fig.16A The electronic component 709 shown includes a semiconductor device 710 within a mold 711. Fig.16A 709 is partially omitted to show the inside. The electronic component 709 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 709 is mounted on the printed circuit board 702, for example. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, the circuit board 704 is completed.

[0270] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can be a monolithic stacked structure. In the monolithic stacked structure, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0271] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to technologies using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0272] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays adopt a monolithic stacked structure, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Note that bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. In addition, when Si transistors are used in the storage layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0273] In addition, the semiconductor device 710 may be referred to as a bare chip. Note that in this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip, and cutting it into rectangular small pieces. In addition, as semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon chip.

[0274] then, Fig. 16B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0275] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0276] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0277] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon plug board, TSV can also be used as a through electrode.

[0278] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0279] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0280] On the other hand, when a plurality of integrated circuits with different terminal spacings are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal spacing is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal spacing becomes a problem, and it is sometimes difficult to set up more wiring required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0281] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0282] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 16BAn example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0283] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0284] [Electronic equipment] then, Fig.17A A perspective view of electronic device 6500 is shown. Fig.17A The electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device 6509, and the like.

[0285] Fig. 17B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. In addition, the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 6611, the control device 6616, etc. In addition, by using a semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0286] [Mainframe computer] then, Fig. 17CA perspective view of a mainframe computer 5600 is shown. Fig. 17C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0287] Computer 5620 may have, for example, Fig.17D The structure of the stereogram is shown. Fig.17D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, all of which are connected to the motherboard 5630.

[0288] Fig.17E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.17E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0289] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0290] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, etc. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0291] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0292] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0293] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 709 can be used.

[0294] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0295] [Space Equipment] The semiconductor device of one embodiment of the present invention can be applied to space equipment such as equipment for processing and storing information.

[0296] A semiconductor device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space.

[0297] exist Fig.18 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.18 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0298] In addition, although Fig.18Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0299] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0300] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0301] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0302] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. In addition, it is preferable to use a semiconductor device of one embodiment of the present invention for the control device 6807. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change less. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0303] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0304] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0305] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0306] [Data Center] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0307] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the size of cooling equipment. As a result, it is possible to save space in the data center.

[0308] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0309] Fig.19 A storage system that may be used in a data center is shown. Fig.19 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). In the accompanying drawings, the host 7001 and the storage 7003 are connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0310] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0311] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the storage and output of data.

[0312] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0313] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0314] Note that by using a semiconductor device of one embodiment of the present invention for one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0315] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0316] <Notes on the Descriptions in This Manual, etc.> Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0317] The structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0318] In addition, the content (or part thereof) described in a certain embodiment may be applied, combined or replaced with other content (or part thereof) described in that embodiment and / or content (or part thereof) described in one or more other embodiments.

[0319] Note that the contents described in the embodiments refer to the contents described using various drawings in each embodiment or the contents described using the articles described in the specification.

[0320] In addition, more figures may be formed by combining a drawing (or part thereof) shown in a certain embodiment with other parts of the drawing, other drawings (or parts thereof) shown in the embodiment, and / or drawings (or parts thereof) shown in one or more other embodiments.

[0321] In this specification, etc., constituent elements are classified according to function and are represented as independent blocks in a block diagram. However, it is difficult to classify constituent elements according to function in actual circuits, etc., and sometimes one circuit involves multiple functions or multiple circuits involve one function. Therefore, the division of blocks in the block diagram is not limited to the constituent elements described in the specification, but can be appropriately changed according to the situation.

[0322] In addition, in the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. Note that the drawings show arbitrary sizes for the sake of clarity and are not limited to the shapes or values ​​shown in the drawings. For example, it may include uneven signals, voltages or currents caused by noise or timing deviations.

[0323] In this specification, etc., when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (or the first electrode or the first terminal) and "the other of the source and the drain" (or the second electrode or the second terminal) are used. This is because the source and the drain of a transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of a transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode, etc., depending on the situation.

[0324] In addition, in this specification, etc., "electrode" or "wiring" does not limit its constituent elements in terms of function. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wiring" are formed as one.

[0325] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference with the reference potential. For example, when the reference potential is the ground voltage (ground voltage), voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential supplied to the wiring, etc. sometimes changes according to the reference potential.

[0326] In this specification, the words "film" and "layer" may be interchanged depending on the situation or state. For example, "conductive layer" may be interchanged with "conductive film". Also, "insulating film" may be interchanged with "insulating layer".

[0327] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0328] In this specification, etc., for example, the channel length refers to the distance between the source and the drain in the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) overlaps with the gate or in the area where the channel is formed in a top view of the transistor.

[0329] In this specification, etc., for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) overlaps with the gate electrode or the portion where the source and drain face each other in the region where the channel is formed.

[0330] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit structure or device structure. In addition, a terminal, wiring, etc. may be referred to as a node.

[0331] In this specification, etc., A and B are connected means that A and B are electrically connected. Here, A and B are electrically connected means a connection that can transmit an electric signal between A and B when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between A and B. Note that the case where A and B are electrically connected includes the case where A and B are directly connected. Here, A and B are directly connected means a connection between A and B that can transmit an electric signal through wiring (or electrodes) etc. without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit. [Explanation of symbols]

[0332] 10: semiconductor device, 20: base die, 21: power circuit, 30_1: die, 30_2: die, 30_3: die, 30: die, 31: power circuit, 32: functional circuit, 33: amplifier circuit, 34: transistor, 40: element layer, 41A: through electrode, 41B: through electrode, 41C: through electrode, 41D: through electrode, 42: metal bump, 47: electrode, 48: OS transistor, 49: Si transistor, 50: heat diffusion layer, 52: heat dissipation layer

Claims

1. A semiconductor device comprising: a base die having a first power supply circuit generating a first voltage; a first die having a second power supply circuit that generates a second voltage by being supplied with the first voltage; as well as a second die having a functional circuit that operates by being supplied with the second voltage, The first die and the second die include a first through electrode and a second through electrode, The first die is disposed on the base die, The second die is arranged in a manner of contacting an upper layer or a lower layer of the first die, The base die is electrically connected to the first die through the first through-electrode, Furthermore, the first die and the second die are electrically connected via the second through-electrode.

2. The semiconductor device according to claim 1, The first power supply circuit is a switching regulator.

3. The semiconductor device according to claim 1, The second power supply circuit is a series regulator.

4. The semiconductor device according to claim 1, The functional circuit is a circuit having one or more functions of an operation circuit, a peripheral circuit, a storage circuit and a driving circuit.

5. The semiconductor device according to claim 1, further comprising: Heat dissipation layer, The heat dissipation layer is disposed between the first die and the second die.

6. The semiconductor device according to claim 1, The first through-electrode and the second through-electrode arranged on different bare chips are electrically connected via a metal bump.

7. The semiconductor device according to claim 1, wherein the second die includes a layer having a transistor including an oxide semiconductor in a channel formation region, And the layers having transistors are arranged in a stacked manner.

8. The semiconductor device according to claim 7, The oxide semiconductor includes In, Ga, and Zn.

9. A semiconductor device comprising: a base die having a first power supply circuit generating a first voltage; a first die having a second power supply circuit that generates a second voltage by being supplied with the first voltage; as well as a second die and a third die having a functional circuit that operates by being supplied with the second voltage, The first die, the second die and the third die include a first through electrode and a second through electrode. The first die is disposed on the base die, The second die is arranged in contact with the lower layer of the first die, The third die is arranged in contact with the upper layer of the first die, The base die is electrically connected to the first die through the first through-electrode, Furthermore, the first die, the second die, and the third die are electrically connected via the second through-electrode.

10. The semiconductor device according to claim 9, The first power supply circuit is a switching regulator.

11. The semiconductor device according to claim 9, The second power supply circuit is a series regulator.

12. The semiconductor device according to claim 9, The functional circuit is a circuit having one or more functions of an operation circuit, a peripheral circuit, a storage circuit and a driving circuit.

13. The semiconductor device according to claim 9, further comprising: Heat dissipation layer, The heat dissipation layer is disposed between the first die and the second die and between the first die and the third die.

14. The semiconductor device according to claim 9, The first through-electrode and the second through-electrode arranged on different bare chips are electrically connected via a metal bump.

15. The semiconductor device according to claim 9, wherein the second die and the third die include a layer having a transistor including an oxide semiconductor in a channel formation region, And the layers having transistors are arranged in a stacked manner.

16. The semiconductor device according to claim 15, The oxide semiconductor includes In, Ga, and Zn.

Images