Substrate processing technology based on exposure and development technology
Through the substrate processing technology based on the exposure development process, the problems of reduced pitch of flip chip bumps and poor coplanarity are solved, and higher integration and product performance are achieved. By accurately controlling the exposure and development conditions, the precise formation of the The pattern and the unexposed part were removed, solving the problem of restriction of steel mesh openings in the printing process.
Patent Information
- Application Number
- CN202411397619.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-03
AI Technical Summary
In the prior art, the pitch of the flip chip bumps is difficult to further reduce, and the coplanarity of the tin column after reflow soldering is poor, which limits the improvement of integration.
The substrate processing technology is adopted based on the exposure development process, including preparing silicon wafer substrates, coating photoresist, baking, aligning exposure, development, post-baking and photoresist peeling, and by precisely controlling the exposure time and development conditions, it forms Accurate patterning and removing unexposed parts solve the problem of restricting steel mesh openings in the printing process.
Achieve smaller line width and higher product yields, the bump structure spacing is reduced to 15μm, and the bottom end spacing is reduced to 10μm, improving product performance and reliability, ensuring the fineness and high density of the through holes. This avoids the problem of excessive development or insufficient development.
Smart Images
Figure CN119247704A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor processing, and in particular to a substrate processing technology based on an exposure and development process. Background Art
[0002] A flip chip is a pinless structure that generally contains a circuit unit and is designed to be electrically and mechanically connected to a circuit through an appropriate number of solder balls (covered by a conductive adhesive) located on its surface. At present, with the increase in integration, the pitch of the bumps of a flip chip is decreasing. In the prior art, the corresponding steel mesh is first processed according to the position and size of the window openings in the top layer of green oil on the substrate. The steel mesh is attached to the surface of the green oil, and the solder is pressed into the mesh holes using a scraper. The steel mesh is separated from the substrate, and the solder is reflowed. Finally, a flattening device is used to flatten the solder balls and adjust their coplanarity. However, due to the use of a printing process, the openings in the steel mesh limit the further reduction of the bump distance, and the coplanarity of the tin pillars is poor after reflow.
[0003] Therefore, a substrate processing technology based on exposure and development process is needed to solve this problem. Summary of the invention
[0004] The purpose of the present invention is to provide a substrate processing technology based on an exposure and development process, aiming to solve the problems raised in the background technology.
[0005] To achieve the above object, the present invention provides the following technical solutions:
[0006] A substrate processing process based on an exposure and development process comprises the following steps: S1, preparing a substrate; S2, applying photoresist; S3, baking a photoresist film; S4, aligning and exposing the photoresist film; S5, developing the substrate; S6, performing a post-baking operation; S7, pattern transfer; and S8, stripping the photoresist.
[0007] Preferably, the substrate material in step S1 is a silicon wafer, and the size of the silicon wafer is a large size of 12 inches. The particulate contaminants on the surface of the silicon wafer substrate are cleaned by mechanical cleaning, and then the moisture on the surface of the silicon wafer substrate is baked off, and finally the silicon wafer substrate is placed in HMDS steam under high temperature and high pressure for hydrophobic treatment.
[0008] Preferably, in step S2, the silicon wafer is first adsorbed on a rotatable worktable by negative pressure, a small amount of photoresist is dropped onto the surface of the silicon wafer substrate, and the silicon wafer substrate is rotated at high speed. The centrifugal force causes the photoresist to diffuse from the center to the periphery. The friction caused by the viscosity of the photoresist will to a certain extent hinder the photoresist from completely diffusing outward. As the solvent evaporates, the viscosity of the photoresist will increase sharply and eventually turn into a solid, forming a layer of photoresist film on the surface of the silicon wafer substrate.
[0009] Preferably, in step S3, the photoresist film is baked; in step S4, the alignment operation of the lithography equipment is performed before exposure, firstly, an identifiable marker is etched at the edge position or other specific position of the silicon wafer substrate, and then the work stage moves the marker on the silicon wafer substrate to the field of view of the alignment lens, the alignment lens recognizes the marker by taking a picture, and then the coordinate system of the silicon wafer substrate and the coordinate system of the exposure system are aligned by an algorithm, and then the spatial position of the silicon wafer substrate can be identified by the displacement of the work stage.
[0010] Preferably, the exposure operation adopts a projection photolithography machine for exposure, and the mask and the silicon wafer substrate of the scanning projection system move simultaneously. When passing through a slit, a beam of light on the mask is projected onto the silicon wafer substrate. The amount of light during the exposure process is between 200 and 250, and a larger exposure amount and a shorter exposure time are adopted. The size of the mask and the target pattern in the exposure system is 1:1.
[0011] Preferably, in step S5, the silicon wafer substrate is developed by placing the exposed silicon wafer substrate in a large beaker filled with developer and stirring it, and developing is performed within 40%-60% of the total length of the development section.
[0012] Preferably, in the step S6, the photoresist on the silicon wafer substrate is post-baked at a high temperature (120-150° C.); in the step S7, the developed photoresist is placed in a high vacuum environment and then an etching gas is injected.
[0013] Preferably, the photoresist stripping adopts plasma stripping and degumming. First, the silicon wafer substrate coated with photoresist is placed in a plasma reaction chamber. According to the characteristics of the photoresist to be removed, argon gas is introduced into the reaction chamber, and the gas is ionized by radio frequency power to form plasma for degumming. Then, the silicon wafer substrate is cleaned to complete the substrate processing.
[0014] Beneficial effects: The novel exposure and development process can obtain a higher product yield under the condition of obtaining a smaller line width. Through this process, the upper end spacing between the bump structures can be reduced to 15μm, and the bottom end spacing can be reduced to 10μm, which helps to improve the performance and reliability of the product; the light intensity in the novel exposure process is between 200 and 250, and a larger exposure intensity and a shorter exposure time are used to reduce the refraction and diffraction of light, so that fine pitch and high-density interconnected vias can be manufactured. By accurately controlling the exposure time, the photoresist is ensured to be correctly exposed, so that an accurate pattern is formed during the development process; the novel development process can avoid over-development or under-development by reasonably controlling the development time, especially by developing at an appropriate position (development point) in the development section, so as to ensure the coplanarity of the bumps and the circuit; after exposure, the photoresist is treated with a developer to remove the unexposed part, leaving the exposed part to form a pattern, and the size and shape of the pattern are accurately controlled by adjusting the concentration, temperature and development time of the developer, so as to effectively solve the problem that the opening of the steel mesh in the printing process limits the reduction of the bump distance and the coplanarity difference. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the implementation of the present invention or the technical solution in the prior art, the following briefly introduces the drawings required for the implementation or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.
[0016] Figure 1 It is a schematic diagram of the overall process flow of the present invention. DETAILED DESCRIPTION
[0017] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are only part of the embodiments of the invention, rather than all of the embodiments. In the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Based on the embodiments in the invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the invention.
[0018] It should be noted that if the embodiments of the invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0019] In addition, "multiple" means more than two. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection required by the invention.
[0020] Please refer to the instruction manual Figure 1 A substrate processing process based on an exposure and development process includes the following steps: S1, preparing a substrate; S2, applying photoresist; S3, baking a photoresist film; S4, aligning and exposing the photoresist film; S5, developing the substrate; S6, performing a post-baking operation; S7, pattern transfer; S8, photoresist stripping.
[0021] Furthermore, the substrate material in step S1 is silicon wafer, and the size of the silicon wafer is a large size of 12 inches. The larger the diameter of the silicon wafer substrate, the higher the utilization rate of the silicon material and the lower the cost. The particulate contaminants on the surface of the silicon wafer substrate are cleaned by mechanical cleaning. The adsorption capacity between the surface of the silicon wafer substrate and the photoresist and the contaminants on the surface of the silicon wafer substrate will cause defects in the photoresist film, thereby affecting the transfer process of the pattern. Subsequently, the moisture on the surface of the silicon wafer substrate is baked and removed. Dehydration baking can also improve the adsorption capacity of the photoresist and the surface of the silicon wafer substrate to a certain extent. Finally, the silicon wafer substrate is placed in HMDS steam under high temperature and high pressure for hydrophobic treatment. The higher temperature allows the groups on the surface of the silicon wafer substrate to react better with HMDS, generating organic functional groups on the surface, thereby achieving the purpose of hydrophobicity.
[0022] Furthermore, in step S2, the silicon wafer is first adsorbed on a rotatable worktable by negative pressure, a small amount of photoresist is dropped onto the surface of the silicon wafer substrate, and the silicon wafer substrate is rotated at high speed. The centrifugal force causes the photoresist to diffuse from the center to the periphery. The friction caused by the viscosity of the photoresist will to a certain extent hinder the photoresist from completely diffusing outward. As the solvent evaporates, the viscosity of the photoresist will increase sharply and eventually turn into a solid, forming a layer of photoresist film on the surface of the silicon wafer substrate.
[0023] Furthermore, in the step S3, the photoresist film is baked, and 20% to 40% of the solvent will remain in the photoresist. By baking the photoresist film, most of the solvent is removed, the film becomes stable at room temperature, the adhesion of the photoresist film is improved, and a sufficiently small amount of residual solvent can keep the film stable in the subsequent photolithography process; in the step S4, the alignment operation of the photolithography equipment is performed before exposure. First, an identifiable marker is etched at the edge position or other specific position of the silicon wafer substrate, and then the worktable moves the marker on the silicon wafer substrate to the field of view of the alignment lens. The alignment lens recognizes the marker by taking a picture, and then the coordinate system of the silicon wafer substrate and the coordinate system of the exposure system are aligned through an algorithm. Then, the spatial position of the silicon wafer substrate can be identified by the displacement of the worktable, so as to achieve the effect of exposing a specified pattern at a specified position and dynamically adjust the random error.
[0024] Furthermore, the exposure operation adopts a projection photolithography machine for exposure, and the scanning projection system mask and the silicon wafer substrate move simultaneously. When passing through a slit, a beam of light on the mask is projected onto the silicon wafer substrate. The amount of light during the exposure process is between 200 and 250, and a larger exposure amount and a shorter exposure time are used. The size of the mask and the target pattern in the exposure system is 1:1. Through the irradiation of the laser, some chemical bonds of the photoresist material will be broken or bonds that did not originally exist will be generated. This change will cause a great change in the solubility of the photoresist in the developer, so that the exposed area and the unexposed area can be distinguished by the developer.
[0025] Furthermore, in step S5, the silicon wafer substrate is developed, the exposed silicon wafer substrate is placed in a large beaker filled with developer and stirred, and development is performed within 40%-60% of the total length of the development section. As the stirring time increases, the area with higher solubility will gradually disappear, exposing the silicon wafer substrate underneath, while the photoresist in the area with lower solubility will be retained in large quantities. The retained photoresist plays a role in protecting the silicon wafer substrate. Development is performed at an appropriate position (development point) in the development section to avoid over-development or under-development, thereby ensuring the coplanarity of the bumps and the circuits.
[0026] Furthermore, in the step S6, the photoresist on the silicon wafer substrate is post-baked at a high temperature (120-150°C); in the step S7, the developed photoresist is placed in a high vacuum environment, and then an etching gas is injected. The part of the substrate not protected by the photoresist will react with the etchant, and a pattern will be etched on the surface, while the area covered by the photoresist will not be etched.
[0027] Furthermore, the photoresist stripping adopts plasma stripping and degumming. First, the silicon wafer substrate coated with photoresist is placed in a plasma reaction chamber. According to the characteristics of the photoresist to be removed, argon gas is introduced into the reaction chamber, and the gas is ionized by radio frequency power to form plasma for degumming. Then, the silicon wafer substrate is cleaned to complete the substrate processing. Under the action of plasma, the photoresist molecules are degraded and the generated small molecule gas is extracted, finally realizing the removal of the photoresist, and the subsequent flip chip processing steps are performed on the substrate.
[0028] First, a silicon wafer is used to make a substrate, and the particle contaminants on the surface of the silicon wafer substrate are cleaned by mechanical cleaning. Then, the moisture on the surface of the silicon wafer substrate is baked off. Finally, the silicon wafer substrate is placed in HMDS steam under high temperature and high pressure for hydrophobic treatment to prevent defects in the photoresist film from affecting the transfer process of the pattern and to improve the adsorption capacity of the photoresist and the surface of the silicon wafer substrate. Then, a small amount of photoresist is dropped onto the surface of the silicon wafer substrate, and the silicon wafer substrate is rotated at high speed to form a layer of photoresist film on the surface of the silicon wafer substrate. The photoresist film is baked, and a small amount of residual solvent can keep the film stable in the subsequent photolithography process. Before exposure, the photolithography equipment is aligned to achieve the effect of exposing a specified pattern at a specified position. The random error is dynamically adjusted, the light intensity during exposure is controlled between 200 and 250, and a larger exposure amount and a shorter exposure time are used. The mask and the target pattern in the exposure system The size is 1:1 to reduce the refraction and diffraction of light, and can produce fine pitch and high-density interconnected vias. By accurately controlling the exposure time, the photoresist is ensured to be correctly exposed, so as to form an accurate pattern in the development process, and then the silicon wafer substrate is developed. The development is carried out within 40%-60% (development point) of the total length of the development section, and the development is carried out at the appropriate position (development point) of the development section. Over-development or under-development can be avoided, thereby ensuring the coplanarity of the bumps and the lines. Finally, the developed photoresist is placed in a high vacuum environment, and then the etching gas is injected and then the plasma is used for stripping and degumming. The photoresist molecules are degraded, and the generated small molecule gas is extracted, and finally the photoresist is removed, and the subsequent flip chip processing steps are carried out on the substrate. This new type effectively solves the problem of the reduction of the bump distance and the poor coplanarity caused by the opening of the steel mesh in the printing process by accurately controlling the exposure time and development conditions.
[0029] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
[0030] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0031] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A substrate processing process based on an exposure and development process, characterized in that: The method comprises the following steps: S1, preparing a substrate; S2, applying photoresist; S3, baking the photoresist film; S4, aligning and exposing the photoresist film; S5, developing the substrate; S6, performing a post-baking operation; S7, pattern transfer; S8. Photoresist stripping.
2. The substrate processing technology based on exposure and development process according to claim 1, characterized in that: The substrate material in step S1 is a silicon wafer, and the size of the silicon wafer is a large size of 12 inches. The particulate contaminants on the surface of the silicon wafer substrate are cleaned by mechanical cleaning, and then the moisture on the surface of the silicon wafer substrate is baked off. Finally, the silicon wafer substrate is placed in HMDS steam under high temperature and high pressure for hydrophobic treatment.
3. The substrate processing technology based on exposure and development process according to claim 1, characterized in that: In step S2, the silicon wafer is first adsorbed on a rotatable worktable by negative pressure, a small amount of photoresist is dropped onto the surface of the silicon wafer substrate, and the silicon wafer substrate is rotated at high speed. The centrifugal force causes the photoresist to diffuse from the center to the periphery. The friction caused by the viscosity of the photoresist will hinder the photoresist from completely diffusing outward to a certain extent. As the solvent evaporates, the viscosity of the photoresist will increase sharply and eventually turn into a solid, forming a layer of photoresist film on the surface of the silicon wafer substrate.
4. The substrate processing technology based on exposure and development process according to claim 1, characterized in that: In the step S3, the photoresist film is baked; in the step S4, the alignment operation of the photolithography equipment is performed before exposure. First, a recognizable marker is etched at the edge position or other specific position of the silicon wafer substrate, and then the worktable moves the marker on the silicon wafer substrate to the field of view of the alignment lens. The alignment lens recognizes the marker by taking a picture, and then the coordinate system of the silicon wafer substrate and the coordinate system of the exposure system are aligned through an algorithm, and then the spatial position of the silicon wafer substrate can be identified through the displacement of the worktable.
5. The substrate processing technology based on exposure and development process according to claim 4, characterized in that: The exposure operation adopts a projection photolithography machine for exposure. The mask and the silicon wafer substrate of the scanning projection system move simultaneously. When passing through a slit, a beam of light on the mask is projected onto the silicon wafer substrate. The amount of light during the exposure process is between 200 and 250, and a larger exposure amount and a shorter exposure time are adopted. The size of the mask and the target pattern in the exposure system is 1:
1.
6. The substrate processing technology based on exposure and development process according to claim 1, characterized in that: In the step S5, the silicon wafer substrate is developed by placing the exposed silicon wafer substrate in a large beaker filled with developer and stirring it, and developing is performed within 40% to 60% of the total length of the development section.
7. The substrate processing technology based on exposure and development process according to claim 1, characterized in that: In the step S6, the photoresist on the silicon wafer substrate is post-baked at a high temperature (120-150° C.); in the step S7, the developed photoresist is placed in a high vacuum environment and then an etching gas is injected.
8. The substrate processing technology based on exposure and development process according to claim 1, characterized in that: The photoresist stripping adopts plasma stripping to remove the photoresist. First, the silicon wafer substrate coated with photoresist is placed in a plasma reaction chamber. According to the characteristics of the photoresist to be removed, argon gas is introduced into the reaction chamber, and the gas is ionized by radio frequency power to form plasma for stripping. Then, the silicon wafer substrate is cleaned to complete the substrate processing.