Operation method and device, equipment and medium

Abstract

The invention provides an operation method and device, equipment and a medium, and relates to the technical field of artificial intelligence, in particular to the technical field of chips. The implementation scheme is as follows: in response to the need of executing inverse quantization operation on a first matrix based on a first quantization coefficient and a first offset, and executing matrix multiplication operation on the quantized first matrix and a second matrix with smaller data volume than the first matrix, the arithmetic logic unit performs a first operation of: operating a sum of a plurality of data elements of each row of the second matrix; using the matrix operation unit to perform the following second operation: determining a first intermediate result, wherein the first intermediate result indicates a product of a matrix multiplication result of the first matrix and the second matrix and the first quantization coefficient; performing a multiplication operation based on the first offset and the sum of the plurality of rows of the second matrix to obtain a second intermediate result; and executing accumulation operation based on the first intermediate result and the second intermediate result to obtain a target operation result.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, in particular to the field of chip technology, and specifically to a computing method, device, electronic device, computer-readable storage medium, and computer program product. Background Art

[0002] Artificial intelligence is a discipline that studies how to use computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It includes both hardware-level and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies mainly include computer vision technology, speech recognition technology, natural language processing technology, as well as machine learning / deep learning, big data processing technology, knowledge graph technology, and other major directions.

[0003] With the development of artificial intelligence technology, more and more applications based on artificial intelligence technology have achieved results far exceeding traditional algorithms. Deep learning is a data-intensive and computationally intensive algorithm, and it is also an algorithm that develops rapidly through iteration. In deep learning algorithms, in order to improve the efficiency of neural network models in processing complex tasks, multiple types of operations need to be applied, such as quantizing data elements based on inverse quantization operations.

[0004] The methods described in this section are not necessarily methods that have been previously conceived or employed. Unless otherwise indicated, it should not be assumed that any method described in this section is considered to be prior art simply because it is included in this section. Similarly, unless otherwise indicated, the issues mentioned in this section should not be considered to have been recognized in any prior art. Summary of the invention

[0005] The present disclosure provides a computing method, an apparatus, an electronic device, a computer-readable storage medium, and a computer program product.

[0006] According to one aspect of the present disclosure, there is provided an operation method implemented by an operation device, wherein the operation device includes a matrix operation unit and an arithmetic logic unit, and the method includes: in response to receiving a target operation request to perform an inverse quantization operation on a first matrix based on a first quantization coefficient and a first offset and to perform a matrix multiplication operation on the quantized first matrix and a second matrix, wherein the data amount of the first matrix is ​​greater than the data amount of the second matrix, using the arithmetic logic unit to perform a first operation, wherein the first operation includes: for each row of the second matrix, calculating the sum of multiple data elements of the row; using the matrix operation unit to perform a second operation, wherein the second operation includes: determining a first intermediate result based on the first quantization coefficient, the first matrix and the second matrix, wherein the first intermediate result indicates the product of the matrix multiplication result of the first matrix and the second matrix and the first quantization coefficient; performing a multiplication operation based on the first offset and the sum of multiple rows of the second matrix to obtain a second intermediate result; and performing an accumulation operation based on the first intermediate result and the second intermediate result to obtain a target operation result.

[0007] According to one aspect of the present disclosure, an operation device is provided, comprising: a matrix operation unit; an arithmetic logic unit; a first operation unit, configured to respond to receiving a target operation request to perform an inverse quantization operation on a first matrix based on a first quantization coefficient and a first offset and to perform a matrix multiplication operation on the quantized first matrix and a second matrix, wherein the data amount of the first matrix is ​​greater than the data amount of the second matrix, and to use the arithmetic logic unit to perform a first operation, wherein the arithmetic logic unit is configured to: for each row of the second matrix, calculate the sum of multiple data elements of the row; a second operation unit, configured to use the matrix operation unit to perform a second operation, wherein the matrix operation unit is configured to: determine a first intermediate result based on the first quantization coefficient, the first matrix and the second matrix, wherein the first intermediate result indicates the product of the matrix multiplication result of the first matrix and the second matrix and the first quantization coefficient; a third operation unit, configured to perform a multiplication operation based on the first offset and the sum of multiple rows of the second matrix to obtain a second intermediate result; and a fourth operation unit, configured to perform an accumulation operation based on the first intermediate result and the second intermediate result to obtain a target operation result.

[0008] According to one aspect of the present disclosure, a chip is provided, comprising the computing device as described above.

[0009] According to one aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the above-mentioned operation method.

[0010] According to one aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the above-mentioned operation method.

[0011] According to one aspect of the present disclosure, a computer program product is provided, including a computer program, wherein the computer program can implement the above-mentioned operation method when executed by a processor.

[0012] According to one or more embodiments of the present disclosure, the operational efficiency of performing an inverse quantization operation including an offset and a matrix multiplication operation on a matrix may be improved.

[0013] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0015] Figure 1 A schematic diagram showing an exemplary system in which the various methods described herein may be implemented according to an exemplary embodiment of the present disclosure;

[0016] Figure 2 A flowchart of an operation method according to an exemplary embodiment of the present disclosure is shown;

[0017] Figure 3 A structural block diagram of a computing device according to an exemplary embodiment of the present disclosure is shown;

[0018] Figure 4 A structural block diagram of a computing device according to an exemplary embodiment of the present disclosure is shown;

[0019] Figure 5 A structural block diagram of an exemplary electronic device that can be used to implement the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0020] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0021] In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

[0022] The terms used in the description of various examples in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. In addition, the term "and / or" used in this disclosure covers any one of the listed items and all possible combinations.

[0023] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0024] Figure 1 FIG. 1 is a schematic diagram of an exemplary system 100 in which various methods and apparatuses described herein may be implemented according to an embodiment of the present disclosure. Figure 1 , the system 100 includes one or more client devices 101, 102, 103, 104, 105, and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105, and 106 may be configured to execute one or more applications.

[0025] In an embodiment of the present disclosure, the server 120 may run one or more services or software applications that enable the execution of the computing method.

[0026] In some embodiments, server 120 may also provide other services or software applications, which may include non-virtualized environments and virtualized environments. In some embodiments, these services may be provided as web-based services or cloud services, such as provided to users of client devices 101, 102, 103, 104, 105, and / or 106 under a software as a service (SaaS) model.

[0027] exist Figure 1 In the configuration shown, the server 120 may include one or more components that implement the functions performed by the server 120. These components may include software components, hardware components, or a combination thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 may in turn utilize one or more client applications to interact with the server 120 to utilize the services provided by these components. It should be understood that a variety of different system configurations are possible, which may differ from the system 100. Therefore, Figure 1 is one example of a system for implementing the various methods described herein and is not intended to be limiting.

[0028] The user may use client devices 101, 102, 103, 104, 105 and / or 106 to send a computation request or data to be computed. The client device may provide an interface that enables the user of the client device to interact with the client device. The client device may also output information to the user via the interface. Figure 1 Only six client devices are depicted, but one skilled in the art will appreciate that the present disclosure may support any number of client devices.

[0029] Client devices 101, 102, 103, 104, 105 and / or 106 may include various categories of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptop computers), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, game systems, thin clients, various messaging devices, sensors or other sensing devices, etc. These computer devices may run various categories and versions of software applications and operating systems, such as MICROSOFT Windows, APPLE iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as GOOGLE Chrome OS); or include various mobile operating systems, such as MICROSOFT Windows Mobile OS, iOS, Windows Phone, Android. Portable handheld devices may include cellular phones, smart phones, tablet computers, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Game systems may include various handheld game devices, Internet-enabled game devices, etc. The client device is capable of executing a variety of different applications, such as various Internet-related applications, communication applications (eg, email applications), short message service (SMS) applications, and may use various communication protocols.

[0030] The network 110 may be any type of network known to those skilled in the art that may support data communications using any of a variety of available protocols, including but not limited to TCP / IP, SNA, IPX, etc. By way of example only, one or more networks 110 may be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, WIFI), and / or any combination of these and / or other networks.

[0031] Server 120 may include one or more general purpose computers, dedicated server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 120 may include one or more virtual machines running virtual operating systems, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that may be virtualized to maintain a server's virtual storage device). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0032] The computing units in the server 120 may run one or more operating systems including any of the above operating systems and any commercially available server operating systems. The server 120 may also run any of a variety of additional server applications and / or middle-tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0033] In some implementations, server 120 may include one or more applications to analyze and consolidate data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0034] In some embodiments, the server 120 may be a server of a distributed system, or a server combined with a blockchain. The server 120 may also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in a cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.

[0035] The system 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. The databases 130 may reside in various locations. For example, the database used by the server 120 may be local to the server 120, or may be remote from the server 120 and may communicate with the server 120 via a network-based or dedicated connection. The databases 130 may be of different categories. In some embodiments, the databases used by the server 120 may be, for example, relational databases. One or more of these databases may store, update, and retrieve data to and from the databases in response to commands.

[0036] In some embodiments, one or more of the databases 130 may also be used by applications to store application data. The databases used by the applications may be different categories of databases, such as a key-value store, an object store, or a conventional store backed by a file system.

[0037] Figure 1 The system 100 may be configured and operated in various ways to enable the application of various methods and apparatuses described in the present disclosure.

[0038] During matrix operations, in order to reduce the demand for corresponding hardware computing resources and storage resources for each data element in the matrix, the matrix can be quantized to reduce the amount of data for matrix operations. For example, high-precision floating-point numbers can be quantized into integers to reduce the difficulty of operations and save hardware resources.

[0039] The data quantization process can be implemented based on a linear transformation operation. For example, when symmetric quantization is performed on the data to be quantized, the quantization operation can be implemented based on the following formula:

[0040]

[0041] In the formula, x is the original data element, q is the quantized data element, scale is the quantization coefficient, and round indicates the rounding operation rule. By performing division operations based on x and scale and performing rounding operations, the data quantization result can be obtained, and the value range of the original data element is mapped to the quantized target value range with zero as the center. In this case, when it is necessary to perform an inverse quantization operation on q, q and scale can be used to restore it to the original data element x.

[0042] In order to more accurately control the distribution of quantized data, an offset bias can be introduced based on the quantization coefficient. In this case, the quantization operation can be implemented based on the following formula:

[0043]

[0044] In this case, when it is necessary to perform an inverse quantization operation on q, the following linear transformation is required based on the quantization coefficient scale and the offset bias:

[0045] x'=q×scale+bias

[0046] Generally speaking, the processing of matrix data involves a large number of matrix multiplication operations. When the matrix corresponding to the multiplication operation involves an asymmetric dequantization operation, the offset in the asymmetric dequantization operation will bring a lot of overhead, occupy more hardware resources, and affect the computing efficiency.

[0047] Based on this, the present disclosure provides an operation method. When it is necessary to perform an inverse quantization operation and a matrix multiplication operation including an offset on a first matrix, on the basis of obtaining a matrix multiplication result after quantization based on a quantization coefficient by using a matrix operation unit, the calculation amount brought by the offset is split into an arithmetic logic unit. By first summing the row elements of the second matrix and then performing a multiplication operation on the row sum, the number of multiplication operations is reduced, the computational load of the matrix multiplication operation array is reduced, and the operation efficiency is improved.

[0048] Figure 2 FIG. 2 shows a flow chart of a method 200 according to an exemplary embodiment of the present disclosure. In this embodiment, the method 200 is implemented by a computing device, which includes a matrix computing unit and an arithmetic logic unit, such as Figure 2 As shown, the method 200 includes:

[0049] Step S210, in response to receiving a target operation request to perform a dequantization operation on a first matrix based on a first quantization coefficient and a first offset and to perform a matrix multiplication operation on the quantized first matrix and a second matrix, the data amount of the first matrix is ​​greater than the data amount of the second matrix, performing a first operation using the arithmetic logic unit, wherein the first operation includes: for each row of the second matrix, calculating the sum of multiple data elements of the row;

[0050] Step S220, performing a second operation using the matrix operation unit, wherein the second operation includes: determining a first intermediate result based on the first quantization coefficient, the first matrix, and the second matrix, wherein the first intermediate result indicates a product of a matrix multiplication result of the first matrix and the second matrix and the first quantization coefficient;

[0051] Step S230, performing a multiplication operation based on the first offset and a sum of multiple rows of the second matrix to obtain a second intermediate result; and

[0052] Step S240: Perform an accumulation operation based on the first intermediate result and the second intermediate result to obtain a target operation result.

[0053] By applying the above method 200, when it is necessary to perform an inverse quantization operation and a matrix multiplication operation including an offset on the first matrix, on the basis of using the matrix operation unit to obtain the matrix multiplication result after quantization based on the quantization coefficient, the calculation amount brought by the offset is split into the arithmetic logic unit, and the number of multiplication operations is reduced by first summing the row elements of the second matrix and then performing a multiplication operation on the sum of the rows, thereby reducing the computational load of the matrix multiplication operation array and improving the computational efficiency.

[0054] The following will illustrate the computational overhead that can be saved by applying the method 200 by way of example.

[0055] In one example, the size of the first matrix is ​​a×a, and the size of the second matrix is ​​b×a. If the above method 200 is not applied, it is necessary to perform a×a inverse quantization operations on the first matrix, which corresponds to a×a multiplication operations and a×a addition operations. After obtaining the quantized first matrix, it is necessary to perform b×a×a multiplication-accumulation operations in the matrix multiplication operation. It can be understood that the data elements of the multiplication-accumulation operation in this case are the inverse quantized data elements.

[0056] By applying the above method 200, the data elements of the b×a×a times of multiplication and accumulation operations in step S220 are no longer the data elements after dequantization, but the data elements before the dequantization operation. It can be understood that the numerical range or data bit width of the data elements before dequantization is smaller than that of the data elements after dequantization, so that computing resources can be saved. For example, the b×a×a times of floating-point multiplication and accumulation operations may be changed to floating-point and fixed-point multiplication and accumulation operations in this step. On this basis, step S210 involves 2×b×a times of addition operations, and step S230 involves b×a times of multiplication operations. Since the data volume of the first matrix (a×a) is greater than the data volume of the second matrix (b×a), the amount of computing can be saved by applying the above method.

[0057] At the same time, by applying the above method 200, the computational overhead involving the quantization coefficient and the computational overhead involving the offset can be allocated to two hardware operation units, the matrix operation unit and the arithmetic logic unit. The two can perform operations in parallel, thereby improving the operation efficiency by increasing the degree of parallelism.

[0058] Continuing with the above example, by performing the addition operation in step S210 on the second matrix, the sum of a rows in the second matrix can be obtained, and then a vector of size a can be obtained, which is equivalent to obtaining a matrix of b×1. On this basis, in step S230, the offset can be expressed as a matrix of 1×a, and then a second intermediate result of b×a can be obtained by matrix multiplication, which is convenient for superposition operation with the first intermediate result of b×a in step S220.

[0059] It can be understood that the above-mentioned operation method of performing matrix multiplication based on the b×1 matrix and the 1×a matrix is ​​only to more conveniently obtain the second intermediate result of b×a, which can then be superimposed with the first intermediate result. In some examples, step S230 can also use other methods to obtain the second intermediate result of b×a. For example, a multiplication operation can be first performed based on the offset and the sum of a rows in the second matrix, and then the results of the multiplication operation can be arranged based on a preset rule to obtain the second intermediate result of b×a.

[0060] According to some embodiments, method 200 further includes: performing a split operation on the first matrix and the second matrix to obtain a plurality of sub-matrix groups, each sub-matrix group including a first sub-matrix and a second sub-matrix, wherein in step S210, performing the first operation using the arithmetic logic unit includes: in response to determining that the first operation on the first sub-matrix group is completed, while performing the second operation on the first sub-matrix group using the matrix operation unit, performing the first operation on the second sub-matrix group using the arithmetic logic unit. By applying the above method, the original matrix is ​​split into a plurality of sub-matrix groups, and the operations of the matrix operation unit and the operations of the arithmetic logic unit can be interleaved for the split sub-matrix groups, thereby improving the utilization rate of the hardware unit and optimizing the operation efficiency by using the pipeline.

[0061] In some examples, when the first matrix and the second matrix are split into sub-matrix group A, sub-matrix group B, and sub-matrix group C, in this case, the operation corresponding to each sub-matrix group includes at least the step of using an arithmetic logic unit to perform a first operation on the second sub-matrix and the step of using a matrix operation unit to perform a second operation on the first sub-matrix and the second sub-matrix. In this case, when the first operation on sub-matrix group A has been completed in the arithmetic logic unit, that is, when the second operation on sub-matrix group A is performed using the matrix operation unit, the first operation on sub-matrix group B can be performed using the arithmetic logic unit at the same time. By arranging the operation pipelines of sub-matrix group A, sub-matrix group B, and sub-matrix group C using the matrix operation unit and the arithmetic logic unit, the operation time can be saved and the operation efficiency can be improved.

[0062] According to some embodiments, the target operation request is determined in the following manner: in response to receiving a first operation request to perform an inverse quantization operation on a first matrix based on a first quantization coefficient and a first offset, to perform an inverse quantization operation on a third matrix based on a second quantization coefficient and a second offset, and to perform a matrix multiplication operation on the quantized first matrix and the quantized third matrix, and in response to determining that the data amount of the first matrix is ​​greater than the data amount of the third matrix, to perform an inverse quantization operation on the third matrix based on the second quantization coefficient and the second offset to obtain the second matrix; and to determine a target operation request to perform an inverse quantization operation on the first matrix based on the first quantization coefficient and the first offset, and to perform a matrix multiplication operation on the quantized first matrix and the second matrix. Thus, when it is necessary to perform an inverse quantization operation on both matrices and further perform a matrix multiplication operation, the matrix with a smaller data amount can be first inversely quantized, so that the optimized operation method described in method 200 can be specifically applied to the first matrix with a larger data amount, thereby improving the operation efficiency.

[0063] According to some embodiments, the first matrix is ​​a weight matrix of a fully connected layer of a neural network model, and the second matrix is ​​an input matrix of the fully connected layer. Thus, targeted optimization can be performed in the matrix multiplication step involved in the fully connected layer of the neural network model calculation to improve the model calculation efficiency.

[0064] According to some embodiments, the first matrix is ​​an attention weight matrix of the attention network, and the second matrix is ​​a value matrix of the attention network. Thus, targeted optimization can be performed in the matrix multiplication step involved in the attention network to improve the model calculation efficiency.

[0065] In some examples, the above method 200 can be applied to the reasoning calculation of the Transformer model. In this example, the Transformer model includes a fully connected layer and an attention network, and its reasoning calculation process can specifically include the following steps:

[0066] First, the input sequence X needs to be linearly transformed into a query vector Q, a key vector K, and a value vector V:

[0067] Q=X·W Q ,K=X·W K ,V=X·W V

[0068] Where W Q , W K and W V is the weight matrix of the fully connected layer. On this basis, nonlinear activation can be performed based on the result of linear transformation.

[0069] In some examples, a row-by-row quantization method may be applied to the input sequence X, and a channel-by-channel quantization method may be applied to the weight matrix W to improve the quantization effect.

[0070] In this step, the dequantization operations of the input sequence X and the weight matrix W correspond to the following calculation formulas:

[0071] X=scale X *qX+bias X

[0072] W=scale W *qW+bias W

[0073] In the formula, scale X and scale W is the quantization coefficient, qX and qW are the data elements before dequantization, bias X and bias W is the amount of data. In this example, the size of X is B×d_model, and the size of W is d_model×d_model, where B is the size of the data batch and d_model is the hidden layer dimension of the model. Generally speaking, the value of B is much smaller than the value of d_model. In this case, the dequantization calculation can be performed on qX first, and then on qW Q The above method 200 is applied to calculate Q by using the dequantized X. The calculation process can be implemented based on the following formula, for example:

[0074] Q=X·(scale WQ *qW Q )+rowsum(X)·bias WQ

[0075] In the formula, rowsum(X) corresponds to the summation operation performed on each row in the second matrix (X after inverse quantization) in step S221.

[0076] In some examples, the reasoning calculation process of the attention network may specifically include the following steps:

[0077] First, we need to calculate the dot product of the query vector Q and the key vector K to get the similarity scores between the two:

[0078] scores=Q·K T

[0079] Based on the similarity scores, the attention weight S can be further calculated:

[0080]

[0081] By performing matrix multiplication based on the attention weight S and the value vector V, we can get the output O of the attention network:

[0082] O=S·V

[0083] In this example, the size of the query vector Q is 1×D, and the size of the key vector K and the value vector V is L×D. In this case, the above method 200 can be applied to optimize the matrix multiplication operations involved in the similarity scores and the output result O. The operation process can be implemented based on the following formula, for example:

[0084] scores=Q·(scale K *qK) T +Q bias K T

[0085] O=S·(scale V *qV)+rowsum(S)*bias V

[0086] In this example, D is the dimension of the head in the attention mechanism, and L is the sequence length. Generally speaking, the value of D is much smaller than the value of L. In this case, Q and S with smaller data volumes can be used as the second matrix in method 200 to save computational effort.

[0087] According to some embodiments, the arithmetic logic unit includes a plurality of adders, and wherein in step S202, performing the second operation using the arithmetic logic unit includes: using the plurality of adders to calculate the sum of a plurality of rows of the second matrix in parallel. Thus, an arithmetic logic unit with a certain degree of operational parallelism can be used to implement high-concurrency operations, thereby improving operational efficiency.

[0088] In some examples, the matrix to be operated may be floating-point data, and the arithmetic logic unit may include n floating-point adders to achieve operation parallelism n. On this basis, the arithmetic logic unit may also include multiple registers for temporarily storing intermediate operation results to support arithmetic logic operations.

[0089] In this case, the summation operation in step S221 can be implemented based on the following formula:

[0090]

[0091] Where A[i][j] corresponds to the data element at position (i, j) in the second matrix A. In this example, each floating-point adder of the arithmetic logic unit and a register together complete a set of addition calculations. Specifically, each set of floating-point adders and registers initializes v0=0. In this example, n sets of floating-point adders and registers can read n data elements of A[i][0] in the first operation cycle, and then calculate v0=v0+data_i (data_i=A[i][0]). Similarly, the second operation cycle can read n data elements of A[i][1], and then calculate v0=v0+data_i (data_i=

[0092] A[i][1]), and so on, you can use v0 to record the sum of the data elements in each row.

[0093] According to one aspect of the present disclosure, a computing device is also provided. Figure 3 FIG. 4 shows a block diagram of a computing device 300 according to an exemplary embodiment of the present disclosure. Figure 3 As shown, the device 300 includes:

[0094] Matrix operation unit 310;

[0095] Arithmetic logic unit 320;

[0096] The first operation unit 330 is configured to, in response to receiving a target operation request to perform a dequantization operation on the first matrix based on the first quantization coefficient and the first offset and to perform a matrix multiplication operation on the quantized first matrix and the second matrix, the data amount of the first matrix is ​​greater than the data amount of the second matrix, perform a first operation using the matrix operation unit, wherein the arithmetic logic unit 320 is configured to: for each row of the second matrix, calculate the sum of multiple data elements of the row;

[0097] a second operation unit 340 configured to perform a second operation using the matrix operation unit, wherein the matrix operation unit 310 is configured to: determine a first intermediate result based on the first quantization coefficient, the first matrix, and the second matrix, wherein the first intermediate result indicates a product of a matrix multiplication result of the first matrix and the second matrix and the first quantization coefficient;

[0098] a third operation unit 350 configured to perform a multiplication operation based on the first offset and a sum of a plurality of rows of the second matrix to obtain a second intermediate result; and

[0099] The fourth operation unit 360 is configured to perform an accumulation operation based on the first intermediate result and the second intermediate result to obtain a target operation result.

[0100] According to some embodiments, the device 300 also includes: a splitting unit, configured to perform a splitting operation on the first matrix and the second matrix to obtain multiple sub-matrix groups, each sub-matrix group includes a first sub-matrix and a second sub-matrix, wherein the first operation unit 330 is configured to: in response to determining that the first operation on the first sub-matrix group is completed, while the matrix operation unit performs the second operation on the first sub-matrix group, use the arithmetic logic unit to perform the first operation on the second sub-matrix group.

[0101] According to some embodiments, the target operation request is determined using the following determination unit, which includes: an inverse quantization subunit, configured to respond to receiving a first operation request to perform an inverse quantization operation on a first matrix based on a first quantization coefficient and a first offset, to perform an inverse quantization operation on a third matrix based on a second quantization coefficient and a second offset, and to perform a matrix multiplication operation on the quantized first matrix and the quantized third matrix, and in response to determining that the data amount of the first matrix is ​​greater than the data amount of the third matrix, to perform an inverse quantization operation on the third matrix based on the second quantization coefficient and the second offset to obtain the second matrix; and a determination subunit, configured to determine a target operation request to perform an inverse quantization operation on the first matrix based on the first quantization coefficient and the first offset, and to perform a matrix multiplication operation on the quantized first matrix and the second matrix.

[0102] According to some embodiments, the first matrix is ​​a weight matrix of a fully connected layer of a neural network model, and the second matrix is ​​an input matrix of the fully connected layer.

[0103] According to some embodiments, the first matrix is ​​an attention weight matrix of an attention network, and the second matrix is ​​a value matrix of the attention network.

[0104] According to some embodiments, the arithmetic logic unit comprises a plurality of adders, and wherein the first operation unit 330 is configured to calculate the sum of a plurality of rows of the second matrix in parallel using the plurality of adders.

[0105] Figure 4 FIG. 4 shows a block diagram of a computing device 400 according to an exemplary embodiment of the present disclosure. Figure 4As shown, the device 400 includes a matrix operation unit 410, an arithmetic logic unit 420, a first operation unit 430, a second operation unit 440 and a third operation unit 450. In this example, the matrix operation unit 410 can be a calculation array composed of multiple arithmetic logic units 411, which can be used to implement two-dimensional matrix multiplication (i.e., the second operation). The arithmetic logic unit 420 may include multiple adders 421 to complete the above-mentioned first operation. The first operation unit 430, the second operation unit 440 and the third operation unit 450 are used to implement the steps S210, S220 and S240 in the aforementioned method 200. In this example, the operation of performing a multiplication operation based on the first offset and the sum of multiple rows of the second matrix in step S230 to obtain the second intermediate result can be implemented using the matrix operation unit 410, that is, performing a multiplication operation based on the row vector corresponding to the first offset and the column vector of the sum of multiple rows of the second matrix to obtain the second intermediate result.

[0106] In this example, when method 200 is applied to the matrix multiplication operation of the fully connected layer (i.e., Q=X·(scale WQ *qW Q )+rowsum(X)·bias WQ ), the hardware implementation process may include the following steps:

[0107] Step S1, use the adder 421 of the arithmetic logic unit 420 to complete the calculation of tmp1=rowsum(X). In this example, tmp1 can be a one-dimensional matrix composed of the sum of multiple rows of the X matrix.

[0108] Step S2: Use the matrix operation unit 410 to complete tmp2=tmp1*bias WQ In this example, bias WQ It can be a one-dimensional matrix obtained based on the value of the offset bias.

[0109] Step S3: Matrix operation unit 410 completes result d =scale WQ *(X*qW Q )+tmp2 is calculated to obtain the output result result_d.

[0110] As mentioned above, when the data scale is large, the original matrix can also be split, and steps S1 and S2-S3 are pipelined based on the split results, that is, the arithmetic logic unit 420 and the matrix operation unit 410 perform parallel operations to improve the operation efficiency.

[0111] According to one aspect of the present disclosure, a chip is also provided, comprising the computing device 300 as described above.

[0112] According to one aspect of the present disclosure, an electronic device is also provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the above-mentioned operation method.

[0113] According to one aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to enable the computer to execute the above-mentioned operation method.

[0114] According to one aspect of the present disclosure, a computer program product is also provided, including a computer program, wherein the computer program implements the above-mentioned operation method when executed by a processor.

[0115] refer to Figure 5 , a block diagram of an electronic device 500 that can be used as a server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0116] like Figure 5 As shown, the device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0117] Multiple components in the device 500 are connected to the I / O interface 505, including: an input unit 506, an output unit 507, a storage unit 508, and a communication unit 509. The input unit 506 can be any type of device that can input information to the device 500. The input unit 506 can receive input digital or character information and generate key signal input related to user settings and / or function control of the electronic device, and can include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and / or a remote controller. The output unit 507 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 508 can include but is not limited to a disk, an optical disk. The communication unit 509 allows the device 500 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and can include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth™ device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0118] The computing unit 501 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above, such as the operation method. For example, in some embodiments, the operation method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by the computing unit 501, one or more steps of the operation method described above may be performed. Alternatively, in other embodiments, the computing unit 501 may be configured to perform the operation method in any other appropriate manner (e.g., by means of firmware).

[0119] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0120] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0121] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0122] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0123] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), the Internet, and a blockchain network.

[0124] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0125] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0126] Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-mentioned methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples. Various elements in the embodiments or examples may be omitted or may be replaced by their equivalent elements. In addition, each step may be performed in an order different from that described in the present disclosure. Further, the various elements in the embodiments or examples may be combined in various ways. It is important that with the evolution of technology, many elements described herein may be replaced by equivalent elements that appear after the present disclosure.

Claims

1. A computing method implemented by a computing device, wherein: The operation device includes a matrix operation unit and an arithmetic logic unit, and the method includes: In response to receiving a target operation request to perform a dequantization operation on a first matrix based on a first quantization coefficient and a first offset and to perform a matrix multiplication operation on the quantized first matrix and a second matrix, wherein the data amount of the first matrix is ​​greater than the data amount of the second matrix, Performing a first operation using the arithmetic logic unit, wherein the first operation includes: For each row of the second matrix, calculating the sum of multiple data elements of the row; Performing a second operation using the matrix operation unit, wherein the second operation includes: Determine a first intermediate result based on the first quantization coefficient, the first matrix, and the second matrix, wherein the first intermediate result indicates a product of a matrix multiplication result of the first matrix and the second matrix and the first quantization coefficient; performing a multiplication operation based on the first offset and a sum of a plurality of rows of the second matrix to obtain a second intermediate result; and An accumulation operation is performed based on the first intermediate result and the second intermediate result to obtain a target operation result.

2. The method of claim 1, further comprising: performing a splitting operation on the first matrix and the second matrix to obtain a plurality of sub-matrix groups, each sub-matrix group including a first sub-matrix and a second sub-matrix, The using the arithmetic logic unit to perform the first operation includes: In response to determining that the first operation on the first sub-matrix group is completed, the arithmetic logic unit is used to perform the first operation on the second sub-matrix group while the matrix operation unit performs the second operation on the first sub-matrix group.

3. The method according to claim 1 or 2, wherein: The target operation request is determined in the following manner: In response to receiving a first operation request to perform a dequantization operation on a first matrix based on a first quantization coefficient and a first offset, to perform a dequantization operation on a third matrix based on a second quantization coefficient and a second offset, and to perform a matrix multiplication operation on the quantized first matrix and the quantized third matrix, and in response to determining that the data amount of the first matrix is ​​greater than the data amount of the third matrix, Performing a dequantization operation on the third matrix based on the second quantization coefficient and the second offset to obtain the second matrix; as well as A target operation request is determined to perform a dequantization operation on the first matrix based on the first quantization coefficient and the first offset and to perform a matrix multiplication operation on the quantized first matrix and the second matrix.

4. The method of claim 3, wherein: The first matrix is ​​a weight matrix of a fully connected layer of a neural network model, and the second matrix is ​​an input matrix of the fully connected layer.

5. The method of claim 3, wherein: The first matrix is ​​the attention weight matrix of the attention network, and the second matrix is ​​the value matrix of the attention network.

6. The method according to any one of claims 1 to 5, wherein: The arithmetic logic unit includes a plurality of adders, and wherein performing a first operation using the arithmetic logic unit includes: The sums of the plurality of rows of the second matrix are calculated in parallel using the plurality of adders.

7. A computing device, comprising: Matrix operation unit; Arithmetic logic unit; A first operation unit is configured to, in response to receiving a target operation request to perform a dequantization operation on a first matrix based on a first quantization coefficient and a first offset and to perform a matrix multiplication operation on the quantized first matrix and a second matrix, wherein the data amount of the first matrix is ​​greater than the data amount of the second matrix, perform a first operation using the arithmetic logic unit, wherein the arithmetic logic unit is configured to: For each row of the second matrix, calculating the sum of multiple data elements of the row; A second operation unit is configured to perform a second operation using the matrix operation unit, wherein the matrix operation unit is configured to: Determine a first intermediate result based on the first quantization coefficient, the first matrix, and the second matrix, wherein the first intermediate result indicates a product of a matrix multiplication result of the first matrix and the second matrix and the first quantization coefficient; a third operation unit configured to perform a multiplication operation based on the first offset and a sum of a plurality of rows of the second matrix to obtain a second intermediate result; and The fourth operation unit is configured to perform an accumulation operation based on the first intermediate result and the second intermediate result to obtain a target operation result.

8. The apparatus of claim 7, further comprising: a splitting unit configured to perform a splitting operation on the first matrix and the second matrix to obtain a plurality of sub-matrix groups, each sub-matrix group including a first sub-matrix and a second sub-matrix, Wherein, the first operation unit is configured as: In response to determining that the first operation on the first sub-matrix group is completed, the arithmetic logic unit is used to perform the first operation on the second sub-matrix group while the matrix operation unit performs the second operation on the first sub-matrix group.

9. The device according to claim 7 or 8, wherein: The target operation request is determined by using the following determination unit, and the determination unit includes: a dequantization subunit configured to, in response to receiving a first operation request to perform a dequantization operation on a first matrix based on a first quantization coefficient and a first offset, to perform a dequantization operation on a third matrix based on a second quantization coefficient and a second offset, and to perform a matrix multiplication operation on the quantized first matrix and the quantized third matrix, and in response to determining that the data amount of the first matrix is ​​greater than the data amount of the third matrix, to perform a dequantization operation on the third matrix based on the second quantization coefficient and the second offset to obtain the second matrix; and A determination subunit is configured to determine a target operation request for performing a dequantization operation on the first matrix based on the first quantization coefficient and the first offset and performing a matrix multiplication operation on the quantized first matrix and the second matrix.

10. The device of claim 9, wherein: The first matrix is ​​a weight matrix of a fully connected layer of a neural network model, and the second matrix is ​​an input matrix of the fully connected layer.

11. The device of claim 9, wherein: The first matrix is ​​the attention weight matrix of the attention network, and the second matrix is ​​the value matrix of the attention network.

12. The device according to any one of claims 7 to 11, wherein: The arithmetic logic unit includes a plurality of adders, and wherein the first operation unit is configured to: The sums of the plurality of rows of the second matrix are calculated in parallel using the plurality of adders.

13. A chip comprising the computing device according to any one of claims 7 to 12.

14. An electronic device comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to make a computer execute the method according to any one of claims 1-6.

16. A computer program product comprising a computer program, wherein: The computer program implements the method according to any one of claims 1 to 6 when executed by a processor.

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