Bridged chip verification platform and method

Abstract

The invention provides a bridge chip verification platform and method. A system driving agent unit controls a PCIe sub-environment to send a first type of data packet to a USB sub-environment through a to-be-tested object, and controls the USB sub-environment to send a second type of data packet to the PCIe sub-environment through the to-be-tested object; and the top scoreboard is used for determining a verification result of the to-be-tested object according to the first type of data packets, the second type of data packets, the third type of data packets and the fourth type of data packets. Protocol stacks of the USB sub-environment and the PCIe sub-environment are separated, so that light weight, high controllability and convenience in debugging can be realized. A system driver proxy unit is established outside a USB sub-environment and a PCIe sub-environment, and an interface provided by a PCIe protocol proxy is indirectly called through a higher-layer system driver proxy unit, so that a system driver accesses a USB hardware layer register through a PCIe interface, and the transceiving transmission of a USB is driven.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a bridge chip verification platform and method. Background Art

[0002] With the development of computer systems and the increase in data demand, interface technologies such as high-speed serial computer expansion bus standards (Peripheral Component Interconnect express, referred to as PCIe) and Universal Serial Bus (USB) play an important role in data storage and transmission. The combination of the two forms a PCIe to USB bridge chip, which facilitates the expansion of the computer's USB interface and achieves the effect of connecting more USB devices.

[0003] The PCIe to USB bridge chip can realize the conversion between the PCIe protocol and the USB protocol. It has many application scenarios in the fields of computers and data storage, mainly for connecting devices with USB interfaces to motherboards or systems that support PCIe interfaces. The stability of the performance of the PCIe to USB bridge chip is very important for the stable operation of the corresponding host device. Therefore, the verification of the PCIe to USB bridge chip is very important. However, since the PCIe to USB bridge chip involves the protocols of two high-speed interfaces, PCIe and USB, and the two need to cooperate with each other, the process is very complicated. This also brings huge challenges to the verification of the PCIe to USB bridge chip, which has become a difficult problem that technicians in this field are concerned about. Summary of the invention

[0004] The object of the present invention is to provide a bridge chip verification platform and method to at least partially improve the above-mentioned problem.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a bridge chip verification platform, the bridge chip verification platform comprising: a PCIe sub-environment, a USB sub-environment, a system driver agent unit, and a top-level scoreboard;

[0007] The system driver agent unit is used to control the PCIe sub-environment to send a first type of data packet to the USB sub-environment through the object to be tested, and control the USB sub-environment to send a second type of data packet to the PCIe sub-environment through the object to be tested;

[0008] The top-level scoreboard is used to determine the verification result of the object to be tested according to the first category of data packets, the second category of data packets, the third category of data packets and the fourth category of data packets;

[0009] Among them, the third type of data packet is a data packet received by the USB sub-environment, and the third type of data packet corresponds to the first type of data packet. The fourth type of data packet is a data packet received by the PCIe sub-environment, and the fourth type of data packet corresponds to the second type of data packet.

[0010] Optionally, the PCIe sub-environment includes a PCIe system agent module, a PCIe configuration module and a PCIe register model;

[0011] The PCIe system agent module includes a PCIe application layer component set, a PCIe protocol agent unit, and a root complex attachment facility;

[0012] The PCIe application layer component set includes a PCIe application layer sequence generator, a PCIe application layer data packet driver, a PCIe application layer request generator, and a PCIe application layer request responder;

[0013] The PCIe protocol agent unit includes a PCIe transaction layer, a PCIe data link layer and a PCIe physical layer;

[0014] The root complex ancillary facilities include an enumeration sequence, a configuration read and write sequence, a storage read and write sequence, an interrupt management component, and a system host memory model;

[0015] The PCIe configuration module includes the BDF number of the PCIe device, the BAR address of the PCIe device and the PCIe comparison enable;

[0016] The PCIe register model includes a plurality of first-type virtual registers, which correspond one-to-one to actual configuration registers in the PCIe subsystem in the object to be tested and serve as mapping registers of the configuration registers.

[0017] Optionally, the enumeration sequence is used to initiate an enumeration function;

[0018] The configuration read and write sequence is used to provide a configuration read and write interface to the PCIe application layer component set and the system driver agent unit;

[0019] The storage read / write sequence is used to provide access read / write interfaces to the PCIe application layer component set and the system driver agent unit;

[0020] The interrupt management component is used to manage the MSI / MSI-X interrupt message reported by the PCIe subsystem in the object to be tested;

[0021] The system host memory model is used to simulate the host memory connected to the root complex attachment facility to implement the storage of the PCIe storage transaction packet read and write data.

[0022] Optionally, the USB sub-environment includes a USB device proxy module, a USB configuration module and a USB register model;

[0023] The USB device proxy module includes a USB protocol layer, a USB link layer and a USB physical layer;

[0024] In the sending direction of the USB device proxy module, the data packet passes through the USB protocol layer, the USB link layer and the USB physical layer in sequence to reach the USB physical layer interface, and then is transmitted to the object to be tested;

[0025] In the receiving direction of the USB device proxy module, after the USB physical layer receives the data packet sent by the object to be tested through the USB physical layer interface, it passes it to the USB link layer and the USB protocol layer in sequence, and the USB protocol layer processes the received data packet to obtain a USB transmission packet;

[0026] The USB configuration module includes the number of USB device interfaces, the number of USB endpoints, and USB comparison enable;

[0027] The USB register model includes a plurality of second-type virtual registers, which correspond one-to-one to actual configuration registers in the USB subsystem of the object to be tested and serve as mapping registers of the configuration registers.

[0028] Optionally, the USB protocol layer includes a USB protocol layer sequence generator, a USB protocol layer data packet driver and a USB protocol layer monitor;

[0029] In the upstream direction, the USB protocol layer sequence generator generates a data packet, and sends the generated data packet to the USB protocol layer data packet driver through a pipeline, and the USB protocol layer data packet driver performs protocol layer protocol processing and then transmits it to the USB link layer;

[0030] In the downstream direction, data packets from the USB link layer are received by the USB protocol layer monitor, and after protocol layer protocol checking, are transmitted to the top-level scoreboard for use.

[0031] Optionally, the USB link layer includes a USB link layer sequence generator, a USB link layer data packet driver, and a USB link layer monitor;

[0032] In the upstream direction, the USB link layer sequence generator processes the USB protocol layer data packet transmitted by the USB protocol layer to generate a USB link layer data packet, and sends the USB link layer data packet to the USB link layer data packet driver through a pipeline, and the USB link layer data packet driver performs link layer protocol processing and then transmits it to the USB physical layer;

[0033] In the downstream direction, data packets from the USB physical layer are received by the USB link layer monitor, and are transmitted to the USB protocol layer after performing a link layer protocol check.

[0034] Optionally, the USB physical layer includes a USB physical layer sequence generator, a USB physical layer data packet driver, and a USB physical layer monitor;

[0035] In the upstream direction, the USB physical layer sequence generator processes the USB link layer data packet to generate a USB physical layer data packet, and sends the USB physical layer data packet to the USB physical layer data packet driver through a pipeline. The USB physical layer data packet driver performs physical layer protocol processing and then transmits it to the USB physical layer interface, and then drives it to the object to be tested;

[0036] In the downstream direction, data packets from the USB physical layer interface are received by the USB physical layer monitor, and are sent to the top-level scoreboard for use after physical layer protocol inspection.

[0037] Optionally, after the verification platform stops running, an internal chip status check and performance statistics are performed, the internal chip status check includes a read check of statistical registers, status registers, error reporting registers and interrupts in the PCIe subsystem of the object to be tested and a read check of statistical registers, status registers, error reporting registers, interrupts and interrupts in the USB subsystem of the object to be tested; performance statistics include the number of transmission packets in the sending and receiving directions and the calculation of the bit rate.

[0038] In a second aspect, an embodiment of the present invention provides a bridge chip verification method, which is applied to the above-mentioned bridge chip verification platform, and the method includes:

[0039] The system driver agent unit controls the PCIe sub-environment to send the first type of data packet to the USB sub-environment through the object to be tested, and controls the USB sub-environment to send the second type of data packet to the PCIe sub-environment through the object to be tested;

[0040] The top-level scoreboard determines the verification result of the object to be tested according to the first-category data packet, the second-category data packet, the third-category data packet, and the fourth-category data packet;

[0041] Among them, the third type of data packet is a data packet received by the USB sub-environment, and the third type of data packet corresponds to the first type of data packet. The fourth type of data packet is a data packet received by the PCIe sub-environment, and the fourth type of data packet corresponds to the second type of data packet.

[0042] Compared with the prior art, the embodiment of the present invention provides a bridge chip verification platform and method. The protocol stacks of the USB sub-environment and the PCIe sub-environment are separated, which can achieve lightweight, high controllability, and convenient debugging. In addition, a system driver proxy unit is built outside the USB sub-environment and the PCIe sub-environment. Through the higher-level system driver proxy unit, the interface provided by the PCIe protocol proxy is indirectly called to enable the system driver to access the USB hardware layer register through the PCIe interface, thereby driving the USB transceiver transmission.

[0043] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A schematic diagram of the structure of a bridge chip verification platform provided by an embodiment of the present invention.

[0046] Figure 2 A schematic diagram of the structure of a PCIe sub-environment provided in an embodiment of the present invention.

[0047] Figure 3 A schematic diagram of the structure of a PCIe system proxy module provided by an embodiment of the present invention.

[0048] Figure 4 A schematic diagram of the structure of a USB sub-environment provided by an embodiment of the present invention.

[0049] Figure 5 A schematic diagram of the structure of a system driver agent unit provided in an embodiment of the present invention.

[0050] Figure 6 A schematic diagram of the flow of a bridge chip verification method provided by an embodiment of the present invention.

[0051] In the figure: 10-system driver agent unit; 11-system driver sequence generator; 12-system driver component; 13-system driver monitor; 20-PCIe sub-environment; 21-PCIe system agent module; 22-PCIe configuration module; 23-PCIe register model; 211-PCIe application layer component set; 212-PCIe protocol agent unit; 213-root complex ancillary facilities; 30-USB sub-environment; 31-USB device agent module; 32-USB configuration module; 33-USB register model; 40-top scoreboard; 50-object to be tested. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0053] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0055] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0056] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, or are directions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0057] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0058] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0059] An embodiment of the present invention provides a bridge chip verification platform, which may be, but is not limited to, a verification platform for a PCIe to USB bridge chip based on Universal Verification Methodology (UVM).

[0060] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a bridge chip verification platform provided by an embodiment of the present invention. The bridge chip verification platform includes a PCIe sub-environment 20 (pcie_subenv), a USB sub-environment 30 (usb_subenv), a system driver agent unit 10 (system_driver_agent) and a top scoreboard 40 (top_scoreboard).

[0061] The system driver agent unit 10 is used to control the PCIe sub-environment 20 to send the first type of data packet to the USB sub-environment 30 through the object to be tested 50 (bridge chip or bridge simulation chip), and control the USB sub-environment 30 to send the second type of data packet to the PCIe sub-environment 20 through the object to be tested 50.

[0062] The top-level scoreboard 40 is used to determine the verification result of the object to be tested 50 according to the first type of data packets, the second type of data packets, the third type of data packets, and the fourth type of data packets.

[0063] Among them, the third type of data packet is the data packet received by the USB sub-environment 30, and the third type of data packet corresponds to the first type of data packet. The fourth type of data packet is the data packet received by the PCIe sub-environment 20, and the fourth type of data packet corresponds to the second type of data packet.

[0064] Please refer to Figure 2 , Figure 2 A schematic diagram of the structure of a PCIe sub-environment provided by an embodiment of the present invention. The PCIe sub-environment 20 includes a PCIe system agent module 21 (pcie_system_agent), a PCIe configuration module 22 (pcie_config) and a PCIe register model 23 (pcie_regmodel).

[0065] Please refer to Figure 3 , Figure 3 A schematic diagram of the structure of a PCIe system agent module provided in an embodiment of the present invention. The PCIe system agent module 21 (pcie_system_agent) is used to simulate a root complex. The PCIe system agent module 21 (pcie_system_agent) includes a PCIe application layer component set 211 (Application Layer), a PCIe protocol agent unit 212 (pcie_prot_agent) and a root complex ancillary facility 213 (Root Complex).

[0066] The PCIe application layer component set 211 (Application Layer) includes a PCIe application layer sequence generator (pcie_app_seqr), a PCIe application layer packet driver (pcie_app_driver), a PCIe application layer request generator (pcie_app_requester), and a PCIe application layer request responder (pcie_app_respond).

[0067] The PCIe application layer request generator (pcie_app_requester) is used to generate any one or more types of requests among storage (Memory), IO, configuration (Configuration) and message (Message).

[0068] The PCIe application layer request responder (pcie_app_respond) is used to receive data packets corresponding to any one or more types of storage (Memory), IO, configuration (Configuration) and message (Message) feedback from the transaction layer.

[0069] Among them, the PCIe application layer request generator (pcie_app_requester) generates a specific combination of PCIe transaction layer data packets by constraining the transaction packet types (including Memory, IO, Configuration, Message) in the PCIe transaction layer (PCIeTransaction Layer), the PCIe transaction layer sequence generator (pcie_tl_seqr) and the PCIe transaction layer data packet driver (pcie_tl_driver) in the PCIe transaction layer (PCIeTransaction Layer). The specific combination of PCIe transaction layer data packets corresponds to any one or more types of requests in the application layer's storage (Memory), IO, configuration (Configuration) and message (Message), and is used to generate the above four types of access to downstream PCIe devices.

[0070] The PCIe application layer request responder (pcie_app_respond) calls the PCIe transaction layer monitor (pcie_tl_monitor) and obtains the received transaction layer packet from the receiving pipeline of the PCIe transaction layer monitor (pcie_tl_monitor), parses and classifies it to obtain the response data packet corresponding to any one or more types of storage (Memory), IO, configuration (Configuration) and message (Message), so as to complete the response from the PCIe device request specified by the PCIe protocol.

[0071] The PCIe protocol agent unit 212 (pcie_prot_agent) includes a PCIe transaction layer (PCIe Transaction Layer), a PCIe data link layer (PCIe Data Link Layer) and a PCIe physical layer (PCIe Physical Layer).

[0072] The PCIe Transaction Layer is used to encapsulate requests from the PCIe application layer component set 211 (Application Layer) to generate transaction layer packets (TLPs) and pass them to the PCIe Data Link Layer (PCIeData Link Layer). It is also used to receive transaction layer packets from the PCIe Data Link Layer (PCIeData Link Layer) and pass the transaction layer packets received from the PCIe Data Link Layer (PCIeData Link Layer) to the PCIe application layer component set 211 (Application Layer) according to the type of the transaction layer packets.

[0073] The PCIe Data Link Layer is used to add the sequence number field and cyclic redundancy check code field to the transaction layer data packet from the PCIe Transaction Layer, encapsulate it into a data link layer packet to ensure the correctness of the data packet received by the other end, and transmit the data link layer packet to the PCIe Physical Layer. In addition, the PCIe Data Link Layer is also used to implement link management and other functions through the data link management packet.

[0074] The PCIe Data Link Layer is also used to parse and perform protocol processing on the data packet (physical layer packet) fed back by the PCIe Physical Layer after stripping the serial number field and cyclic redundancy check code field, and send the processed data packet to the PCIe Transaction Layer.

[0075] In the sending direction, the PCIe physical layer (PCIe Physical Layer) is used to convert and encode the data link layer packets transmitted by the PCIe data link layer (PCIe Data Link Layer) according to the physical layer protocol, and transmit the converted and encoded data to the object to be tested 50. The conversion and encoding process includes but is not limited to operations such as parallel-to-serial conversion and line coding.

[0076] In the receiving direction, the PCIe physical layer (PCIe Physical Layer) is used to receive the serial data transmitted by the test object 50 from the PCIe physical layer interface (PCIe_phy_interface), perform serial-to-parallel conversion and line decoding, and send the combined data packet back to the PCIe data link layer (PCIe Data Link Layer). At the same time, the PCIe physical layer (PCIePhysical Layer) implements the PCIe link training state machine and low power consumption function through the training sequence (Training Sequence) defined by the PCIe protocol.

[0077] Optionally, the PCIe transaction layer (PCIe Transaction Layer) includes a PCIe transaction layer sequence generator (pcie_tl_seqr), a PCIe transaction layer data packet driver (pcie_tl_driver) and a PCIe transaction layer monitor (pcie_tl_monitor). In the downlink direction, the PCIe transaction layer sequence generator (pcie_tl_seqr) generates a transaction packet, and sends the generated transaction packet to the PCIe transaction layer data packet driver (pcie_tl_driver) through a pipeline. The PCIe transaction layer data packet driver (pcie_tl_driver) performs transaction layer protocol processing and then transmits it to the PCIe data link layer (PCIe Data Link Layer). In the uplink direction, the data packet from the PCIe Data Link Layer is received by the PCIe transaction layer monitor (pcie_tl_monitor), and after the transaction layer protocol check, it is transmitted to the PCIe application layer component set 211 (Application Layer) for processing. Specifically, the PCIe application layer request responder (pcie_app_respond) receives the data packet transmitted by the PCIe transaction layer monitor (pcie_tl_monitor).

[0078] In the embodiment of the present invention, the downstream direction refers to the direction in which data is sent from the PCIe sub-environment 20 (pcie_subenv), and the upstream direction refers to the direction in which the PCIe sub-environment 20 (pcie_subenv) receives data.

[0079] The PCIe Data Link Layer includes the PCIe Link Layer Sequence Generator (pcie_dl_seqr), the PCIe Link Layer Packet Driver (pcie_dl_driver), and the PCIe Link Layer Monitor (pcie_dl_monitor). In the downstream direction, the PCIe Link Layer Sequence Generator (pcie_dl_seqr) adds the sequence number field and the cyclic redundancy check code field according to the transaction packet transmitted by the PCIe Transaction Layer (PCIeTransaction Layer), encapsulates it into a data link layer packet, and sends the data link layer packet to the PCIe Link Layer Packet Driver (pcie_dl_driver) through a pipeline. The PCIe Link Layer Packet Driver (pcie_dl_driver) performs link layer protocol processing and transmits it to the PCIe Physical Layer (PCIePhysical Layer). In the upstream direction, data packets from the PCIe physical layer (PCIe Physical Layer) are received by the PCIe link layer monitor (pcie_dl_monitor), and after the link layer protocol check is performed, they are transmitted to the PCIe transaction layer (PCIeTransaction Layer) for processing. Specifically, the PCIe transaction layer monitor (pcie_tl_monitor) receives data packets transmitted by the PCIe link layer monitor (pcie_dl_monitor).

[0080] The PCIe physical layer (PCIe Physical Layer) includes a PCIe physical layer sequence generator (pcie_pl_seqr), a PCIe physical layer data packet driver (pcie_pl_driver) and a PCIe physical layer monitor (pcie_pl_monitor). In the downstream direction, the PCIe physical layer sequence generator (pcie_pl_seqr) generates a transaction packet according to the data link layer packet transmitted by the PCIe data link layer (PCIeData Link Layer), and sends the generated transaction packet to the PCIe physical layer data packet driver (pcie_pl_driver) through a pipeline. The PCIe physical layer data packet driver (pcie_pl_driver) performs physical layer protocol processing and then transmits it to the PCIe physical layer interface (PCIe_phy_interface), and then drives it to the object to be tested 50. In the upstream direction, data packets from the PCIe physical layer interface (PCIe_phy_interface) are received by the PCIe physical layer monitor (pcie_pl_monitor), and after the physical layer protocol check, they are transmitted to the PCIe data link layer (PCIe Data Link Layer) for processing.

[0081] The above packet driver is used to realize the transaction level signal driving to the corresponding interface, the sequence generator is used to generate the corresponding layer packet, and the monitor is used to monitor the interface timing and check whether the data complies with the PCIe protocol. The root complex attachment facility 213 (Root Complex) includes an enumeration sequence (pcie_enum_seq), a configuration read and write sequence (pcie_cfg_seq), a storage read and write sequence (pcie_mem_seq), an interrupt management component (pcie_intr_mng) and a system host memory model (system_host_mem).

[0082] Among them, the enumeration sequence (pcie_enum_seq) is used to initiate the enumeration function; the configuration read and write sequence (pcie_cfg_seq) is used to provide a configuration read and write interface to the PCIe application layer component set 211 (Application Layer) and the system driver agent unit 10 (system_driver_agent); the storage read and write sequence (pcie_mem_seq) is used to provide an access read and write interface to the PCIe application layer component set 211 (Application Layer) and the system driver agent unit 10 (system_driver_agent); the interrupt management component (pcie_intr_mng) is used to manage the MSI / MSI-X interrupt message reported by the PCIe device (PCIe subsystem in the object to be tested); the system host memory model (system_host_mem) is used to simulate the host (CPU) memory connected to the root complex attachment facility 213 (Root Complex) to realize the storage of PCIe storage transaction package read and write data.

[0083] The PCIe configuration module 22 (pcie_config) includes global configuration information such as the BDF number (Bus Device Function) of the PCIe device, the BAR address (Base Address Register) of the PCIe device, and PCIe comparison enable.

[0084] The PCIe register model 23 (pcie_regmodel) includes mapping registers of all configuration registers of the PCIe subsystem in the object to be tested 50 (bridge chip), and provides an interface for the verification platform to access the registers. The PCIe register model 23 (pcie_regmodel) includes a plurality of first-class virtual registers, which correspond one-to-one to the actual configuration registers in the PCIe subsystem in the bridge chip, and serve as mapping registers of the configuration registers.

[0085] Please refer to Figure 4 , Figure 4 The USB sub-environment 30 includes a USB device agent module 31 (usb_device_agent), a USB configuration module 32 (usb_config) and a USB register model 33 (usb_regmodel).

[0086] The USB device agent module 31 (usb_device_agent) is used to simulate a USB device to generate a USB receiving transmission packet and / or sending transmission packet. The USB device agent module 31 (usb_device_agent) includes a USB protocol layer (USB Protocol Layer), a USB link layer (USB Link Layer) and a USB physical layer (USB Physical Layer).

[0087] In the sending direction of the USB device agent module 31 (usb_device_agent), the data packet sequentially passes through the USB protocol layer (USB Protocol Layer), the USB link layer (USB Link Layer) and the USB physical layer (USB Physical Layer) to reach the USB physical layer interface (usb_phy_interface), and is then transmitted to the object to be tested 50.

[0088] In the receiving direction of the USB device agent module 31 (usb_device_agent), after the USB physical layer (USBPhysical Layer) receives the data packet sent by the object to be tested 50 through the USB physical layer interface (usb_phy_interface), it passes it to the USB link layer (USB Link Layer) and the USB protocol layer (USB Protocol Layer) in sequence. The USB protocol layer (USB Protocol Layer) processes the received data packet to obtain a USB transmission packet.

[0089] The USB configuration module 32 (usb_config) includes global configuration information such as the number of USB device interfaces, the number of USB endpoints, and USB comparison enable.

[0090] The USB register model 33 (usb_regmodel) includes mapping registers of all configuration registers of the USB subsystem in the object to be tested 50 (bridge chip), and provides an interface for the verification platform to access the registers. The USB register model 33 (usb_regmodel) includes a plurality of second-class virtual registers, which correspond one-to-one to the actual configuration registers in the USB subsystem in the bridge chip, and serve as mapping registers of the configuration registers.

[0091] Optionally, the USB protocol layer (USB Protocol Layer) includes a USB protocol layer sequence generator (usb_prot_seqr), a USB protocol layer data packet driver (usb_prot_driver) and a USB protocol layer monitor (usb_prot_monitor). In the upstream direction, the USB protocol layer sequence generator (usb_prot_seqr) generates a data packet, and sends the generated data packet to the USB protocol layer data packet driver (usb_prot_driver) through a pipeline, and the USB protocol layer data packet driver (usb_prot_driver) performs protocol layer protocol processing and then transmits it to the USB link layer (USB Link Layer). In the downstream direction, the data packet from the USB link layer (USB Link Layer) is received by the USB protocol layer monitor (usb_prot_monitor), and after performing protocol layer protocol inspection, it is transmitted to the top layer of the verification platform (top layer scoreboard 40) for use.

[0092] The USB Link Layer includes a USB Link Layer sequence generator (usb_link_seqr), a USB Link Layer packet driver (usb_link_driver), and a USB Link Layer monitor (usb_link_monitor). In the upstream direction, the USB Link Layer sequence generator (usb_link_seqr) processes the USB Protocol Layer packets transmitted by the USB Protocol Layer to generate USB Link Layer packets, and sends the USB Link Layer packets to the USB Link Layer packet driver (usb_link_driver) through a pipeline. The USB Link Layer packet driver (usb_link_driver) performs Link Layer protocol processing and then transmits it to the USB Physical Layer. In the downstream direction, the packets from the USB Physical Layer are received by the USB Link Layer monitor (usb_link_monitor), and are transmitted to the USB Protocol Layer after performing Link Layer protocol checks.

[0093] The USB physical layer (USB Physical Layer) includes a USB physical layer sequence generator (usb_phy_seqr), a USB physical layer data packet driver (usb_phy_driver), and a USB physical layer monitor (usb_phy_monitor). In the upstream direction, the USB physical layer sequence generator (usb_phy_seqr) processes the USB link layer data packet to generate a USB physical layer data packet, and sends the USB physical layer data packet to the USB physical layer data packet driver (usb_phy_driver) through a pipeline. The USB physical layer data packet driver (usb_phy_driver) performs physical layer protocol processing and transmits it to the USB physical layer interface (usb_phy_interface), and then drives it to the object to be tested 50. In the downstream direction, the data packet from the USB physical layer interface (usb_phy_interface) is received by the USB physical layer monitor (usb_phy_monitor), and after the physical layer protocol check is performed, it is transmitted to the top layer of the verification platform (top scoreboard 40) for use.

[0094] Please refer to Figure 5 , Figure 5 A schematic diagram of the structure of a system driver agent unit provided in an embodiment of the present invention.

[0095] The system driver agent unit 10 (system_driver_agent) includes a system driver sequence generator 11 (system_driver_seqr), a system driver component 12 (system_driver_comp) and a system driver monitor 13 (system_driver_monitor).

[0096] The system driver sequence generator 11 (system_driver_seqr) is used to perform random processing according to one or more test items in the test case to obtain test parameter information corresponding to each test item, wherein the test item can be but is not limited to data length, endpoint number and transmission direction. The system driver sequence generator 11 (system_driver_seqr) is also used to send the test parameter information to the system driver component 12 (system_driver_comp). The test parameter information includes test case type constraint information and data construction information.

[0097] The system driver component 12 (system_driver_comp) is used to call the storage read and write sequence (pcie_mem_seq) provided by the PCIe system agent module 21 (pcie_system_agent) according to the test case type constraint information and data construction information, wherein the storage read and write sequence (pcie_mem_seq) is used to provide access read and write interfaces to the system driver component 12 in the PCIe application layer component set 211 (ApplicationLayer) and the system driver agent unit 10 (system_driver_agent). By calling the storage read and write sequence (pcie_mem_seq), a command ring (Command Ring), an event ring (Event Ring), and a transfer ring (Transfer Ring) are constructed in the system host memory model (system_host_mem). Among them, the command ring, the event ring, and the transfer ring are circular linked list data structures specified by the xHCI protocol, and their basic unit is a transfer request block (Transfer Tequest Block, abbreviated TRB). The data information and control information of TRB come from the test case type constraint information and data construction information to complete the verification of various scenarios.

[0098] The system driver component 12 (system_driver_comp) is also used to call the configuration read and write sequence (pcie_cfg_seq) provided by the PCIe system agent module 21 (pcie_system_agent) to drive the configuration of the USB operation registers (Operational Registers) and runtime registers (Runtime Registers) in the object under test 50, thereby starting the USB subsystem in the object under test 50 to initiate transceiver transmission.

[0099] The system driver monitor 13 (system_driver_monitor) is used to obtain the first type of data packets and the fourth type of data packets, and transmit the first type of data packets and the fourth type of data packets to the top scoreboard 40 (top_scoreboard).

[0100] The top scoreboard 40 (top_scoreboard) is responsible for comparing the uplink and downlink data to determine the verification result of the object to be tested 50 .

[0101] Specifically, in the downstream direction, the first type of data packet input from the PCIe subsystem of the object to be tested 50 is compared with the third type of data packet output from the USB subsystem of the object to be tested 50; in the upstream direction, the second type of data packet input from the USB subsystem of the object to be tested 50 is compared with the fourth type of data packet output from the PCIe subsystem of the object to be tested 50.

[0102] On the basis of the foregoing, regarding how the bridge chip verification platform realizes the power-on of the object to be tested, the embodiment of the present invention further provides an optional implementation method, please refer to the following.

[0103] Perform power-on reset and clock generation, and the verification platform drives the object to be tested 50 to power on the top layer of the chip, generate reference clocks, and perform reset withdrawal. Powering on the top layer of the chip refers to driving the power-on level of the power pin VDD and the ground pin VSS at the top layer of the chip, wherein VDD drives the power-on process of the level 0->1, and VSS always drives the 0 level. The reference clock includes the reference clock clk_pref of PCIe and the reference clock clk_uref of USB, both of which can be 100M. Each reset includes the pin reset (ponrst) and the PCIe interface (perst) of the object to be tested 50, and the reset timing is the reset withdrawal process of driving the level 0->1, and the reset withdrawal order is the pin reset (ponrst) first and then the PCIe interface (perst).

[0104] After power-on reset and clock generation, the verification platform loads the firmware program and initializes the chip configuration for the object under test 50. After power-on reset and clock generation, the firmware program (basic operation program) is loaded into the ROM memory in the processing subsystem (mcu_subsys) of the object under test 50 and the initialization chip is started.

[0105] Since the reset and withdrawal of the processing subsystem (mcu_subsys) is withdrawn after the pin reset (ponrst) is supplemented with a preset delay, the firmware program loading is completed in the time period before the reset and withdrawal of the processing subsystem (mcu_subsys) and after the pin reset (ponrst). The loading method can be but is not limited to calling the verilog system function $readmemh to read the firmware program file and store it in the corresponding array of the ROM memory. The firmware program mainly includes the chip initialization configuration program and the interrupt handler. The chip initialization configuration program includes PCIe / USB PHY parameters, PCIe link training enable, and PCIe configuration space parameter vendor flag / device flag (vendor_id / device_id ) And USB controller low power enable.

[0106] After the chip initialization configuration is completed, PCIe link detection and training can be performed.

[0107] The PCIe physical layer (PCIePhysical Layer) in the PCIe protocol agent unit 212 (pcie_prot_agent) in the verification platform and the PCIe physical layer interface (PCIe_phy_interface) of the object to be tested 50 form a pair of link partners of the PCIe bus. After the power-on reset on the chip is removed, the PCIe physical layer (PCIe Physical Layer) and the PCIe physical layer interface (PCIe_phy_interface) detect each other's existence and PCIe link training can be performed.

[0108] Optionally, the PCIe link training state is converted from Detect->Polling->Configuration->L0 through an interactive PCIe training sequence (including TS1 / TS2 and other training sequences) to achieve the L0 state of normal communication.

[0109] Optionally, the PCIe physical layer (PCIe Physical Layer) has a link training state machine inside for tracking and recording the link status, and has a corresponding checker to check whether the response and status of the PCIe physical layer interface (PCIe_phy_interface) of the object to be tested 50 during the link training process are as expected, so as to ensure the compliance of the chip PCIe protocol.

[0110] After the PCIe link detection and training are completed, the USB link detection and training are performed.

[0111] The USB device agent module 31 (usb_device_agent) in the verification platform simulates a USB device, and the USB physical layer (USB Physical Layer) therein is connected to the USB physical layer interface (usb_phy_interface) in the object to be tested 50. After the chip is powered on and reset, the USB physical layer interface (usb_phy_interface) in the object to be tested 50 detects the existence of the USB device agent module 31 (usb_device_agent), and USB link training can be performed.

[0112] Optionally, interactive training is performed based on a low frequency periodic signal (LFPS) and a USB training sequence (including TSEQ, TS1, and TS2, etc.) to complete the state transition of the USB link training state from Rx.Detect->Polling->U0 to reach the U0 state of normal operation.

[0113] Optionally, the USB physical layer (USB Physical Layer) has a link training state machine inside for tracking and recording the link status, and has a corresponding checker to check whether the response and status of the USB physical layer interface (usb_phy_interface) in the object to be tested 50 are as expected during the link training process to ensure compliance with the chip USB protocol.

[0114] After the USB link detection and training are completed, PCIe device enumeration is performed. The root complex auxiliary facility 213 (Root Complex) in the PCIe system agent module 21 (pcie_system_agent) acts as the root complex on the PCIe bus and initiates the enumeration process of the PCIe subsystem in the test object. The specific enumeration process is as follows:

[0115] The enumeration sequence (pcie_enum_seq) is attached to the PCIe application layer sequence generator (pcie_app_seqr), which constrains the PCIe application layer sequence generator (pcie_app_seqr) to generate enumeration transaction packets, which are sent to the PCIe application layer data packet driver (pcie_app_driver) through the channel, and then the enumeration-related application layer transaction packets are issued, including the BDF number and BAR address allocation transaction packets for the PCIe device. The enumeration process is to constrain the PCIe application layer sequence generator (pcie_app_seqr) to generate enumeration transaction packets, and send the enumeration transaction packets to the PCIe subsystem of the design to be tested. These enumeration-related application layer transaction packets are converted into corresponding protocol layer transaction packets layer by layer through the PCIe transaction layer (PCIe TransactionLayer), PCIe data link layer (PCIe Data Link Layer) and PCIe physical layer (PCIe Physical Layer) in the PCIe protocol agent unit 212 (pcie_prot_agent), and finally driven to the PCIe physical layer interface (PCIe_phy_interface) of the object to be tested 50, thereby completing the enumeration of the PCIe device.

[0116] After the PCIe device enumeration is completed, the USB device enumeration is performed. It should be noted that the USB device enumeration is performed after the PCIe device enumeration is completed, and the PCIe link has the storage read and write and configuration read and write capabilities.

[0117] The system driver agent unit 10 (system_driver_agent), the USB device agent module 31 (usb_device_agent) and the PCIe system agent module 21 (pcie_system_agent) cooperate to complete the enumeration process of the USB subsystem in the object to be tested. The system driver component 12 (system_driver_comp) in the system driver agent unit 10 (system_driver_agent) performs the read and write actions corresponding to the USB device enumeration by calling the configuration read and write sequence (pcie_cfg_seq) and / or the storage read and write sequence (pcie_mem_seq) in the PCIe system agent module 21 (pcie_system_agent).

[0118] The USB device enumeration process is specifically as follows: the USB subsystem in the object to be tested 50 sends an assign address command, a get device descriptor command and a get device configuration command to the USB device agent module 31 (usb_device_agent).

[0119] The system driver component 12 (system_driver_comp) uses the system host memory model (system_host_mem) in the PCIe system agent module 21 (pcie_system_agent) to simulate the system host memory, and constructs a command ring (Command Ring), an event ring (Event Ring), and a transfer ring (Transfer Ring) with the transfer request block TRB (Transfer Request Block) as the basic unit, and adds the above-mentioned address allocation command, device descriptor acquisition command, and device configuration acquisition command to the command ring, thereby driving the command register (USBCMD.Run) in the USB subsystem of the object to be tested to be written as 1, and starting the execution of the command ring. During the execution of the command ring, the USB device agent module 31 (usb_device_agent) acts as a USB device role, receives requests corresponding to the command ring (including address allocation and response acquisition requests) and responds to corresponding requests, thereby completing the enumeration process of the USB device.

[0120] The top scoreboard 40 (top_scoreboard) is responsible for comparing the uplink and downlink data, and the specific process is as follows.

[0121] The system driver agent unit 10 controls the PCIe sub-environment 20 to send the first type of data packet to the USB sub-environment 30 through the object to be tested 50 (bridge chip), and controls the USB sub-environment 30 to send the second type of data packet to the PCIe sub-environment 20 through the object to be tested 50. The top-level scoreboard 40 determines the verification result of the object to be tested 50 according to the first type of data packet, the second type of data packet, the third type of data packet and the fourth type of data packet.

[0122] Among them, the third type of data packet is the data packet received by the USB sub-environment 30, and the third type of data packet corresponds to the first type of data packet. The fourth type of data packet is the data packet received by the PCIe sub-environment 20, and the fourth type of data packet corresponds to the second type of data packet.

[0123] In the USB data transmission direction, after receiving the stimulus packet request from the system driver sequence generator 11 (system_driver_seqr), the system driver component 12 (system_driver_comp) constructs a transmission TRB structure according to the data length, endpoint number, and transmission direction in the stimulus packet, wherein the data buffer pointer points to the pre-initialized buffer area, and then adds the transmission TRB to the transmission transmission ring. In the USB data reception direction, the system driver component 12 (system_driver_comp) also adds the constructed transmission TRB to another reception transmission ring.

[0124] After the construction of the transmission ring is completed in the USB data sending direction and the USB data receiving direction, the system driver component 12 (system_driver_comp) will call the storage read and write sequence (pcie_mem_seq) to drive the PCIe physical layer interface (PCIe_phy_interface) in the object to be tested to generate a storage write operation targeting the doorbell register to complete the corresponding USB endpoint doorbell register write to start the execution of the transmission ring, and finally complete the sending and receiving of USB data.

[0125] The top scoreboard 40 (top_scoreboard) is responsible for comparing the data in the USB data transmission direction and the USB data reception direction. Specifically, the top scoreboard 40 determines the verification result of the object to be tested 50 according to the first data packet, the second data packet, the third data packet and the fourth data packet.

[0126] In the USB data transmission direction, the top scoreboard 40 (top_scoreboard) receives the transmission data packet (third type data packet) sampled from the USB device agent module 31 (usb_device_agent), and receives the transmission reference data packet (first type data packet) extracted from the system cache by the system driver monitor 13 (system_driver_monitor), and compares the two data packets. In the USB data reception direction, the top scoreboard 40 (top_scoreboard) receives the reception data packet (fourth type data packet) extracted from the system cache by the system driver monitor 13 (system_driver_monitor), and receives the reference data packet (second type data packet) sampled from the USB device agent module 31 (usb_device_agent), and compares the two data packets.

[0127] In an optional implementation, after the verification platform stops running, the chip internal status check and performance statistics can be performed (by the top level of the verification platform). The chip internal status check and performance statistics are started after a configurable delay such as the completion of the sending of the stimulus packet called by the verification platform, and the verification platform is stopped after completion. The chip internal status check includes a read check of the statistics registers, status registers, error report registers, and interrupts in the PCIe subsystem of the object to be tested, and a read check of the statistics registers, status registers, error report registers, interrupts, and interrupts in the USB subsystem of the object to be tested; performance statistics include the number of transmission packets in the sending and receiving directions and the calculation (and printing) of the bit rate.

[0128] In the verification platform provided by the embodiment of the present invention, the protocol stacks of the USB sub-environment and the PCIe sub-environment are separated, and the protocol layers of the customized PCIe and USB are implemented to achieve lightweight, high controllability, and convenient debugging. In addition, a system driver proxy unit is built outside the USB sub-environment and the PCIe sub-environment, and the interface provided by the PCIe protocol proxy is indirectly called through the higher-level system driver proxy unit to enable the system driver to access the USB hardware layer register through the PCIe interface, thereby driving the USB transceiver transmission.

[0129] A bridge chip verification method is applied to the above-mentioned bridge chip verification platform, please refer to Figure 6 The bridge chip verification method includes: S601 and S602, which are specifically described as follows.

[0130] S601, the system driver agent unit controls the PCIe sub-environment to send a first type of data packet to the USB sub-environment through the object to be tested, and controls the USB sub-environment to send a second type of data packet to the PCIe sub-environment through the object to be tested.

[0131] S602, the top-level scoreboard determines the verification result of the object to be tested according to the first type of data packets, the second type of data packets, the third type of data packets and the fourth type of data packets.

[0132] Among them, the third type of data packet is a data packet received by the USB sub-environment, and the third type of data packet corresponds to the first type of data packet. The fourth type of data packet is a data packet received by the PCIe sub-environment, and the fourth type of data packet corresponds to the second type of data packet.

[0133] It should be noted that the bridge chip verification method provided in this embodiment can perform the functions and uses shown in the above bridge chip verification platform embodiment to achieve the corresponding technical effects. For the sake of brief description, for parts not mentioned in this embodiment, please refer to the corresponding contents in the above embodiments.

[0134] In summary, an embodiment of the present invention provides a bridge chip verification platform and method, the bridge chip verification platform includes: a PCIe sub-environment, a USB sub-environment, a system driver agent unit and a top-level scoreboard; the system driver agent unit is used to control the PCIe sub-environment to send a first-class data packet to the USB sub-environment through the object to be tested, and control the USB sub-environment to send a second-class data packet to the PCIe sub-environment through the object to be tested; the top-level scoreboard is used to determine the verification result of the object to be tested according to the first-class data packet, the second-class data packet, the third-class data packet and the fourth-class data packet; wherein the third-class data packet is a data packet received by the USB sub-environment, and the third-class data packet corresponds to the first-class data packet, and the fourth-class data packet is a data packet received by the PCIe sub-environment, and the fourth-class data packet corresponds to the second-class data packet. The protocol stacks of the USB sub-environment and the PCIe sub-environment are separate, which can achieve lightweight, high controllability, and convenient debugging. In addition to the USB sub-environment and PCIe sub-environment, a system driver agent unit is built. Through the higher-level system driver agent unit, the interface provided by the PCIe protocol agent is indirectly called to enable the system driver to access the USB hardware layer registers through the PCIe interface, thereby driving the USB transmission.

[0135] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0136] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A bridge chip verification platform, characterized in that: The bridge chip verification platform includes: a PCIe sub-environment, a USB sub-environment, a system driver agent unit and a top-level scoreboard; The system driver agent unit is used to control the PCIe sub-environment to send a first type of data packet to the USB sub-environment through the object to be tested, and control the USB sub-environment to send a second type of data packet to the PCIe sub-environment through the object to be tested; The top-level scoreboard is used to determine the verification result of the object to be tested according to the first category of data packets, the second category of data packets, the third category of data packets and the fourth category of data packets; Among them, the third type of data packet is a data packet received by the USB sub-environment, and the third type of data packet corresponds to the first type of data packet. The fourth type of data packet is a data packet received by the PCIe sub-environment, and the fourth type of data packet corresponds to the second type of data packet.

2. The bridge chip verification platform according to claim 1, characterized in that: The PCIe sub-environment includes a PCIe system agent module, a PCIe configuration module and a PCIe register model; The PCIe system agent module includes a PCIe application layer component set, a PCIe protocol agent unit, and a root complex attachment facility; The PCIe application layer component set includes a PCIe application layer sequence generator, a PCIe application layer data packet driver, a PCIe application layer request generator, and a PCIe application layer request responder; The PCIe protocol agent unit includes a PCIe transaction layer, a PCIe data link layer and a PCIe physical layer; The root complex ancillary facilities include an enumeration sequence, a configuration read and write sequence, a storage read and write sequence, an interrupt management component, and a system host memory model; The PCIe configuration module includes the BDF number of the PCIe device, the BAR address of the PCIe device and the PCIe comparison enable; The PCIe register model includes a plurality of first-type virtual registers, which correspond one-to-one to actual configuration registers in the PCIe subsystem in the object to be tested and serve as mapping registers of the configuration registers.

3. The bridge chip verification platform as claimed in claim 2, characterized in that: The PCIe application layer request generator is used to constrain the transaction packet type in the PCIe transaction layer so that the PCIe transaction layer sequence generator and the PCIe transaction layer data packet driver in the PCIe transaction layer generate a specific combination of PCIe transaction layer data packets, and the specific combination of PCIe transaction layer data packets corresponds to any one or more types of requests among storage, IO, configuration and message of the application layer; The PCIe application layer request responder is used to obtain the received transaction layer packet from the receiving pipeline of the PCIe transaction layer monitor by calling the PCIe transaction layer monitor, and parse and classify to obtain the response data packet corresponding to any one or more types of storage, IO, configuration and message.

4. The bridge chip verification platform as claimed in claim 2, characterized in that: The PCIe transaction layer is used to encapsulate the request from the PCIe application layer component set to generate a transaction layer data packet, and transmit it to the PCIe data link layer; Also used for receiving a transaction layer data packet from the PCIe data link layer, and delivering the transaction layer data packet received from the PCIe data link layer to the PCIe application layer component set according to the type of the transaction layer data packet; The PCIe data link layer is used to add a sequence number field and a cyclic redundancy check code field to a transaction layer data packet from the PCIe transaction layer, encapsulate it into a data link layer packet, and transmit the data link layer packet to the PCIe physical layer; The PCIe data link layer is also used to parse and perform protocol processing on the data packet fed back by the PCIe physical layer after stripping the sequence number field and the cyclic redundancy check code field, and send the processed data packet to the PCIe transaction layer; The PCIe physical layer is used to convert and encode the data link layer packets transmitted by the PCIe data link layer according to the physical layer protocol, and transmit the converted and encoded data to the object to be tested; The PCIe physical layer is also used to receive serial data transmitted by the object to be tested from the PCIe physical layer interface, perform serial-to-parallel conversion and line decoding, and send the combined data packet back to the PCIe data link layer.

5. The bridge chip verification platform as claimed in claim 4, characterized in that: The PCIe transaction layer includes a PCIe transaction layer sequence generator, a PCIe transaction layer data packet driver and a PCIe transaction layer monitor; In the downlink direction, the PCIe transaction layer sequence generator generates a transaction packet, and sends the generated transaction packet to the PCIe transaction layer data packet driver through a pipeline, and the PCIe transaction layer data packet driver performs transaction layer protocol processing and then transmits it to the PCIe data link layer; In the uplink direction, the data packet from the PCIe data link layer is received by the PCIe transaction layer monitor, and is transmitted to the PCIe application layer component set for processing after a transaction layer protocol check.

6. The bridge chip verification platform as claimed in claim 4, characterized in that: The PCIe data link layer includes a PCIe link layer sequence generator, a PCIe link layer data packet driver and a PCIe link layer monitor; In the downlink direction, the PCIe link layer sequence generator adds a sequence number field and a cyclic redundancy check code field according to the transaction packet transmitted by the PCIe transaction layer, encapsulates it into a data link layer packet, and sends the data link layer packet to the PCIe link layer data packet driver through a pipeline. The PCIe link layer data packet driver performs link layer protocol processing and then transmits it to the PCIe physical layer; In the uplink direction, the data packet from the PCIe physical layer is received by the PCIe link layer monitor, and is transmitted to the PCIe transaction layer after a link layer protocol check.

7. The bridge chip verification platform according to claim 4, characterized in that: The PCIe physical layer includes a PCIe physical layer sequence generator, a PCIe physical layer data packet driver and a PCIe physical layer monitor; In the downlink direction, the PCIe physical layer sequence generator generates a transaction packet according to the data link layer packet transmitted by the PCIe data link layer, and sends the generated transaction packet to the PCIe physical layer data packet driver through a pipeline. The PCIe physical layer data packet driver performs physical layer protocol processing and transmits it to the PCIe physical layer interface, and then drives it to the object to be tested; In the uplink direction, data packets from the PCIe physical layer interface are received by the PCIe physical layer monitor, and are transmitted to the PCIe data link layer for processing after a physical layer protocol check.

8. The bridge chip verification platform according to claim 1, characterized in that: The USB sub-environment includes a USB device proxy module, a USB configuration module and a USB register model; The USB device proxy module includes a USB protocol layer, a USB link layer and a USB physical layer; In the sending direction of the USB device proxy module, the data packet passes through the USB protocol layer, the USB link layer and the USB physical layer in sequence to reach the USB physical layer interface, and then is transmitted to the object to be tested; In the receiving direction of the USB device proxy module, after the USB physical layer receives the data packet sent by the object to be tested through the USB physical layer interface, it passes it to the USB link layer and the USB protocol layer in sequence, and the USB protocol layer processes the received data packet to obtain a USB transmission packet; The USB configuration module includes the number of USB device interfaces, the number of USB endpoints, and USB comparison enable; The USB register model includes a plurality of second-type virtual registers, which correspond one-to-one to actual configuration registers in the USB subsystem of the object to be tested and serve as mapping registers of the configuration registers.

9. The bridge chip verification platform according to claim 2, characterized in that: The system drive agent unit includes a system drive sequence generator, a system drive component and a system drive monitor; The system drive sequence generator is used to perform random processing according to one or more test items in the test case to obtain test parameter information corresponding to each test item, wherein the test item is any one or more of data length, endpoint number and transmission direction; The system drive sequence generator is also used to send the test parameter information to the system drive component, wherein the test parameter information includes test case type constraint information and data construction information; The system driver component is used to call the storage read and write sequence provided by the PCIe system agent module according to the test case type constraint information and the data construction information, and to construct a command ring, an event ring, and a transmission ring in the system host memory model by calling the storage read and write sequence, wherein the command ring, the event ring, and the transmission ring are circular linked list data structures specified by the xHCI protocol; The system driver component is also used to call the configuration read and write sequence provided by the PCIe system agent module to drive the configuration of the USB operation register and the runtime register of the object to be tested, thereby starting the USB subsystem of the object to be tested to initiate the receiving and sending transmission; The system driver monitor is used to obtain the first type of data packets and the fourth type of data packets, and transmit the first type of data packets and the fourth type of data packets to the top-level scoreboard.

10. A bridge chip verification method, characterized in that: The bridge chip verification platform applied to any one of claims 1 to 9, the method comprising: The system driver agent unit controls the PCIe sub-environment to send the first type of data packet to the USB sub-environment through the object to be tested, and controls the USB sub-environment to send the second type of data packet to the PCIe sub-environment through the object to be tested; The top-level scoreboard determines the verification result of the object to be tested according to the first category of data packets, the second category of data packets, the third category of data packets, and the fourth category of data packets; Among them, the third type of data packet is a data packet received by the USB sub-environment, and the third type of data packet corresponds to the first type of data packet. The fourth type of data packet is a data packet received by the PCIe sub-environment, and the fourth type of data packet corresponds to the second type of data packet.

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