Pseudo dual-port static random access memory SRAM

Abstract

The present invention relates to the technical field of processors, and provides a pseudo dual-port static random access memory SRAM. The pseudo dual-port SRAM has two external ports, which are used for reading data and writing data respectively. The interior of the SRAM is composed of three single-port SRAMs, an address mapping table, three fully associative mapped data valid registers and three idle address registers. In the structures provided by various embodiments of the present invention, the area occupied by the SRAM is smaller, and both timing and area can be considered.

Description

Technical Field

[0001] The present invention relates to the technical field of processors, and in particular to a pseudo dual-port static random access memory SRAM. Background Art

[0002] Static Random-Access Memory (SRAM) technology has long been an ideal choice for on-chip storage. This is not only because of its superior latency and scalability characteristics, but also because the same complementary metal oxide semiconductor (CMOS) transistors used in logic components can also be used for SRAM cache. The SRAM cell is a simple bistable latch that operates at the same voltage as the other components in the processor. Therefore, it does not require a separate voltage plane or charge pump that is commonly used for other memory types. Because the cross-coupled inverters in the latch can automatically correct for any charge leakage in the stored value, the device can maintain its value without periodic refreshes, as required in dynamic RAM (DRAM) memory. By design, it outputs a differential signal that is easier to detect and more reliable. These characteristics have made SRAM the best choice for on-chip storage for many years.

[0003] As the processor frequency increases, the read and write timing of SRAM gradually becomes the bottleneck of the pipeline. The read and write time of dual-port SRAM is 10%~20% worse than that of single-port SRAM. Therefore, in actual implementation, pseudo dual-port SRAM (Simple dual-port SRAM) is used to simulate true dual-port SRAM (True dual-port SRAM), but the method of using two identical single-port SRAMs to simulate single-port SRAM will lead to problems such as high SRAM area. Summary of the invention

[0004] In view of the problems in the prior art, the present invention provides a pseudo dual-port static random access memory SRAM.

[0005] A first aspect of the present invention provides a pseudo dual-port static random access memory SRAM, wherein the pseudo dual-port SRAM has two external ports, which are used for reading data and writing data respectively; the pseudo dual-port SRAM comprises:

[0006] Three single-port SRAMs, and the internal column address set of each of the single-port SRAMs is half of the external column address set; the three single-port SRAMs include even SRAMs, odd SRAMs and other SRAMs;

[0007] Three data valid registers, corresponding to the three single-port SRAMs respectively, the number of bits of each data valid register is the same as the number of sets within the single-port SRAM, and the values ​​of the corresponding bits of the data valid registers are respectively used to indicate the validity of the data in the storage address corresponding to each address index within the single-port SRAM;

[0008] Three idle address registers, corresponding to the three single-port SRAMs respectively, each of the idle address registers is used to indicate whether there is an idle table entry in the corresponding single-port SRAM, and an external idle mapping address value;

[0009] An address mapping table is used to record the correspondence between the external address index and the internal address index in the three single-port SRAMs.

[0010] Optionally, the length of the corresponding bit in the data valid register is 1 bit, and a bit position of 1 indicates that the data is valid, and a bit position of 0 indicates that the data is invalid.

[0011] Optionally, the free address register includes a 1-bit hasFree bit, which is 1 to indicate that there is a free table entry, and 0 to indicate that there is no free table entry; a 1-bit other bit, which is 1 to indicate that the data is stored in the other SRAM, and is 0 to indicate that the data is stored in the even SRAM or the odd SRAM; an n-bit index bit, which indicates the external address index of each single-port SRAM, the width of n is equal to log2 (set / 2), and set is an external set; a 1-bit even / odd bit, which is 1 to indicate that the data is stored in the even SRAM, and is 0 to indicate that the data is stored in the odd SRAM.

[0012] Optionally, the three idle address registers include: an even idle address register, an odd idle address register and an other idle address register;

[0013] The other bits in the even idle address register and the odd idle address register are constantly 0, and the other bits in the other idle address register are constantly 1;

[0014] The even / odd bit of the even idle address register is constantly 0, the even / odd bit of the odd idle address register is constantly 1, and the even / odd bit of the other idle address register is constantly 0.

[0015] Optionally, the address mapping table includes multiple rows, and the data of each row is used to represent the internal address index; the data of each row includes a 1-bit other bit, which is 1 to indicate that the data is stored in the other SRAM, and is 0 to indicate that the data is stored in the even SRAM or the odd SRAM; an n-bit index bit, which indicates the external address index of each single-port SRAM, and the width of n is equal to log2 (set / 2), and set is an external set; a 1-bit even / odd bit, which is 1 to indicate that the data is stored in the even SRAM, and is 0 to indicate that the data is stored in the odd SRAM;

[0016] The number of rows of the address mapping table is the same as the number of the external address indexes, and the data of each row of the address mapping table corresponds one-to-one to the external address index.

[0017] Optionally, when the external read enable is valid, searching for an internal address index corresponding to the external address index based on the address mapping table;

[0018] When the other bit is 1 and the even / odd bit is 1, determine to read data from the storage address corresponding to the index bit in the even SRAM;

[0019] When the other bit is 1 and the even / odd bit is 0, determine to read data from the storage address corresponding to the index bit in the odd SRAM;

[0020] When the other bit is 0, it is determined to read data from the storage address corresponding to the index bit in the other SRAM.

[0021] Optionally, when both external read and write enable are valid, but internal read and write addresses are not on the same single-port SRAM or only write enable is valid, the address of the external write request is used as the address of the internal write request;

[0022] When the external read and write enables are valid at the same time and the internal read and write addresses are on the same single-port SRAM, it is determined to perform write splitting and one address is selected from the idle address register as the internal write address.

[0023] Optionally, at the end of the write operation:

[0024] Use the external write request address as an index and update the actual internal write address to the corresponding index position;

[0025] Use the actual internal write update address to update the corresponding single-port SRAM;

[0026] Use the data valid register corresponding to the external update address index to update the corresponding index position to 0;

[0027] Use the internal write to update the data valid register corresponding to the address index and update the corresponding index position to 1.

[0028] A second aspect of the present invention provides a chip, comprising the pseudo dual-port static random access memory SRAM described in the first aspect.

[0029] A third aspect of the present invention provides an electronic device, comprising the chip described in the second aspect.

[0030] The pseudo dual-port static random access memory SRAM provided by the present invention has two external ports, which are used for reading data and writing data respectively. The interior of the SRAM is composed of three single-port SRAMs, an address mapping table, three fully associative mapped data valid registers and three idle address registers. The SRAM in the structure provided by each embodiment of the present invention occupies a smaller area, and can take into account both timing and area. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of the structure of a pseudo dual-port SRAM provided in an embodiment of the present invention.

[0033] Figure 2 Schematic diagram of three single-port SRAMs provided in an embodiment of the present invention.

[0034] Figure 3 A schematic diagram of a data valid flag register provided in an embodiment of the present invention.

[0035] Figure 4 A schematic diagram of an idle address register provided by an embodiment of the present invention.

[0036] Figure 5 The address mapping diagram provided in the embodiment of the present invention is shown.

[0037] Figure 6 This is one of the read flow diagrams provided by the embodiment of the present invention.

[0038] Figure 7 The second schematic diagram of the reading process provided by the embodiment of the present invention.

[0039] Figure 8This is one of the write flow diagrams provided in the embodiment of the present invention.

[0040] Fig. 9 The second writing process diagram provided by the embodiment of the present invention.

[0041] Fig.10 A schematic diagram of an even data valid reg update process provided by an embodiment of the present invention.

[0042] Fig.11 A schematic diagram of the other data valid reg update process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] Some explanation about ping-pong sram implementation.

[0045] In order to avoid using dual-port SRAM in the prior art, two identical single-port SRAMs are usually used to simulate single-port SRAM (i.e., ping-pong SRAM). The implementation logic is as follows:

[0046] 1. Add a set bit fully connected flag (1-bit), 0 means the data in sram_0 is the latest, 1 means the data in sram_1 is the latest.

[0047] 2. Read and write enable generation logic:

[0048] a. Read the address and decode it to get a mask in the form of a one-hot code;

[0049] b. The obtained address mask is ANDed with flags;

[0050] c. Finally, we get a 1-bit result (read slt is used to represent this signal). True means the data is in sram_1, and false means the data is in sram_0.

[0051] 3. Update flags:

[0052] a. SRAM write enable = write enable &! read_slt, read slt negation means that writing cannot block reading, and writing must be diverted to another SRAM;

[0053] 4. Problems caused:

[0054] a. The area of ​​sram is doubled, and two identical srams are used;

[0055] b. It will pollute the read and write timing of SRAM at the same time.

[0056] In view of the problems existing in the prior art, the pseudo dual-port static random access memory provided by each embodiment of the present invention has two external ports, which are used to read data and write data respectively. It is internally composed of three single-port SRAMs (the set of each SRAM is half of the external set), an address mapping table, three fully associative mapped data valid registers and three idle address registers. Data writing will determine whether there is a port conflict with the read operation. In the case of a read-write conflict, the data writing will be diverted to other SRAM blocks, thereby realizing simultaneous reading and writing to the outside. Compared with the prior art, the SRAM in the structure provided by each embodiment of the present invention occupies a smaller area, which can take into account both timing and area.

[0057] In each embodiment of the pseudo dual-port SRAM provided by the present invention, the following expressions are involved, which have the following meanings: Internally: Control and device inside the pseudo dual-port. Externally: Externally refers to the top layer of the pseudo dual-port, where the input has a set of data lines and two sets of address lines, one port can only read, and the other port can only write, and the external display can process 1 read / 1 write request at the same time. Set: indicates the column address.

[0058] Figure 1 A schematic diagram of a pseudo dual-port SRAM structure provided by an embodiment of the present invention, such as Figure 1 As shown in the figure, the ports in the pseudo dual-port SRAM include DIN: data input; ADDR: addr; WEN: write enable; REN: read enable. The actual SRAM will contain other ports, which will not be listed here. The pseudo dual-port SRAM has two ports to the outside, which are used to read data and write data respectively. The pseudo dual-port SRAM includes: three single-port SRAMs, three data valid registers, three free address registers and an address mapping table.

[0059] Figure 2 A schematic diagram of three single-port SRAMs provided in an embodiment of the present invention, such as Figure 2As shown, the three single-port SRAMs include an even SRAM (even sram 114A), an odd SRAM (odd sram 114B) and other SRAM (othersram 114C). The internal column address set of even sram 114A, odd sram 114B and other sram 114C is half of the external set, for example, if the external set is 8, the internal set of even sram 114A, odd sram 114B and other sram 114C is 4.

[0060] Figure 3 A schematic diagram of a data valid flag register provided by an embodiment of the present invention, such as Figure 3 As shown, the pseudo dual-port SRAM includes three data valid registers, namely, even data valid register 115A, odd data valid register 115B and other data valid register 115C, and they correspond one-to-one to the three single-port SRAMs, that is, even data valid reg 115A corresponds to even sram 114A, odd data valid reg 115B corresponds to odd sram 114B, and other data valid reg 115C corresponds to othersram 114C.

[0061] Among them, the number of bits of even data valid reg 115A, odd data valid reg 115B and other data valid reg 115C is the same as the number of sets within the single-port SRAM, and the values ​​of the corresponding bits of the data valid registers are used to indicate the validity of the data in the storage address corresponding to each internal address index in the single-port SRAM.

[0062] Take even data valid reg 115A as an example. For example, if the internal set of a single-port SRAM is 4, then even data valid reg 115A has 4 bits, and their indexes are index=0, index=1, index=2, and index=3 respectively. The length of the corresponding bit in the data valid register is 1 bit, and the 1 bit is 1 to indicate that the data is valid, and the bit is 0 to indicate that the data is invalid. Each data valid register is initialized to all 0s, indicating that all data is invalid, and follows the specification of write first and read later.

[0063] Figure 4A schematic diagram of an idle address register provided by an embodiment of the present invention, such as Figure 4 As shown, the pseudo dual-port SRAM includes three idle address registers, namely, an even idle address register 116A, an odd idle address register 116B, and an other idle address register 116C, which correspond to three single-port SRAMs one by one. Each data valid reg of this idle address register corresponds to one. Each idle address register is used to indicate whether there is an idle table entry in the corresponding single-port SRAM, and the idle mapping address value to the outside, that is, the purpose of the idle address register is to record whether there is an idle table entry in even / odd / other and the idle mapping address value seen internally.

[0064] Among them, the free address register includes a 1-bit hasFree bit, which is 1 for free table entries and 0 for no free table entries; a 1-bit other bit, which is 1 for data stored in the other SRAM and 0 for data stored in the even SRAM or the odd SRAM; an n-bit index bit, which represents the external address index of each single-port SRAM, where the width of n is equal to log2 (set / 2), and set is an external set, for example, if the external set is 8, then the width of n is equal to 2. A 1-bit even / odd bit, which is 1 for data stored in the even SRAM and 0 for data stored in the odd SRAM.

[0065] Further, the other bit in the even idle address register 116A and the odd idle address register 116B is constantly 0, and the other bit of the other idle address register 116C is constantly 1; the even / odd bit of the even idle address register 116A is constantly 0, the even / odd bit of the odd idle address register 116B is constantly 1, and the even / odd bit of the other idle address register 116C is constantly 0.

[0066] Figure 5 The address mapping diagram provided in the embodiment of the present invention is as follows: Figure 5 As shown, the pseudo dual-port SRAM includes an address mapping table 160A. The entire mapping table is designed with three types of registers for recording the correspondence between the external address index and the internal address index in the three single-port SRAMs. The dotted line in the figure indicates that the actual circuit does not involve storage.

[0067] Specifically, the address mapping table 160A includes multiple rows, and the data in each row is used to represent the internal address index; the data in each row includes a 1-bit other bit, which is 1 and indicates that the data is stored in the other sram 114C, and is 0 and indicates that the data is stored in the even sram 114A or the odd sram 114B; an n-bit index bit, which represents the external address index of each single-port SRAM, and the width of n is equal to log2 (set / 2), and set is an external set; a 1-bit even / odd bit, which is 1 and indicates that the data is stored in the even sram 114A, and is 0 and indicates that the data is stored in the odd sram 114B; the number of rows in the address mapping table 160A is the same as the number of the external address indexes (for example, the external set is 8), and the data in each row of the address mapping table corresponds one-to-one to the external address index.

[0068] Figure 6 One of the read flow diagrams provided in the embodiment of the present invention, Figure 7 The second read flow diagram provided by the embodiment of the present invention is as follows: Figure 6 and Figure 7 As shown, the read enable is effective, first read the address mapping table 160A to obtain the internal mapping address; select the final data according to the read address, specifically:

[0069] When the external read enable is valid, searching the internal address index corresponding to the external address index based on the address mapping table;

[0070] When the other bit is 0 and the even / odd bit is 1, determine to read data from the storage address corresponding to the index bit in the even SRAM;

[0071] When the other bit is 0 and the even / odd bit is 0, determine to read data from the storage address corresponding to the index bit in the odd SRAM;

[0072] When the other bit is 1, it is determined to read data from the storage address corresponding to the index bit in the other SRAM.

[0073] Figure 8 One of the write flow diagrams provided in the embodiment of the present invention is as follows: Figure 8As shown, when the external read and write enables are valid at the same time, but the internal read and write addresses are not on the same single-port SRAM or only the write enable is valid, the address of the external write request is used as the address of the internal write request; when the external read and write enables are valid at the same time, and the internal read and write addresses are on the same single-port SRAM, it is determined to perform write diversion, and one is selected from the free address register as the internal write address.

[0074] At the end of the write operation:

[0075] Use the external write request address as an index and update the actual internal write address to the corresponding index position;

[0076] Use the actual internal write update address to update the corresponding single-port SRAM;

[0077] Use the data valid register corresponding to the external update address index to update the corresponding index position to 0;

[0078] Use the internal write to update the data valid register corresponding to the address index and update the corresponding index position to 1.

[0079] Specifically, write operations face two situations:

[0080] 1. External read and write enable are valid at the same time, and the internal read and write addresses are on the same SRAM

[0081] a. Write diversion is required at this time, and writing needs to select one from the free address register as the internal write address.

[0082] 2. The external read and write enable are valid at the same time, but the internal read and write addresses are not on the same SRAM or only the write enable is valid;

[0083] a. In this case, the address for the external write request is directly used as the address for the internal write request.

[0084] 3. After determining the address to be written internally, you need to update the following addresses:

[0085] a. Address mapping table 160A;

[0086] b. Write address mapping to the internal SRAM (one of 114A, 114B, 114C);

[0087] c. data valid reg 115A, 115B, 115C;

[0088] d. Idle address registers 116A, 116B, 116C.

[0089] The following is a further introduction through an example. Assume that there is a ping-pong SRAM with external set = 8, then the actual internal set = 4, and the index value ranges from 00 to 11.

[0090] like Figure 3 As shown, the bit in data valid reg is 0 to indicate invalid data, and 1 to indicate valid data. The set in index = set -1 in the figure is an internal set, corresponding to 4 in this embodiment.

[0091] like Figure 4 As shown, in the free address register:

[0092] 1. hasFree: 1-bit register, 1 indicates there is a free entry, 0 indicates there is no free entry;

[0093] 2. other sram: 1-bit register, constant register, cannot be written, can only be read;

[0094] a) 116A and 116B are constant at 0;

[0095] b) 116C is constant at 1;

[0096] 3. Index: address index;

[0097] 4. Even / odd: 1-bit register;

[0098] a) 116A is constant at 0;

[0099] b) 116B is always 1;

[0100] c) 116C is constant at 0.

[0101] Even data valid reg 115A (initialized state) is shown in Table 1.

[0102] Table 1

[0103]

[0104] even the idle address register 116A is shown in Table 2.

[0105] Table 2

[0106]

[0107] odd data valid reg 115B (initialization state) is shown in Table 3.

[0108] Table 3

[0109]

[0110] The odd sram free address 116B is shown in Table 4.

[0111] Table 4

[0112]

[0113] Other data valid reg 115C (initialization state) is shown in Table 5.

[0114] Table 5

[0115]

[0116] The other sram free address 116C is shown in Table 6.

[0117] Table 6

[0118]

[0119] The address mapping table 160A (initialized state) is as follows Figure 5 As shown, it is used to record the relationship between the external address index and the internal address index. It should be noted that the dashed box represents the index, and the actual hardware implementation does not involve the register, while the solid box involves the register. Table 7 is an example of the address mapping table 160A.

[0120] Table 7

[0121]

[0122] Under the initialization conditions in the above example, Example 1: the read request is invalid / the external write request is valid, the external write address is 2, and the write data is 4. Fig. 9 The second writing process diagram provided by the embodiment of the present invention is as follows: Fig. 9 As shown:

[0123] 1. The read request is invalid and there is no conflict between reading and writing;

[0124] 2. The write request is valid. The address of the external write request is 2. The address mapping table 160A is queried. The value corresponding to the index of the external address 2 is (other, index, even / odd) which is (0, 1, 0). The corresponding write update is in the even sram 114A.

[0125] 3. Update address mapping table 160A;

[0126] 4. Update even data valid reg 115A;

[0127] 5. Update even free address register 116A.

[0128] even data valid reg 115A is updated as shown in Table 8.

[0129] Table 8

[0130]

[0131] The even sram free address 116A is updated as shown in Table 9.

[0132] Table 9

[0133]

[0134] The address mapping table 160A is updated as shown in Table 10.

[0135] Table 10

[0136]

[0137] Also under the initialization conditions in the above example, Example 2: the external read request is valid, the external read address is 2 / the external write request is valid, the external write address is 4, and the write data is 8.

[0138] 1. Both sram reading and writing are valid.

[0139] 2. The read request queries the address mapping table 160A and obtains the read data in the even sram 114A.

[0140] 3. According to 1 and 2, there is a read-write conflict at this time, and the write request needs to be diverted.

[0141] 4. The actual address to be written must be selected from three free address registers.

[0142] a. The priority is other>even>odd.

[0143] b. The write bypass address found here is the idle address (1, 0, 0) corresponding to 116C.

[0144] 5. Update even data valid reg 115A with external write request address 4.

[0145] 6. Use the external write request address 4 to index the address mapping table 160A, and write the internal idle address 8 allocated by the write diversion into the register.

[0146] 7. Update other data valid reg 115C with the free address allocated by 116C.

[0147] 8. Use external write address 4 to index even data valid reg 115A. Because the actual write request is diverted to other sram 114C, the data in even sram 114A should be marked as invalid.

[0148] 9. Update other sram free address 116C.

[0149] 10. Update even sram free address.

[0150] Fig.10 A schematic diagram of an even data valid reg update process provided in an embodiment of the present invention, wherein the update of even data valid reg is shown in Table 11.

[0151] Table 11

[0152]

[0153] Fig.11 This is a schematic diagram of the other data valid reg update process provided by an embodiment of the present invention. The update of other data valid reg is shown in Table 12.

[0154] Table 12

[0155]

[0156] The address mapping table 160A is updated as shown in Table 13.

[0157] Table 13

[0158]

[0159] other free address 116C: Use the updated value of other data valid to find the location of the first 0, as shown in Table 14 and Table 15.

[0160] Table 14

[0161]

[0162] Table 15

[0163]

[0164] even free address 116A, as shown in Table 16 and Table 17.

[0165] Table 16

[0166]

[0167] Table 17

[0168]

[0169] The pseudo dual-port SRAM provided in the embodiments of the present invention has two external ports, which are used for reading data and writing data respectively. The interior of the SRAM is composed of three single-port SRAMs, an address mapping table, three fully associative mapped data valid registers and three idle address registers. The SRAM in the structure provided in each embodiment of the present invention occupies a smaller area, and both timing and area can be taken into account.

[0170] An embodiment of the present invention further provides a chip, which is applied to an electronic device. The chip includes the pseudo dual-port static random access memory SRAM provided by the above embodiments and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0171] It should be understood that the chip mentioned in the embodiment of the present invention may also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0172] The embodiment of the present invention further provides an electronic device. The electronic device includes the chip provided in the above embodiment. To avoid repetition, it will not be described here.

[0173] The electronic device provided by the embodiment of the present invention may include a handheld device, a vehicle-mounted device, etc. having an image processing function. For example, some electronic devices are: mobile phones, tablet computers, PDAs, laptop computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices, wearable devices, terminal devices in 5G networks or future evolved public land mobile communication networks (publicland mobile The embodiment of the present invention does not limit this.

[0174] As an example but not limitation, in an embodiment of the present invention, the electronic device may also be a wearable device. Wearable devices may also be referred to as wearable smart devices, which are a general term for wearable devices that are intelligently designed and developed using wearable technology for daily wear, such as glasses, gloves, watches, clothing, and shoes. A wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also powerful functions achieved through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include devices that are fully functional, large in size, and can achieve complete or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as devices that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various types of smart bracelets and smart jewelry for vital sign monitoring.

[0175] In addition, in the embodiments of the present invention, the electronic device may also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network that interconnects people and machines and things.

[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pseudo dual-port static random access memory SRAM, characterized in that: The pseudo dual-port static random access memory SRAM has two external ports, which are used for reading data and writing data respectively; The pseudo dual-port static random access memory SRAM comprises: Three single-port SRAMs, and the internal column address set of each single-port SRAM is half of the external column address set; the three single-port SRAMs include even SRAMs, odd SRAMs and other SRAMs; Three data valid registers, corresponding to the three single-port SRAMs respectively, the number of bits of each data valid register is the same as the number of sets within the single-port SRAM, and the values ​​of the corresponding bits of the data valid registers are respectively used to indicate the validity of the data in the storage address corresponding to each address index within the single-port SRAM; Three idle address registers, corresponding to the three single-port SRAMs respectively, each of the idle address registers is used to indicate whether there is an idle table entry in the corresponding single-port SRAM, and an external idle mapping address value; An address mapping table, used to record the correspondence between the external address index and the internal address index in the three single-port SRAMs; The length of the corresponding bit in the data valid register is 1 bit, and a bit position of 1 indicates that the data is valid, and a bit position of 0 indicates that the data is invalid; The free address register includes a 1-bit hasFree bit, which is 1 to indicate that there is a free table entry, and 0 to indicate that there is no free table entry; a 1-bit other bit, which is 1 to indicate that the data is stored in the other SRAM, and is 0 to indicate that the data is stored in the even SRAM or the odd SRAM; an n-bit index bit, which indicates the external address index of each single-port SRAM, and the width of n is equal to log2 (set / 2), and set is an external set; a 1-bit even / odd bit, which is 1 to indicate that the data is stored in the even SRAM, and is 0 to indicate that the data is stored in the odd SRAM; The three idle address registers include: an even idle address register, an odd idle address register and an other idle address register; The other bits in the even idle address register and the odd idle address register are constantly 0, and the other bits in the other idle address register are constantly 1; The even / odd bit of the even idle address register is constantly 0, the even / odd bit of the odd idle address register is constantly 1, and the even / odd bit of the other idle address register is constantly 0.

2. The pseudo dual-port static random access memory SRAM according to claim 1, characterized in that: The address mapping table includes multiple rows, and the data of each row is used to represent the internal address index; the data of each row includes a 1-bit other bit, which is 1 to indicate that the data is stored in the other SRAM, and is 0 to indicate that the data is stored in the even SRAM or the odd SRAM; an n-bit index bit, which indicates the external address index of each single-port SRAM, and the width of n is equal to log2 (set / 2), and set is an external set; a 1-bit even / odd bit, which is 1 to indicate that the data is stored in the even SRAM, and is 0 to indicate that the data is stored in the odd SRAM; The number of rows of the address mapping table is the same as the number of the external address indexes, and the data of each row of the address mapping table corresponds one-to-one to the external address index.

3. The pseudo dual-port static random access memory SRAM according to claim 1 or 2, characterized in that: When the external read enable is valid, searching the internal address index corresponding to the external address index based on the address mapping table; When the other bit is 1 and the even / odd bit is 1, determine to read data from the storage address corresponding to the index bit in the even SRAM; When the other bit is 1 and the even / odd bit is 0, determine to read data from the storage address corresponding to the index bit in the odd SRAM; When the other bit is 0, it is determined to read data from the storage address corresponding to the index bit in the other SRAM.

4. The pseudo dual-port static random access memory SRAM according to claim 1 or 2, characterized in that: When both external read and write enable are valid, but the internal read and write addresses are not on the same single-port SRAM or only the write enable is valid, the address of the external write request is used as the address of the internal write request; When the external read and write enables are valid at the same time and the internal read and write addresses are on the same single-port SRAM, it is determined to perform write splitting and one address is selected from the idle address register as the internal write address.

5. The pseudo dual-port static random access memory SRAM according to claim 4, characterized in that: At the end of the write operation: Use the external write request address as an index and update the actual internal write address to the corresponding index position; Use the actual internal write update address to update the corresponding single-port SRAM; Use the data valid register corresponding to the external update address index to update the corresponding index position to 0; Use the internal write to update the data valid register corresponding to the address index and update the corresponding index position to 1.

6. A chip, characterized in that: The invention comprises the pseudo dual-port static random access memory SRAM as described in any one of claims 1 to 5.

7. An electronic device, characterized in that: Comprising the chip as claimed in claim 6.

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