Chip packaging structure and chip packaging method

Abstract

The invention provides a chip packaging structure and a chip packaging method. The chip packaging structure comprises a glass substrate, a wiring layer, a first rewiring layer, a chip layer and a second rewiring layer. In the direction perpendicular to the glass substrate, the height of the first rewiring layer is 8-12 microns, the distance between adjacent conductive wires in the first rewiring layer is 1.5-2.5 microns, and compared with a combined structure of the rewiring layer and the silicon interposer, the first rewiring layer has higher circuit integration level and smaller circuit size. The chip layer and the glass substrate are electrically connected through the high-integration first rewiring layer, and the structure height is effectively reduced, so that the chip layers can be manufactured in batches under the influence of equipment height limitation, and the production efficiency is effectively improved. Meanwhile, compared with a combined structure of the rewiring layer and the silicon interposer, the chip layer and the glass substrate are electrically connected through the first rewiring layer, the signal transmission path can be effectively shortened, and the risk of signal loss is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] In semiconductor technology, packaging is an important part of the production and processing of semiconductor integrated circuit chips. It can not only place, fix, seal and protect the chip, but also enhance the electrical and thermal performance, and also realize the transmission of data and signals between the internal and external circuits of the chip. However, the existing chip packaging process still has the problem of low production efficiency. Summary of the invention

[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging structure and a chip packaging method.

[0004] In a first aspect, an embodiment of the present application provides a chip packaging structure, the chip packaging structure comprising:

[0005] A glass substrate, the glass substrate comprising a glass substrate, a through-glass hole penetrating the glass substrate, and a wiring layer located on a surface of a portion of the glass substrate via the through-glass hole;

[0006] a first redistribution layer, the first redistribution layer being located on one side of the glass substrate, the first redistribution layer being electrically connected to the wiring layer, wherein in a direction perpendicular to the glass substrate, a height of the first redistribution layer is 8 μm to 12 μm, and a spacing between adjacent conductive wirings in the first redistribution layer is 1.5 μm to 2.5 μm;

[0007] a chip layer, the chip layer being located on a side of the first redistribution layer away from the glass substrate, wherein the chip layer comprises at least one chip, and the chip is electrically connected to the first redistribution layer;

[0008] The second redistribution layer is located on a side of the glass substrate away from the first redistribution layer, and the second redistribution layer is electrically connected to the first redistribution layer through the routing layer.

[0009] In a possible implementation, a first conductive bump is disposed on a side of the first redistribution layer away from the glass substrate, and the chip is electrically connected via the first conductive bump, wherein a first distance between any two adjacent first conductive bumps is 2 μm-10 μm.

[0010] In a possible implementation, the chip packaging structure includes a first conductive connection layer and a second conductive connection layer;

[0011] A first conductive connection layer is located between the glass substrate and the first redistribution layer, and the first conductive connection layer includes a first conductive connection portion electrically connected to the routing layer;

[0012] The second conductive connection layer is located between the glass substrate and the second redistribution layer, and the second conductive connection layer includes a second conductive connection portion electrically connected to the routing layer.

[0013] In a possible implementation, the routing layer includes a seed layer and a metal layer, the seed layer is located on the inner wall of the through glass hole and at least a portion of the surface of the glass substrate, and the metal layer is located on a side of the seed layer away from the through glass hole.

[0014] In a possible implementation, the second redistribution layer further includes a second conductive bump on a side away from the glass substrate;

[0015] The chip packaging structure further includes a conductive ball located on a side of the second redistribution layer away from the glass substrate, and the conductive ball is electrically connected to the second conductive bump.

[0016] In a second aspect, an embodiment of the present application further provides a chip packaging method, the method comprising:

[0017] Providing a glass substrate, the glass substrate comprising a glass substrate, a through-glass hole penetrating the glass substrate, and a wiring layer located on a surface of a portion of the glass substrate via the through-glass hole;

[0018] A first redistribution layer electrically connected to the wiring layer is fabricated on one side of the glass substrate, wherein the height of the first redistribution layer is 8 μm to 12 μm in a direction perpendicular to the glass substrate, and the spacing between adjacent conductive wirings in the first redistribution layer is 1.5 μm to 2.5 μm;

[0019] Forming a second redistribution layer on a side of the glass substrate away from the first redistribution layer;

[0020] A chip layer is manufactured on a side of the first redistribution layer away from the glass substrate, wherein the chip layer includes at least one chip electrically connected to the first redistribution layer.

[0021] In a possible implementation manner, before the step of manufacturing a first redistribution layer electrically connected to the routing layer on one side of the glass substrate, the method further includes:

[0022] Providing a first substrate, and bonding the glass substrate to the first substrate;

[0023] A first conductive connection layer is formed on a side of the glass substrate away from the first substrate, wherein the first conductive connection layer includes a plurality of first conductive connection parts electrically connected to the wiring layer;

[0024] The step of manufacturing a first redistribution layer electrically connected to the wiring layer on one side of the glass substrate comprises:

[0025] A first redistribution layer is formed on a side of the first conductive connection layer away from the first substrate.

[0026] In a possible implementation, the step of forming a second redistribution layer on a side of the glass substrate away from the first redistribution layer includes:

[0027] Providing a second substrate, and bonding the second substrate to a side of the first redistribution layer away from the first substrate;

[0028] The first substrate is removed, and a second conductive connection layer is formed on a side of the glass substrate away from the second substrate, and a second redistribution layer is formed on a side of the second conductive connection layer away from the second substrate.

[0029] In a possible implementation, the step of manufacturing a chip layer on a side of the first redistribution layer away from the glass substrate includes:

[0030] Providing a third substrate, and bonding the third substrate to a side of the first redistribution wiring away from the second substrate;

[0031] The second substrate is removed, at least one chip is placed on the side of the first redistribution layer away from the third substrate, and a bottom filling glue layer is formed between the chip and the first redistribution layer to obtain the chip layer.

[0032] In a possible implementation manner, after the step of manufacturing a chip layer on a side of the first redistribution layer away from the glass substrate, the method further includes:

[0033] The third substrate is removed, and a ball planting process is performed on a side of the second redistribution layer away from the glass substrate to obtain conductive balls electrically connected to the second redistribution layer.

[0034] Based on any of the above aspects, the chip packaging structure and chip packaging method provided in the embodiment of the present application include a glass substrate, a routing layer, a first redistribution layer, a chip layer and a second redistribution layer. In the direction perpendicular to the glass substrate, the height of the first redistribution layer is 8μm to 12μm, and the spacing between adjacent conductive traces in the first redistribution layer is 1.5μm to 2.5μm. Relative to the combined structure of the redistribution layer and the silicon interposer, the first redistribution layer has a higher circuit integration and a smaller circuit size. The electrical connection between the chip layer and the glass substrate is achieved through the highly integrated first redistribution layer, which effectively reduces the height of the structure, so that the chip layer can be mass-produced without being affected by the height limit of the equipment, effectively improving production efficiency. At the same time, relative to the combined structure of the redistribution layer and the silicon interposer, the use of the first redistribution layer to achieve the electrical connection between the chip layer and the glass substrate can also effectively shorten the signal transmission path and reduce the risk of signal loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application Figure 1 ;

[0037] Figure 2 A schematic diagram of a chip packaging structure provided in an embodiment of the present application Figure 2 ;

[0038] Figure 3 A schematic diagram of a chip packaging structure provided in an embodiment of the present application Figure 3 ;

[0039] Figure 4 A schematic diagram of a chip packaging method provided in an embodiment of the present application Figure 1 ;

[0040] Figure 5 for Figure 4 The corresponding process diagram;

[0041] Figure 6 A schematic diagram of a chip packaging method provided in an embodiment of the present application Figure 2 ;

[0042] Figure 7 for Figure 6 Corresponding process diagram. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0045] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0046] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0047] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0048] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0049] The inventors found in specific practice that when packaging highly integrated chips such as system-on-chip (SoC chip) and high-bandwidth memory chip (HBM), a redistribution layer is usually made on both sides of the glass substrate 110. However, due to process limitations, the spacing between the conductive bumps on the redistribution layer is large, and the pin spacing of the highly integrated chip is too small, and a silicon interposer is often required as a transition, and the process is relatively cumbersome. However, the structural height after the introduction of the silicon interposer is relatively large. Affected by the height limitation of the equipment, the chip layer 130 cannot be produced in batches, and can only be prepared one by one using thermal compression bonding (TCB) equipment, resulting in low production efficiency. In addition, the introduction of the redistribution layer and the silicon interposer will also increase the path of signal transmission and increase the risk of signal loss.

[0050] To solve the problems in the prior art, please refer to Figure 1 An embodiment of the present application provides a chip packaging structure 10 , which includes a glass substrate 110 , a first redistribution layer 120 , a chip layer 130 and a second redistribution layer 140 .

[0051] The glass substrate 110 includes a glass substrate 111, a through-glass hole and a wiring layer 112, wherein the through-glass hole penetrates the glass substrate 111, and the wiring layer 112 is located on at least the surface of the glass substrate 111 via the through-glass hole, wherein the extension direction of the through-glass hole may be perpendicular to the surface where the glass substrate 111 is located. Specifically, the wiring layer 112 may include a seed layer and a metal layer, wherein the seed layer is located on the inner wall of the through-glass hole and at least a portion of the surface of the glass substrate 110, and the metal layer is located on a side of the seed layer away from the through-glass hole. In addition, the glass substrate 110 may further include an ABF filling layer 113, wherein the ABF filling layer 113 may be located in the through-glass hole and on the surface of the glass substrate 111, wherein the ABF filling layer 113 at least partially exposes the wiring layer 112. Exemplarily, the material of the ABF filling layer 113 includes, but is not limited to, ABF (Ajinomoto Build-up Film) material.

[0052] The first redistribution layer 120 may be located on one side of the glass substrate 110, the first redistribution layer 120 is electrically connected to the routing layer 112, and the spacing between adjacent conductive routings in the first redistribution layer 120 is 1.5 μm to 2.5 μm, which can achieve higher circuit integration and smaller circuit size. Wherein, in the direction perpendicular to the glass substrate 110, the height of the first redistribution layer 120 is 8 μm to 12 μm, and illustratively, in the direction perpendicular to the glass substrate 110, the height of the first redistribution layer 120 may be 8 μm, 8.5 μm, 9 μm, 10 μm, 11 μm, 11.5 μm, and 12 μm, etc. Preferably, in the direction perpendicular to the glass substrate 110, the height of the first redistribution layer 120 is 10 μm.

[0053] The chip layer 130 can be located on a side of the first redistribution layer 120 away from the glass substrate 110, wherein the chip layer 130 includes at least one chip 131, and the pins of the chip 131 can be electrically connected by the first conductive bump, that is, the chip is flipped on the first redistribution layer 120, which can not only shorten the transmission path of the signal, but also make the chip packaging structure 10 more compact and improve the integration of the chip. Exemplarily, the chip 131 includes highly integrated chips such as system-on-chip (SoC chip) and high-bandwidth memory chip (HBM). In addition, the chip packaging structure 10 can also include a bottom filling glue layer 150 located between the chip 131 and the first redistribution layer 120, and the bottom filling glue layer 150 can improve the mechanical connection strength between the chip 131 and the first redistribution layer 120, and protect the chip 131 from physical loss.

[0054] The second redistribution layer 140 is located on a side of the glass substrate 110 away from the first redistribution layer 120 . The second redistribution layer 140 is electrically connected to the first redistribution layer 120 through the routing layer 112 .

[0055] In the above structure, in the direction perpendicular to the glass substrate 110, the height of the first redistribution layer 120 is 8μm to 12μm, and the spacing between adjacent conductive traces in the first redistribution layer 120 is 1.5μm to 2.5μm. Compared with the combined structure of the redistribution layer and the silicon interposer, the first redistribution layer 120 has a higher circuit integration and a smaller circuit size. The highly integrated first redistribution layer 120 is used to realize the electrical connection between the chip layer 130 and the glass substrate 110, which effectively reduces the height of the structure, so that the chip layer 130 can be mass-produced without being affected by the height limit of the equipment, effectively improving the production efficiency. At the same time, compared with the combined structure of the redistribution layer and the silicon interposer, the use of the first redistribution layer 120 to realize the electrical connection between the chip layer 130 and the glass substrate 110 can also effectively shorten the signal transmission path and reduce the risk of signal loss.

[0056] For further information, please refer to Figure 2 , a first conductive bump 121 is provided on the side of the first redistribution layer 120 away from the glass substrate 110, and the chip 131 can be electrically connected through the first conductive bump 121. Among them, the distance between any two adjacent first conductive bumps 121 is 35μm-45μm. For example, the distance between any two adjacent first conductive bumps 121 can be 35μm, 36μm, 37μm, 40μm, 43μm, 44μm and 45μm, etc. Preferably, the distance between any two adjacent first conductive bumps 121 is 40μm. It should be noted that, since the first redistribution layer 120 has a higher circuit integration and a smaller circuit size, the spacing of the first conductive bumps 121 can be adjusted according to the integration of the specific chip 131, thereby replacing the silicon interposer and simplifying the process. In addition, the orthographic projection shape of the first conductive bump 121 on the glass substrate 110 includes a circle, a square, etc., and the size of the orthographic projection shape can be 20μm-30μm. Preferably, the shape of the first conductive bump 121 is cylindrical, and the size of the orthographic projection shape on the glass substrate 110 can be 25μm.

[0057] In one possible implementation, please refer again to Figure 2 The chip packaging structure 10 may further include a first conductive connection layer 161 and a second conductive connection layer 162. The first conductive connection layer 161 is located between the glass substrate 110 and the first redistribution layer 120, and the second conductive connection layer 162 is located between the glass substrate 110 and the second redistribution layer 140. The first conductive connection layer 161 includes a first conductive connection portion 1611 electrically connected to the wiring layer 112 and a first plastic sealing layer located between the first conductive connection portions 1611. Similarly, the second conductive connection layer 162 includes a second conductive connection portion 1621 electrically connected to the wiring layer 112 and a second plastic sealing layer located between the second conductive connection portions 1621.

[0058] For further information, please refer to Figure 3 The chip packaging structure 10 further includes a conductive ball 170 located on the side of the second redistribution layer 140 away from the glass substrate 110. The side of the second redistribution layer 140 away from the glass substrate 110 further includes a second conductive bump, and the conductive ball 170 is electrically connected to the second conductive bump.

[0059] Based on the same inventive concept, the present application also provides a chip packaging method, for details, please refer to Figure 4 and Figure 5 , Figure 4 Schematic diagram of the chip packaging method. Figure 5 for Figure 4 The corresponding process diagram. Figure 4 and Figure 5Each step of the chip packaging method is described in detail.

[0060] Step S110: providing a glass substrate.

[0061] Specifically, the glass substrate 110 includes a glass substrate 111, a through-glass hole and a wiring layer 112, wherein the through-glass hole penetrates the glass substrate 111, and the wiring layer 112 is located on at least the surface of the glass substrate 111 via the through-glass hole, wherein the extension direction of the through-glass hole may be perpendicular to the surface where the glass substrate 111 is located. Specifically, the wiring layer 112 may include a seed layer and a metal layer, wherein the seed layer is located on the inner wall of the through-glass hole and at least a portion of the surface of the glass substrate 110, and the metal layer is located on a side of the seed layer away from the through-glass hole. In addition, the glass substrate 110 may further include an ABF filling layer 113, wherein the ABF filling layer 113 may be located in the through-glass hole and on the surface of the glass substrate 111, wherein the ABF filling layer 113 at least partially exposes the wiring layer 112. Exemplarily, the material of the ABF filling layer 113 includes, but is not limited to, ABF (Ajinomoto Build-up Film) material.

[0062] Step S120: forming a first redistribution layer electrically connected to the wiring layer on one side of the glass substrate.

[0063] In this step, the first redistribution layer 120 has a plurality of conductive traces connected to the trace layer 112, and the spacing between adjacent conductive traces is 1.5μm-2.5μm, with higher circuit integration and smaller circuit size. For example, the spacing between adjacent conductive traces can be 1.5μm, 1.75μm, 1.9μm, 2μm, 2.2μm, 2.35μm and 2.5μm, etc. Preferably, the spacing between adjacent conductive traces is 2μm. Wherein, in the direction perpendicular to the glass substrate 110, the height of the first redistribution layer 120 is 8μm to 12μm. For example, in the direction perpendicular to the glass substrate 110, the height of the first redistribution layer 120 can be 8μm, 8.5μm, 9μm, 10μm, 11μm, 11.5μm and 12μm, etc. Preferably, in the direction perpendicular to the glass substrate 110, the height of the first redistribution layer 120 is 10μm.

[0064] In addition, a first conductive bump 121 is further provided on the side of the first redistribution layer 120 away from the glass substrate 110, and the distance between any two adjacent first conductive bumps 121 is 35μm-45μm. For example, the distance between any two adjacent first conductive bumps 121 can be 35μm, 36μm, 37μm, 40μm, 43μm, 44μm and 45μm, etc. Preferably, the distance between any two adjacent first conductive bumps 121 is 40μm. It should be noted that, since the first redistribution layer 120 has a higher circuit integration and a smaller circuit size, the spacing of the first conductive bumps 121 can be adjusted according to the integration of the specific chip 131, thereby replacing the silicon interposer and simplifying the process.

[0065] Step S130: forming a second redistribution layer on a side of the glass substrate away from the first redistribution layer.

[0066] In this step, a second conductive bump is disposed on a side of the second redistribution layer 140 away from the glass substrate 110 .

[0067] Step S140: manufacturing a chip layer on a side of the first redistribution layer away from the glass substrate.

[0068] In this step, at least one chip 131 may be placed on the side of the first redistribution layer 120 away from the glass substrate 110, and then a bottom filling glue layer 150 is made to fix the first redistribution layer 120 and the chip 131. Exemplarily, the chip 131 includes a highly integrated chip such as a system-on-chip (SoC chip) and a high-bandwidth memory chip (HBM).

[0069] In this embodiment, the electrical connection between the chip layer 130 and the glass substrate 110 is realized through the highly integrated first redistribution layer 120, which effectively reduces the height of the structure, so that the chip layer 130 can be mass-produced without being affected by the height limit of the equipment, effectively improving the production efficiency. At the same time, compared with the combined structure of the redistribution layer and the silicon interposer, the use of the first redistribution layer 120 to realize the electrical connection between the chip layer 130 and the glass substrate 110 can also effectively shorten the signal transmission path and reduce the risk of signal loss.

[0070] In a possible implementation, before step S120, the chip packaging method provided in the embodiment of the present application may further include the following steps.

[0071] Step S111: providing a first substrate, and bonding a glass substrate to the first substrate.

[0072] In this step, a first adhesive layer 211 may be formed on one side of the first substrate 210 , and the glass substrate 110 may be bonded to the first substrate 210 via the first adhesive layer 211 , wherein the first adhesive layer 211 may be made of a photodegradable bonding material or a laser degradable bonding material.

[0073] Step S112: forming a first conductive connection layer on a side of the glass substrate away from the first substrate.

[0074] The first conductive connection layer 161 includes a plurality of first conductive connection portions 1611 electrically connected to the wiring layer 112 , and a first plastic packaging layer located between adjacent first conductive connection portions 1611 .

[0075] Further, step S130 can be implemented by the following method.

[0076] Step S131: providing a second substrate, and bonding the second substrate to a side of the first redistribution layer away from the first substrate.

[0077] In this step, a second adhesive layer 221 can be made on one side of the second substrate 220, and the second substrate 220 can be bonded to the side of the first redistribution layer 120 away from the first substrate 210 through the second adhesive layer 221, wherein the second adhesive layer 221 can be made of a photodegradable bonding material or a laser degradable bonding material.

[0078] Step S132: removing the first substrate, and forming a second conductive connection layer on a side of the glass substrate away from the second substrate, and forming a second redistribution layer on a side of the second conductive connection layer away from the second substrate.

[0079] In this step, the first substrate 210 can be removed by heating or laser, and a suitable debonding method can be selected according to the material of the first adhesive layer 211. Next, a second conductive connection layer 162 is made on the side of the glass substrate 110 away from the second substrate 220. The second conductive connection layer 162 includes a second conductive connection part 1621 electrically connected to the wiring layer 112, and a second plastic sealing layer located around the second conductive connection part 1621. Finally, an ABF material is selected to make a second redistribution layer on the side of the second conductive connection layer away from the second substrate.

[0080] Furthermore, step S140 can be implemented in the following manner.

[0081] Step S141: providing a third substrate, and bonding the third substrate to a side of the first redistribution pattern away from the second substrate.

[0082] In this step, a third adhesive layer can be first made on the third substrate 230, and then the glass substrate 110 with the second redistribution layer 140 made thereon can be transferred to the side of the third adhesive layer away from the third substrate 230, and the third substrate 230 can be bonded to the side of the first redistribution layer away from the second substrate 220 through the third adhesive layer, wherein the third adhesive layer can be made of a photodegradable bonding material or a laser degradable bonding material.

[0083] Step S142: remove the second substrate, place at least one chip on the side of the first redistribution layer away from the third substrate, and form a bottom filling glue layer between the chip and the first redistribution layer to obtain a chip layer.

[0084] In this step, the second substrate 220 can be removed by removing the second adhesive layer 221 by heating or laser, and a suitable debonding method can be selected according to the material of the first adhesive layer 211. Next, at least one chip 131 is placed on the side of the first redistribution layer 120 away from the third substrate 230, wherein the pins of the chip 131 can be connected to the first conductive bumps on the first redistribution layer 120 to shorten the signal transmission path. Finally, according to the material properties (such as thermal expansion coefficient) of the chip 131 and the first redistribution layer 120, a suitable bottom filling material is selected, and the bottom filling material is dotted between the chip 131 and the first redistribution layer 120, and finally filled in the gap between the chip 131 and the first redistribution layer 120 by heating, and the bottom filling material is cooled and solidified to form a bottom filling glue layer 150. Exemplarily, the chip 131 may include a system on chip (SoC) and a high bandwidth memory (HBM) chip.

[0085] In addition, after step S140, the chip packaging method provided in the embodiment of the present application may further include the following steps.

[0086] Step 150: remove the third substrate, and perform ball planting on the side of the second redistribution layer away from the glass substrate to obtain conductive balls electrically connected to the second redistribution layer.

[0087] Specifically, the third substrate 230 can be removed by first removing the third adhesive layer by heating or laser, and then ball planting is performed on the side of the second redistribution layer 140 away from the glass substrate 110 to obtain conductive balls electrically connected to the second conductive bumps.

[0088] In summary, the embodiments of the present application provide a chip packaging structure and a chip packaging method. In the direction perpendicular to the glass substrate, the height of the first redistribution layer is 8μm to 12μm, and the spacing between adjacent conductive traces in the first redistribution layer is 1.5μm to 2.5μm. Compared with the combined structure of the redistribution layer and the silicon interposer, the first redistribution layer has a higher circuit integration and a smaller circuit size. The electrical connection between the chip layer and the glass substrate is achieved through the highly integrated first redistribution layer, which effectively reduces the height of the structure, so that the chip layer can be mass-produced without being affected by the height limit of the equipment, effectively improving production efficiency. At the same time, compared with the combined structure of the redistribution layer and the silicon interposer, the use of the first redistribution layer to achieve the electrical connection between the chip layer and the glass substrate can also effectively shorten the signal transmission path and reduce the risk of signal loss.

[0089] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: A glass substrate, the glass substrate comprising a glass substrate, a through-glass hole penetrating the glass substrate, and a wiring layer located on a surface of a portion of the glass substrate via the through-glass hole; a first redistribution layer, the first redistribution layer being located on one side of the glass substrate, the first redistribution layer being electrically connected to the wiring layer, wherein in a direction perpendicular to the glass substrate, a height of the first redistribution layer is 8 μm to 12 μm, and a spacing between adjacent conductive wirings in the first redistribution layer is 1.5 μm to 2.5 μm; a chip layer, the chip layer being located on a side of the first redistribution layer away from the glass substrate, wherein the chip layer comprises at least one chip, and the chip is electrically connected to the first redistribution layer; The second redistribution layer is located on a side of the glass substrate away from the first redistribution layer, and the second redistribution layer is electrically connected to the first redistribution layer through the routing layer.

2. The chip packaging structure according to claim 1, characterized in that: A first conductive bump is disposed on a side of the first redistribution layer away from the glass substrate, and the chip is electrically connected via the first conductive bump, wherein a first distance between any two adjacent first conductive bumps is 2 μm-10 μm.

3. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure includes a first conductive connection layer and a second conductive connection layer; A first conductive connection layer is located between the glass substrate and the first redistribution layer, and the first conductive connection layer includes a first conductive connection portion electrically connected to the routing layer; The second conductive connection layer is located between the glass substrate and the second redistribution layer, and the second conductive connection layer includes a second conductive connection portion electrically connected to the routing layer.

4. The chip packaging structure according to claim 1, characterized in that: The routing layer includes a seed layer and a metal layer, the seed layer is located on the inner wall of the through glass hole and at least a portion of the surface of the glass substrate, and the metal layer is located on a side of the seed layer away from the through glass hole.

5. The chip packaging structure according to claim 1, characterized in that: The second redistribution layer further comprises a second conductive bump on a side away from the glass substrate; The chip packaging structure further includes a conductive ball located on a side of the second redistribution layer away from the glass substrate, and the conductive ball is electrically connected to the second conductive bump.

6. A chip packaging method, characterized in that: The method comprises: Providing a glass substrate, the glass substrate comprising a glass substrate, a through-glass hole penetrating the glass substrate, and a wiring layer located on a surface of a portion of the glass substrate via the through-glass hole; A first redistribution layer electrically connected to the wiring layer is fabricated on one side of the glass substrate, wherein the height of the first redistribution layer is 8 μm to 12 μm in a direction perpendicular to the glass substrate, and the spacing between adjacent conductive wirings in the first redistribution layer is 1.5 μm to 2.5 μm; Forming a second redistribution layer on a side of the glass substrate away from the first redistribution layer; A chip layer is manufactured on a side of the first redistribution layer away from the glass substrate, wherein the chip layer includes at least one chip electrically connected to the first redistribution layer.

7. The chip packaging method according to claim 6, characterized in that: Before the step of manufacturing a first redistribution layer electrically connected to the wiring layer on one side of the glass substrate, the method further includes: Providing a first substrate, and bonding the glass substrate to the first substrate; A first conductive connection layer is formed on a side of the glass substrate away from the first substrate, wherein the first conductive connection layer includes a plurality of first conductive connection parts electrically connected to the wiring layer; The step of manufacturing a first redistribution layer electrically connected to the wiring layer on one side of the glass substrate comprises: A first redistribution layer is formed on a side of the first conductive connection layer away from the first substrate.

8. The chip packaging method according to claim 7, characterized in that: The step of forming a second redistribution layer on a side of the glass substrate away from the first redistribution layer comprises: Providing a second substrate, and bonding the second substrate to a side of the first redistribution layer away from the first substrate; The first substrate is removed, and a second conductive connection layer is formed on a side of the glass substrate away from the second substrate, and a second redistribution layer is formed on a side of the second conductive connection layer away from the second substrate.

9. The chip packaging method according to claim 8, characterized in that: The step of manufacturing a chip layer on a side of the first redistribution layer away from the glass substrate comprises: Providing a third substrate, and bonding the third substrate to a side of the first redistribution wiring away from the second substrate; The second substrate is removed, at least one chip is placed on the side of the first redistribution layer away from the third substrate, and a bottom filling glue layer is formed between the chip and the first redistribution layer to obtain the chip layer.

10. The chip packaging method according to claim 9, characterized in that: After the step of manufacturing a chip layer on a side of the first redistribution layer away from the glass substrate, the method further comprises: The third substrate is removed, and a ball planting process is performed on a side of the second redistribution layer away from the glass substrate to obtain conductive balls electrically connected to the second redistribution layer.

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