Process window electrical property test structure, assembly and test method for polycrystalline silicon gate spacing

Abstract

The invention provides a process window electrical test structure for polycrystalline silicon grid spacing, which is placed in a cutting channel and at least comprises a formal test structure, the formal test structure comprises an N-well resistance reference test structure and a polycrystalline silicon grid resistance test structure, the N-well resistance reference test structure comprises a rectangular N-well resistor in an active region, and the polycrystalline silicon grid resistance test structure comprises a polycrystalline silicon grid spacing. The first test leading-out end and the second test leading-out end are located at the two ends of the N-well resistor and electrically communicated with the first test bonding pad and the second test bonding pad respectively; the polycrystalline silicon grid resistance test structure comprises an N-well resistance reference test structure, at least two long-strip-shaped polycrystalline silicon arranged in parallel above the N-well resistance, and a third test leading-out end and a fourth test leading-out end which are arranged at the two ends of the N-well resistance and the two polycrystalline silicon; and the third test leading-out end and the fourth test leading-out end are electrically communicated with the third test bonding pad and the fourth test bonding pad respectively. According to the scheme, nondestructive testing of the preparation process of the metal silicide between the polycrystalline silicon grids is realized, the cost is reduced, and the monitoring convenience is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a process window electrical property test structure, component and test method for polysilicon gate spacing. Background Art

[0002] In the field of semiconductor chips, in order to save area and reduce costs, when designing semiconductor chips, MOS in series often do not have ohmic contact holes (CT) in the middle, and the distance between polysilicon gates (Poly) will be set to the minimum value specified by the design rules. At the same time, it is also necessary to ensure that sidewalls (spacers) and metal silicides (silicide) can be formed between the polysilicon gates.

[0003] However, due to the sidewall being too wide, the residual silicon oxide in the middle of the sidewall not being cleaned up, and the poor hole-filling capability of the process when filling the metal material, the metal material cannot enter the potential non-metal silicide area (between the two polysilicon gate sidewalls) to contact the silicon, and thus cannot form silicide in this area as expected, resulting in abnormal series resistance, affecting the chip function and performance. In the prior art, the metal silicide between the polysilicon gate sidewalls of the series-connected MOS is generally monitored by slicing, but slicing will cause wafer damage and is costly, which is not conducive to industrial production. Summary of the invention

[0004] In view of the above problems, the present invention provides a process window electrical test structure, component and test method for polysilicon gate spacing to solve the problem that when monitoring whether metal silicide is formed between MOS devices connected in series by slicing, wafer damage will be caused and the cost is high.

[0005] According to a first aspect of the present invention, a process window electrical test structure of a polysilicon gate spacing is provided, the process window electrical test structure is placed in a cutting path of a wafer, and includes at least one formal test structure, the formal test structure includes an N-well resistance reference test structure and a polysilicon gate resistance test structure, the N-well resistance reference test structure and the polysilicon gate resistance test structure are arranged in parallel up and down in the cutting path, the N-well resistance reference test structure is provided with a first test pad and a second test pad, the polysilicon gate resistance test structure is provided with a third test pad and a fourth test pad, the first test pad, the third test pad, the second test pad and the fourth test pad are arranged alternately along the cutting path direction, wherein:

[0006] The N-well resistance reference test structure comprises:

[0007] An N-well resistor in the active area, the N-well resistor is rectangular, and a first test lead-out terminal and a second test lead-out terminal are located at two ends of the rectangular N-well resistor, the first test lead-out terminal and the second test lead-out terminal are electrically connected to the first test pad and the second test pad, respectively;

[0008] The polysilicon gate resistance test structure comprises:

[0009] The N-well resistor reference test structure and at least two long strips of polysilicon located above the N-well resistor and a third test lead-in and a fourth test lead-in located at both ends of the N-well resistor and the two long strips of polysilicon, the two long strips of polysilicon are arranged in parallel, the spacing between the two polysilicons is located between the third test lead-in and the fourth test lead-in, and the third test lead-in and the fourth test lead-in are electrically connected to the third test pad and the fourth test pad, respectively.

[0010] Optionally, the two long strip-shaped polysilicon sidewalls are both formed with side walls, and the distance between the two polysilicon strips is the distance between the side walls.

[0011] Optionally, the test structure further includes a virtual test structure, which is symmetrically arranged at upper and lower positions of the formal test structure; the structure of the virtual test structure is the same as that of the formal test structure.

[0012] According to a second aspect of the present invention, a method for manufacturing a process window electrical test structure of a polysilicon gate spacing is provided, which is used to prepare the process window electrical test structure of the polysilicon gate spacing described in the first aspect of the present invention, comprising:

[0013] Forming the N-well resistance reference test structure includes:

[0014] forming an N-well resistor in an active area within the cutting path, wherein the N-well resistor is rectangular;

[0015] Forming first and second test leads at two ends of the rectangular N-well resistor respectively;

[0016] The polysilicon gate resistance test structure is fabricated in the cutting path and is arranged in parallel with the N-well resistance reference test structure, including:

[0017] At least two strips of polysilicon are formed in the area above the N-well resistor; the two strips of polysilicon are arranged in parallel;

[0018] A third test lead-out terminal and a fourth test lead-out terminal are formed at both ends of the N-well resistor and the two long strips of polysilicon respectively, and the distance between the two polysilicon strips is located between the third test lead-out terminal and the fourth test lead-out terminal.

[0019] According to a third aspect of the present invention, a contact layer measurement method is provided, comprising:

[0020] Detecting the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure in the process window electrical property test structure of the polysilicon gate spacing according to any one of the third aspects of the present invention;

[0021] Whether the metal silicide layer is formed between the two long strips of polysilicon is determined according to the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure.

[0022] According to a fourth aspect of the present invention, a process window electrical test component for polysilicon gate spacing is provided, comprising a plurality of process window electrical test structures for polysilicon gate spacing as described in any one of the first aspect of the present invention, wherein the spacings between the polysilicon are different in the plurality of process window electrical test structures for polysilicon gate spacing.

[0023] According to a fifth aspect of the present invention, a method for determining a minimum spacing of a semiconductor process is provided, comprising:

[0024] Obtaining the spacing between polysilicon corresponding to the process window electrical property test structures of the polysilicon gate spacing as described in the first aspect of the present invention;

[0025] Measuring the total resistance value of the resistance of the process window electrical property test structure of each polysilicon gate spacing;

[0026] According to a plurality of spacings between the polysilicon and a plurality of total resistance values, a first relationship model between the spacings between the polysilicon and the corresponding total resistance values ​​is obtained;

[0027] According to the first relationship model, the value of the minimum spacing is determined.

[0028] Optionally, the method further includes:

[0029] Obtaining slices of the process window electrical test structures of the plurality of polysilicon gate spacings;

[0030] The value of the minimum distance is determined according to the plurality of slices and the first relationship model.

[0031] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0032] In the process window electrical property test structure of the polysilicon gate spacing provided by the technical solution of the present invention, a test structure including a polysilicon gate resistance test structure and an N-well resistance reference test structure is set, wherein, compared with the N-well resistance reference test structure, the polysilicon gate resistance test structure is provided with at least two long strips of polysilicon above the N-well resistance, so that in the subsequent process, the N-well resistance of the N-well resistance reference test structure will be completely covered with a metal silicide barrier layer (SAB, Salicide-block), resulting in the area on the N-well resistance being a metal silicide-free area; while in the polysilicon gate resistance test structure, the area covered by polysilicon will not form Metal silicide, the resistance value of this area is equivalent to the resistance value of the N-well resistor covered by the metal silicide barrier layer, and only the area between the two polysilicons is not covered by the metal silicide barrier layer, and metal silicide will be formed in this area; therefore, only the area between the two polysilicons may affect the resistance value of the polysilicon gate resistance test structure; and the polysilicon gate resistance test structure and the N-well resistance reference test structure are respectively led out through the pad and the pad lead-out end, and the resistance between the polysilicon gate resistance test structure and the N-well resistance reference test structure is tested, and the resistance between the two is compared, so that the purpose of non-destructive testing of the metal silicide preparation process between the polysilicon gates can be achieved by using the electrical test method. Thereby, it is possible to monitor whether metal silicide is formed between the two polysilicons without slicing, which reduces the cost, improves the convenience of monitoring, and does not cause wafer damage.

[0033] Furthermore, a method for determining the minimum spacing of a semiconductor process is also provided, by setting a number of process window electrical test structures of polysilicon gate spacing, and setting the spacing between polysilicon in the polysilicon gate resistance test structures corresponding to the process window electrical test structures of the polysilicon gate spacing to different sizes; after obtaining the spacing between the polysilicon and the total resistance values ​​corresponding to the process window electrical test structures of the polysilicon gate spacing, a first relationship model of the change of the spacing between the polysilicon is established according to the spacing between the polysilicon and the total resistance values, and the value of the minimum spacing can be determined according to the first relationship model. Therefore, when developing a new node and establishing a new production line, the method provided by the present invention can determine the minimum spacing under the process node, providing a reference for monitoring the spacing between polysilicon in the subsequent production stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The schematic diagram is a structural diagram of two adjacent polysilicon pieces in a series MOS device;

[0035] Figure 2 A schematic diagram of a process window electrical property test structure of a polysilicon gate spacing provided in one embodiment of the present invention;

[0036] Figure 3 A schematic diagram of a pad structure of a process window electrical test structure for a polysilicon gate spacing provided by an embodiment of the present invention;

[0037] Figure 4 for Figure 2 The process window electrical test structure of the polysilicon gate spacing shown is a cross-sectional view along p1-p1' (a), a cross-sectional view along p2-p2' (b), and a cross-sectional view along p3-p3' (c);

[0038] Figure 5 for Figure 2 A cross-sectional view of a process window electrical test structure for a polysilicon gate spacing along the line p4-p4' is shown;

[0039] Figure 6 A flow chart of a method for determining a minimum spacing of a semiconductor process provided by an embodiment of the present invention;

[0040] Figure 7 A schematic diagram of a process window electrical property test structure for polysilicon gate spacing provided by another embodiment of the present invention;

[0041] Figure 8 A first relationship model between the spacing between polysilicon and the corresponding total resistance is provided in one embodiment of the present invention.

[0042] Description of reference numerals:

[0043] 10-potentially metal silicide-free area;

[0044] 30-substrate;

[0045] 40-polysilicon;

[0046] 50-side wall;

[0047] 60-metal silicide-free region;

[0048] 70-metal silicide barrier layer;

[0049] 80-resistance zone;

[0050] 1- Electrical test structure of process window of polysilicon gate spacing;

[0051] 11- Formal test structure;

[0052] 111- polysilicon gate resistance test structure;

[0053] 1111-third test pad;

[0054] 1112- fourth test pad;

[0055] 1113-polysilicon;

[0056] 1114-third test lead terminal;

[0057] 1115- fourth test lead terminal;

[0058] 112-N well resistance reference test structure;

[0059] 1121-first test pad;

[0060] 1122-second test pad;

[0061] 1123-N well resistor;

[0062] 1124-first test lead-out terminal;

[0063] 1125-second test lead terminal;

[0064] 101-substrate;

[0065] 102-P well region;

[0066] 103-isolation structure;

[0067] 104-N-type heavily doped region;

[0068] 12- Virtual test structure. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] As described in the background art, the technical solution of the present invention aims to solve the problem of causing wafer damage and high cost when monitoring whether metal silicide is formed between MOS devices connected in series by slicing.

[0072] Figure 1 The figure is a schematic diagram illustrating the structure of two adjacent polysilicon pieces in a series MOS device.

[0073] Please refer to Figure 1 The structure includes two polysilicon blocks 40 located on a substrate 30, and the sidewalls of the polysilicon blocks are formed with sidewalls 50. When the two polysilicon blocks are very close, even at the minimum space, for example Figure 1 As for the potential non-silicide region 10 shown, since sidewalls (spacers) need to be formed on both sides of the polysilicon, the space between the two will be occupied to form metal silicide. At the 0.18um node, the minimum spacing (Polyminimum space) between the polysilicon gates will be greater than the sum of the sidewalls on both sides. Therefore, under normal circumstances, metal silicide can and should be formed in the potential non-silicide region 10. However, during the process, the sidewalls may be too wide, or the oxide in the middle of the sidewalls may not be completely removed, or when filling metal materials (such as Co, Ti, NiPt, etc.), due to the poor hole filling ability of the process, the metal material cannot enter the potential non-silicide region 10 to contact silicon, resulting in the inability to form metal silicide in this area as expected, which in turn leads to abnormal series resistance, affecting the function and performance of the chip.

[0074] From this, we can conclude that according to the deduction that the offset of the spacing between polysilicon (poly space) causes the metal silicide to fail to grow normally and leads to abnormal series resistance, the stability of the poly space can be detected by measuring the resistance change of the area between polysilicon.

[0075] However, due to the lack of in-line measurement in the prior art, it is necessary to set up multiple sets of experiments with different polyspaces and determine the minimum Poly spacing and process window through repeated slicing. In the later stage, it is also necessary to monitor the stability of the process through slicing. This method will cause wafer damage and is costly, which is not conducive to industrial production.

[0076] The methods and problems of the prior art have triggered the inventors of the present application to think that if there is a method for electrical measurement: using electrical parameters as characteristic parameters reflecting whether metal silicide is formed in the potential metal-free silicide region 10, in the early stage of developing new technology nodes and establishing production lines, by continuously collecting these electrical parameters, a distribution diagram of the electrical parameters changing with the poly space is established, and the minimum gate spacing and process window are determined while the normal range of the parameter is determined. Then, in the later stage, the stability of the process can be determined by the electrical parameters, which can achieve cost savings compared to the traditional slicing method.

[0077] In view of this, an embodiment of the present invention provides a process window electrical test structure of a polysilicon gate spacing, wherein the process window electrical test structure is placed in a cutting path of a wafer, and comprises at least one formal test structure, wherein the formal test structure comprises an N-well resistance reference test structure and a polysilicon gate resistance test structure, wherein the N-well resistance reference test structure and the polysilicon gate resistance test structure are arranged in parallel up and down in the cutting path, wherein the N-well resistance reference test structure is provided with a first test pad and a second test pad, wherein the polysilicon gate resistance test structure is provided with a third test pad and a fourth test pad, wherein the first test pad, the third test pad, the second test pad and the fourth test pad are arranged alternately along the cutting path direction, wherein:

[0078] The N-well resistance reference test structure comprises:

[0079] An N-well resistor in the active area, the N-well resistor is rectangular, and a first test lead-out terminal and a second test lead-out terminal are located at two ends of the rectangular N-well resistor, the first test lead-out terminal and the second test lead-out terminal are electrically connected to the first test pad and the second test pad, respectively;

[0080] The polysilicon gate resistance test structure comprises:

[0081] An N-well resistor reference test structure and at least two long strips of polysilicon located above the N-well resistor and a third test lead-in and a fourth test lead-in located at both ends of the N-well resistor and the two long strips of polysilicon, the two long strips of polysilicon are arranged in parallel, the spacing between the two polysilicons is located between the third test lead-in and the fourth test lead-in, and the third test lead-in and the fourth test lead-in are electrically connected to the third test pad and the fourth test pad, respectively.

[0082] In the process window electrical property test structure of the polysilicon gate spacing provided by the technical solution of the present invention, a test structure including a polysilicon gate resistance test structure and an N-well resistance reference test structure is set, wherein, compared with the N-well resistance reference test structure, the polysilicon gate resistance test structure is provided with at least two long strips of polysilicon above the N-well resistance, so that in the subsequent process, the N-well resistance of the N-well resistance reference test structure will be completely covered with a metal silicide barrier layer (SAB, Salicide-block), resulting in the area on the N-well resistance being a metal silicide-free area; while in the polysilicon gate resistance test structure, the area covered by polysilicon will not form a metal silicide barrier layer. The resistance value of the region is equivalent to the resistance value of the N-well resistor covered by the metal silicide barrier layer. Only the region between the two polysilicons is not covered by the metal silicide barrier layer, and metal silicide may be formed in this region; therefore, only the region between the two polysilicons may affect the resistance value of the polysilicon gate resistance test structure; and the polysilicon gate resistance test structure and the N-well resistance reference test structure are respectively led out through the pad and the pad lead-out end, and the resistance between the polysilicon gate resistance test structure and the N-well resistance reference test structure is tested, and the resistance between the two is compared, so that the purpose of non-destructive testing of the metal silicide preparation process between the polysilicon gates can be achieved by using the electrical test method. Whether metal silicide is formed between the two polysilicons can be monitored without slicing, which reduces the cost, improves the convenience of monitoring, and does not cause wafer damage.

[0083] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0084] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0085] Please refer to Figure 2-Figure 5 ,in, Figure 2 A schematic diagram of a process window electrical property test structure of a polysilicon gate spacing provided in one embodiment of the present invention; Figure 3 A schematic diagram of a pad structure of a process window electrical test structure for a polysilicon gate spacing provided by an embodiment of the present invention; Figure 4 for Figure 2 The process window electrical test structure of the polysilicon gate spacing shown is a cross-sectional view along p1-p1' (a), a cross-sectional view along p2-p2' (b), and a cross-sectional view along p3-p3' (c); Figure 5 for Figure 2 The cross-sectional view of the process window electrical test structure of the polysilicon gate spacing is shown along p4-p4'.

[0086] like Figure 2-Figure 5As shown, an embodiment of the present invention provides a process window electrical test structure 1 for a polysilicon gate spacing, the process window electrical test structure 1 is placed in a cutting path of a wafer, and includes at least one formal test structure 11, the formal test structure 11 includes an N-well resistance reference test structure 112 and a polysilicon gate resistance test structure 111, the N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 are arranged in parallel up and down in the cutting path, the N-well resistance reference test structure 112 is provided with a first test pad 1121 and a second test pad 1122, the polysilicon gate resistance test structure 111 is provided with a third test pad 1111 and a fourth test pad 1112, the first test pad 1121, the third test pad 1111, the second test pad 1122 and the fourth test pad 1112 are arranged alternately along the cutting path direction, wherein:

[0087] The N-well resistance reference test structure 112 includes:

[0088] An N-well resistor 1123 in the active area is rectangular, and has a first test lead-out terminal 1124 and a second test lead-out terminal 1125 at both ends of the rectangular N-well resistor 1123, and the first test lead-out terminal 1124 and the second test lead-out terminal 1125 are electrically connected to the first test pad 1121 and the second test pad 1122 respectively.

[0089] The polysilicon gate resistance test structure 111 includes:

[0090] The N-well resistor reference test structure 112 and at least two long strips of polysilicon 1113 located above the N-well resistor 1123, and a third test lead-in terminal 1114 and a fourth test lead-in terminal 1115 located at both ends of the N-well resistor 1123 and the two long strips of polysilicon 1113. The two long strips of polysilicon 1113 are arranged in parallel, and the distance between the two polysilicon 1113 is located between the third test lead-in terminal 1114 and the fourth test lead-in terminal 1115. The third test lead-in terminal 1114 and the fourth test lead-in terminal 1115 are electrically connected to the third test pad 1111 and the fourth test pad 1112, respectively.

[0091] See also Figure 2 , wherein the N-well resistor 1123 can be understood as: for the active area 105 on the substrate, the resistor corresponding to the part of the N-well region in the N-well region that serves as the resistor region 80. Figure 2 , and combined with the graph pair Figure 4 , Figure 5By comparing the polysilicon gate resistance test structure 111 and the N-well resistance reference test structure 112, it can be seen that, except for the difference in the structure of the area above the N-well resistance 1123, the structures of other areas are the same; in the area above the N-well resistance 1123, the N-well resistance reference test structure 112 has the same structure as the conventional device, and is completely covered by the metal silicide barrier layer 70, and the area above it is a metal silicide-free area 60, while in the polysilicon gate resistance test structure 111, metal silicide may be formed between two polysilicons 1113, and metal silicide will not be formed in the area covered by the polysilicon 1113, which is equivalent to the resistance value of the N-well resistance 1123 covered by the metal silicide barrier layer 70. Only the area between the two polysilicons 1113 may affect the resistance change of the polysilicon gate resistance test structure 111 due to the possible formation of metal silicide, thereby generating a resistance difference between the polysilicon gate resistance test structure 111 and the N-well resistance reference test structure 112.

[0092] Continue reading Figure 3 , if the given polysilicon spacing (Poly space) is small enough to prevent metal silicide from being formed between two polysilicons 1113, it is experimentally proved that the resistance between the first test pad 1121 and the second test pad 1122 measured at this time is equal to the resistance between the third test pad 1111 and the fourth test pad 1112; and in the case of a given polysilicon spacing being large, when metal silicide is formed in the region between the polysilicon, the resistance between the first test pad 1121 and the second test pad 1122 measured is greater than the resistance between the third test pad 1111 and the fourth test pad 1112. Therefore, through this characteristic, the present invention can monitor whether metal silicide is formed between polysilicon by comparing the resistance between the two test pads of the polysilicon gate resistance test structure and the resistance between the two test pads of the N-well resistance reference test structure measured. Compared with the existing slicing monitoring method, the electrical testing method provided by the present invention greatly reduces the cost, improves the convenience of monitoring, and does not cause wafer damage.

[0093] In one embodiment, Figure 5 As shown, the sidewalls of the two long strips of polysilicon 1113 are both formed with a spacer 50. In this case, the spacing between the two polysilicons 1113 is specifically the spacing between the sidewalls 50 of the two polysilicons 1113. Therefore, in this embodiment, it is possible to monitor the metal silicide formed between the sidewalls of the two polysilicons under the influence of the poly space causing the poly space to shift due to the sidewall being affected by process fluctuations.

[0094] like Figure 2 , Figure 4 and Figure 5 As shown, the N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 also include: a substrate 101, a P-well region 102 formed on the substrate 101 and distributed on both sides of the N-well resistance 1123, an isolation structure 103 formed in the P-well region 102, and an N-type heavily doped region 104, a first test lead-out terminal 1124 and a second test lead-out terminal 1125 are in contact with the N-type heavily doped region 104 in the N-well resistance reference test structure 112, and a third test lead-out terminal 1114 and a fourth test lead-out terminal 1115 are both in contact with the N-type heavily doped region 104 in the polysilicon gate resistance test structure 111. The N-well resistance 1123 in the N-well resistance reference test structure 112 is covered by a metal silicide barrier layer 70 ( Figure 2 2 is a diagram illustrating an N-well resistor in the N-well resistor reference test structure 112, and a metal silicide barrier layer on the N-well resistor is not illustrated).

[0095] Continue to refer Figure 2 and Figure 4 As a preferred embodiment, the length of the area above the N-well resistor 1123 in the polysilicon gate resistance test structure 111 is consistent with the length of the N-well resistor 1123 in the N-well resistance reference test structure 112, and the outer boundaries of the two polysilicon blocks are flush with the boundary of the metal silicide barrier layer 70. In addition, the polysilicon gate resistance test structure 111 and the N-well resistance reference test structure 112 are consistent in other aspects, for example: the size and spacing of the source and drain injection regions are also consistent to maintain the same ohmic contact; the number of contact holes, the distance from the contact holes to the resistance area 80 are also consistent, and the size of the resistance area 80 of the two is consistent, so as to overcome the influence of irrelevant variables.

[0096] In addition, in order to form better uniformity and eliminate the influence of process fluctuations, it is preferably necessary to set the distance between the polysilicon gate resistance test structure 111 and the N-well resistance reference test structure 112 to be sufficiently small, for example, the distance can be set within the range of the minimum distance specified by the process design rules to twice the minimum distance. Specifically, the minimum distance specified by the process design rules is not the same in different process nodes, and the minimum distance of the design rules is well known to those skilled in the art, and will not be specifically described here. Those skilled in the art can select a suitable distance between the polysilicon of the series MOS tube according to different process technology nodes.

[0097] As a further preferred method, in order to eliminate the influence of other processes, such as the drift of the size of the active area (AA), polysilicon, N-well, etc., their sizes should be appropriately increased. However, if these sizes are set too large, the resistance change caused between the sidewalls of the polysilicon sidewalls will be too small to be detected, so the sizes of these structural layers should be determined based on actual calculations. Regarding the above-mentioned method for determining the size, in a specific typical example, for example, it is known that the width of the single-sided sidewall is 0.09um, the square resistance of the N-well is 500Ω / sq, and the resistance of the metal silicide block is 20Ω / sq (the above three data depend on the specific process); when L = 50um (the length of the N-well resistor), W = 2um (the width of the N-well resistor), and the poly space is 0.25um, it is calculated that: R NW =500*(50 / 2)=12500Ω, R silicide =20*(50 / (0.25-0.09*2.0))=14285Ω, the resistance after the two are connected in parallel: R 并 =6666.5Ω; where R NW is the resistance of the N-well resistor, R silicide is the resistance of metal silicide, R 并 is the resistance of the N-well resistor and the metal silicide resistor in parallel. When the poly space is offset by 0.01um, it can be solved as follows:

[0098]

[0099] Of course, the above is only an example of calculating and determining the aforementioned structural layer. The values ​​of the aforementioned data may vary due to the specific process. However, no matter what process is used, the size of the corresponding structural layer can be calculated under the premise of knowing the corresponding data.

[0100] Please Figure 2 Based on the combination Figure 7 As a preferred embodiment, the process window electrical test structure 1 of the polysilicon gate spacing provided by the present invention includes a virtual test structure 12 on the basis of the formal test structure 11, and the virtual test structure 12 is symmetrically arranged at the upper and lower positions of the formal test structure 11; the structure of the virtual test structure 12 is the same as that of the formal test structure 11. In the actual production process, the chip environment is dense. In order for the test structure of the present invention to be able to monitor during the production process and enable the electrical properties of the test structure to simulate the electrical properties of the chip environment, it is necessary to add a virtual test structure around the test structure to achieve a uniform pattern, thereby simulating the chip environment. Furthermore, the metal connection between the formal test structure 11 and the test pad must also achieve symmetry to reduce the interference caused by the metal connection.

[0101] In a further embodiment of the present invention, a method for manufacturing a process window electrical test structure of a polysilicon gate spacing is provided, which is used to prepare the process window electrical test structure 1 of the polysilicon gate spacing described in the above embodiment, and the method comprises:

[0102] The N-well resistor reference test structure 112 is formed; wherein the N-well resistor reference test structure 112 is formed while forming other device structures in the functional area of ​​the wafer. Specifically, the formation of the N-well resistor reference test structure 112 includes: forming an N-well resistor 1123 in the active area within the cutting path, wherein the N-well resistor 1123 is rectangular; and forming a first test lead-out terminal 1124 and a second test lead-out terminal 1125 at both ends of the rectangular N-well resistor 1123, respectively.

[0103] The polysilicon gate resistance test structure 111 is fabricated in the cutting path and arranged in parallel with the N-well resistance reference test structure 112. Specifically, it includes: forming at least two long strips of polysilicon 1113 in the area above the N-well resistance 1123, and the two long strips of polysilicon 1113 are arranged in parallel; and forming a third test lead-out terminal 1114 and a fourth test lead-out terminal 1115 at both ends of the N-well resistance 1123 and the two long strips of polysilicon 1113, respectively, and the spacing between the two polysilicon 1113 is located between the third test lead-out terminal 1114 and the fourth test lead-out terminal 1115. The fabrication of other test structures in the process window electrical test structure 1 of the polysilicon gate spacing, such as the fabrication of the isolation structure, the P-well region, etc., is also prepared together with the fabrication process of forming other device structures in the functional area of ​​the wafer. According to another embodiment of the present invention, a contact layer measurement method is also provided, and the method includes:

[0104] Detecting the resistance values ​​of the N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 in the process window electrical property test structure 1 for the polysilicon gate spacing according to any one of the aforementioned embodiments of the present invention;

[0105] Whether the metal silicide layer is formed between the two long strips of polysilicon is determined according to the resistance values ​​of the N-well resistance reference test structure 112 and the polysilicon gate resistance test structure 111 .

[0106] If the resistance between the first test pad 1121 and the second test pad 1122 is greater than the resistance between the third test pad 1111 and the fourth test pad 1112, it means that a metal silicide layer is formed between the polysilicon; if the two are approximately the same, it means that the metal silicide layer is not formed normally. This realizes non-destructive testing of whether metal silicide is formed between the polysilicon of the semiconductor device, greatly reducing costs and improving the convenience of monitoring.

[0107] According to another embodiment of the present invention, a process window electrical test component for polysilicon gate spacing is provided, comprising a plurality of process window electrical test structures 1 for polysilicon gate spacing as described in any one of the aforementioned embodiments of the present invention, wherein the spacing (Polyspace) between the polysilicon is different in the plurality of process window electrical test structures 1 for polysilicon gate spacing.

[0108] When developing new nodes and establishing new production lines, it is necessary to determine the minimum value of the spacing between two polysilicons at the process node. The process window electrical test component of the polysilicon gate spacing provided by the embodiment of the present invention is placed in the cutting path of the wafer, that is, a number of process window electrical test structures 1 of polysilicon gate spacing are set in the cutting path, and the spacing between polysilicon in each process window electrical test structure of polysilicon gate spacing is different; the resistance of each process window electrical test structure of polysilicon gate spacing under different spacing between polysilicon is measured, and these test structures only have different spacing between polysilicon, and other structures and sizes are consistent. By collecting a large number of test results, a point-line distribution diagram of the measured resistance as the spacing between polysilicon in test structures of different sizes changes with resistance can be obtained, and the process minimum value and process window of the spacing between polysilicon can be determined from the point-line distribution diagram.

[0109] Figure 6 A flowchart of a method for determining a minimum spacing of a semiconductor process provided by an embodiment of the present invention, Figure 8 is a first relationship model between the spacing between polysilicon and the corresponding total resistance, wherein Figure 8 The first spacing is the spacing between polysilicon, the unit of the first spacing is um, and wafer center refers to the center position of the wafer.

[0110] in, Figure 8 The distance between polysilicon at the sudden resistance value in the dotted line graph is the minimum process distance. Figure 6 shown.

[0111] like Figure 6 As shown, a method for determining a minimum spacing of a semiconductor process provided in one embodiment of the present invention includes:

[0112] S1: Obtain the spacing between polysilicon layers corresponding to the process window electrical test structures 1 of several polysilicon gate spacings as described in the above-mentioned embodiments of the present invention.

[0113] S2: Measure the total resistance of the resistance of the process window electrical test structure 1 of each polysilicon gate spacing. Specifically, measure the resistance between the first test pad 1121 and the second test pad 1122, and the resistance between the third test pad 1111 and the fourth test pad 1112 of each polysilicon gate spacing process window electrical test structure to obtain the total resistance. As an example, the total resistance is expressed as Indicates. Among them, R 测 represents the resistance value of the polysilicon gate resistance test structure 111; R NW represents the resistance value of the N-well resistance reference test structure 112 .

[0114] S3: See Figure 8 According to the spacings between the polysilicon and the total resistances, a first relationship model between the spacings between the polysilicon and the corresponding total resistances is obtained.

[0115] In a typical example, the spacing between polysilicon and several total resistance values ​​at the center of the wafer in the test chip are obtained, a distribution graph of the change in the spacing between polysilicon is made, data from multiple wafers are collected, and a distribution graph is also made. Statistical analysis is performed on these data to make a fitted distribution curve.

[0116] Preferably, the above two steps may be repeated at different representative positions such as the center position of the wafer or other positions in the wafer to obtain fitting curves at different positions.

[0117] In a typical example, taking the 0.18um technology node as an example, the spacing between polysilicon and several total resistance values ​​at the center of the wafer in the test chip are obtained. The total resistance is Get the distribution diagram of the change in the spacing between polysilicon, collect data from multiple wafers, and also make a distribution diagram, perform statistical analysis on these data, and make a fitting distribution curve. According to the distribution curve, as the spacing between polysilicon decreases, the change curve of the total resistance should be a curve that is flat first and then rises. Repeat the above two steps at other locations on the wafer, and get fitting curves at different locations, such as Figure 8 As shown. Figure 8It can be seen that: when the spacing between polysilicon is large, excluding the possibility of other process fluctuations, at this time, due to the normal growth of metal silicide in the potential non-metal silicide area, the total resistance of the area is a constant value; as the spacing between polysilicon increases, the proportion of metal silicide resistance in the middle increases, so the measured total resistance will be smaller, and as the spacing between polysilicon decreases, the measured resistance will increase in a nearly linear form until the spacing between polysilicon decreases to a certain extent, and the increase rate of the measured resistance will slowly slow down until it is flat. This is because when the spacing between polysilicon is very small, the potential non-metal silicide area cannot form a uniform metal silicide layer, or even no metal silicide layer. At this time, if the spacing between polysilicon continues to decrease, the change in total resistance is not large.

[0118] S4: Determine the value of the minimum spacing according to the first relationship model. Preferably, if under a certain spacing condition between polysilicon, they can all be distributed within the 10% deviation range of the corresponding curve point, then the spacing between the polysilicon is determined to be the minimum process spacing (minimum poly space). Figure 8 As shown, the minimum process spacing is 0.2um.

[0119] Preferably, slices of the process window electrical test structure 1 of the several polysilicon gate spacings can also be obtained. According to the several slices and the first relationship model, the value of the minimum spacing is determined. In this embodiment, the slicing results are compared with the electrical test results to ensure the accuracy of the electrical test during the research and development stage of developing new nodes and establishing new production lines. After determining the minimum process spacing, process monitoring of metal silicide can be achieved without slicing in the subsequent production stage, thereby greatly reducing the monitoring cost while achieving the determination of the minimum process spacing and metal silicide process monitoring. At the same time, this embodiment further verifies the accuracy of the minimum process spacing determined by the scheme of the present invention by slicing, so the technical scheme provided by this embodiment reduces experimental errors and improves accuracy.

[0120] In summary, the process window electrical test structure of the polysilicon gate spacing provided by the present invention is provided with a test structure including a polysilicon gate resistance test structure and an N-well resistance reference test structure, wherein, compared with the N-well resistance reference test structure, the polysilicon gate resistance test structure is provided with at least two long strips of polysilicon above the N-well resistance, so that in the subsequent process, the N-well resistance of the N-well resistance reference test structure will be completely covered with a metal silicide barrier layer (SAB, Salicide-block), resulting in the area on the N-well resistance being a metal silicide-free area; whereas in the polysilicon gate resistance test structure, the area covered by polysilicon will not form a metal silicide barrier layer. Silicide, the resistance value of this area is equivalent to the resistance value of the N-well resistor covered by the metal silicide barrier layer, and only the area between the two polysilicons is not covered by the metal silicide barrier layer, and metal silicide may be formed in this area; therefore, only the area between the two polysilicons may affect the resistance value of the polysilicon gate resistance test structure; and the polysilicon gate resistance test structure and the N-well resistance reference test structure are respectively led out through the pad and the pad lead-out end, and the resistance between the polysilicon gate resistance test structure and the N-well resistance reference test structure is tested, and the resistance between the two is compared, so that the purpose of non-destructive testing of the metal silicide preparation process between the polysilicon gates can be achieved by using the electrical test method. Thereby, it is possible to monitor whether metal silicide is formed between the two polysilicons without slicing, which reduces the cost, improves the convenience of monitoring, and does not cause wafer damage.

[0121] Furthermore, a method for determining the minimum spacing of a semiconductor process is provided, by setting a number of process window electrical test structures of polysilicon gate spacing, and setting the spacing between polysilicon in the polysilicon gate resistance test structures corresponding to the process window electrical test structures of the polysilicon gate spacing to different sizes; after obtaining the spacing between the polysilicon and the total resistance values ​​corresponding to the process window electrical test structures of the polysilicon gate spacing, a first relationship model of the change in the spacing between the polysilicon is established according to the spacing between the polysilicon and the total resistance values ​​of the polysilicon, and the value of the minimum spacing can be determined according to the first relationship model. Therefore, when developing a new node and establishing a new production line, the method provided by the present invention can determine the minimum spacing under the process node, providing a reference for monitoring the spacing between polysilicon in the subsequent production stage.

[0122] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A process window electrical test structure for a polysilicon gate spacing, wherein the process window electrical test structure is placed in a cutting path of a wafer, characterized in that: At least one formal test structure is included, the formal test structure includes an N-well resistance reference test structure and a polysilicon gate resistance test structure, the N-well resistance reference test structure and the polysilicon gate resistance test structure are arranged in parallel up and down in the cutting path, the N-well resistance reference test structure is provided with a first test pad and a second test pad, the polysilicon gate resistance test structure is provided with a third test pad and a fourth test pad, the first test pad, the third test pad, the second test pad and the fourth test pad are arranged alternately along the cutting path direction, wherein: The N-well resistance reference test structure comprises: An N-well resistor in the active area, the N-well resistor is rectangular, and a first test lead-out terminal and a second test lead-out terminal are located at two ends of the rectangular N-well resistor, the first test lead-out terminal and the second test lead-out terminal are electrically connected to the first test pad and the second test pad, respectively; The polysilicon gate resistance test structure comprises: An N-well resistor reference test structure and at least two long strips of polysilicon located above the N-well resistor and a third test lead-in and a fourth test lead-in located at both ends of the N-well resistor and the two long strips of polysilicon, the two long strips of polysilicon are arranged in parallel, the spacing between the two polysilicons is located between the third test lead-in and the fourth test lead-in, and the third test lead-in and the fourth test lead-in are electrically connected to the third test pad and the fourth test pad, respectively.

2. The process window electrical property test structure of polysilicon gate spacing according to claim 1, characterized in that: The two long strip-shaped polysilicon side walls are both formed with side walls, and the distance between the two polysilicon strips is the distance between the side walls.

3. The process window electrical property test structure of polysilicon gate spacing according to claim 1, characterized in that: The test structure further includes a virtual test structure, which is symmetrically arranged at upper and lower positions of the formal test structure; the structure of the virtual test structure is the same as that of the formal test structure.

4. A method for manufacturing a process window electrical test structure of a polysilicon gate spacing, used for manufacturing the process window electrical test structure of a polysilicon gate spacing according to claim 1, characterized in that: include: Forming the N-well resistance reference test structure includes: forming an N-well resistor in an active area within the cutting path, wherein the N-well resistor is rectangular; Forming first and second test leads at two ends of the rectangular N-well resistor respectively; The polysilicon gate resistance test structure is fabricated in the cutting path and is arranged in parallel with the N-well resistance reference test structure, including: At least two strips of polysilicon are formed in the area above the N-well resistor; the two strips of polysilicon are arranged in parallel; A third test lead-out terminal and a fourth test lead-out terminal are formed at both ends of the N-well resistor and the two long strips of polysilicon respectively, and the distance between the two polysilicon strips is located between the third test lead-out terminal and the fourth test lead-out terminal.

5. A method for measuring a contact layer, characterized in that: include: Detecting the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure in the process window electrical property test structure of the polysilicon gate spacing according to any one of claims 1 to 3; Whether the metal silicide layer is formed between the two long strips of polysilicon is determined according to the resistance values ​​of the N-well resistance reference test structure and the polysilicon gate resistance test structure.

6. A process window electrical property test component for polysilicon gate spacing, characterized in that: It comprises a plurality of process window electrical test structures of polysilicon gate spacing as described in any one of claims 1 to 3, wherein the spacings between the polysilicon are all different.

7. A method for determining the minimum spacing of a semiconductor process, characterized in that: include: Obtaining the spacing between polysilicon corresponding to the process window electrical property test structures of the plurality of polysilicon gate spacings as claimed in claim 6; Measuring the total resistance value of the resistance of the process window electrical property test structure of each polysilicon gate spacing; According to a plurality of spacings between the polysilicon and a plurality of total resistance values, a first relationship model between the spacings between the polysilicon and the corresponding total resistance values ​​is obtained; According to the first relationship model, a value of a minimum distance is determined.

8. The method for determining the minimum spacing of a semiconductor process according to claim 7, wherein: The method further includes: Obtaining slices of the process window electrical test structures of the plurality of polysilicon gate spacings; The value of the minimum distance is determined according to the plurality of slices and the first relationship model.

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