Anti-reverse protection circuit for keeping low standby quiescent current and control method

Abstract

The invention relates to an anti-reverse protection circuit capable of keeping low standby quiescent current. The anti-reverse protection circuit comprises an MOS tube Q1, a voltage-regulator tube D1, a first resistor R1, a triode Q2, a second resistor R2, a diode D2, a third resistor R3, a fourth resistor R4 and a power management module. The negative electrode of the voltage-regulator tube D1 is connected with the source electrode of the MOS tube Q1, the positive electrode of the voltage-regulator tube D1 is connected with the grid electrode of the MOS tube Q1, and the first end of the first resistor R1 is connected with the source electrode of the MOS tube Q1. According to the anti-reverse protection circuit for keeping the low standby quiescent current, when the electronic equipment works normally, the MOS tube is conducted bidirectionally, so that lower on-resistance is obtained, and the power supply of the equipment is in an optimal working state; when the electronic equipment is in a standby state, the grid electrode of the P-channel MOS tube is disconnected with the GND, so that basically no current passes through each component in the anti-reverse circuit, and a relatively low standby quiescent current is obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an anti-reverse protection circuit and a control method for maintaining low standby static current. Background Art

[0002] For automotive electronic equipment, in order to prevent damage when the battery is mistakenly connected in reverse, there must be an anti-reverse design in the power circuit. Before the positive and negative poles of the battery are connected to the power management circuit of the device, the anti-reverse protection circuit protects the polarized capacitors and ICs in the back-end circuit from reverse breakdown.

[0003] The simplest form of anti-reverse circuit for automotive electronic equipment is to use diodes for anti-reverse. This form is very low cost, but it is only suitable for small current applications of 1~2A. In large current applications, anti-reverse circuits usually have the following forms: 1. Use N-channel MOS tube on the low side of the power supply to prevent reverse, but this form is rarely used in practice because it separates the power ground and the load ground; 2. Use P-channel MOS tube on the high side of the power supply to prevent reverse. Figure 1 This form is widely used in practice, but its main disadvantage is that the standby static current is large, usually more than 2mA; 3. Use a dedicated driver IC plus a P-channel or N-channel MOS tube for reverse protection. This form of standby static current can be made very low, usually within 10~50 uA, but the disadvantage is that the cost of the dedicated IC is relatively high. Summary of the invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the existing technology that there are a large number of electronic devices in modern cars. If the standby static current of many electronic devices is large, it will undoubtedly put pressure on the vehicle battery, and will continue to cause more power consumption of the battery during the vehicle stop process. Over time, it will cause the battery life to decrease and affect the normal start of the car. The above-mentioned third anti-reverse circuit cannot completely replace the second anti-reverse circuit because the dedicated IC is expensive and more likely to face the risk of shortage. Therefore, how to reduce the standby static current of the P-channel MOS tube anti-reverse protection circuit is a technical problem that needs to be solved urgently.

[0005] In order to solve the above technical problems, the present invention provides an anti-reverse protection circuit for maintaining low standby static current, comprising: a MOS tube Q1, a voltage regulator tube D1, a first resistor R1, a triode Q2, a second resistor R2, a diode D2, a third resistor R3, a fourth resistor R4 and a power management module; wherein the source of the MOS tube Q1 is connected to the power management module at the back end, the cathode of the voltage regulator tube D1 is connected to the source of the MOS tube Q1, and the anode of the voltage regulator tube D1 is connected to the gate of the MOS tube Q1, and the first end of the first resistor R1 is connected to the M The source of the MOS tube Q1 is connected, and the second end of the first resistor R1 is connected to the gate of the MOS tube Q1, the collector of the transistor Q2 is connected to the gate of the MOS tube Q1 through the second resistor R2, the emitter of the transistor Q2 is connected to GND, the positive electrode of the diode D1 is connected to VCC, and the negative electrode of the diode D2 is connected to the base of the transistor Q2 through the third resistor R3, the first end of the fourth resistor R4 is connected to the base of the transistor Q2, and the second end of the fourth resistor R4 is connected to the emitter of the transistor Q2. The anti-reverse protection circuit for maintaining low standby static current of the present invention, when the electronic device is in normal operation, through the setting of the circuit, the gate of the P-channel MOS tube is connected to GND, so that the MOS tube is bidirectionally conductive, thereby obtaining a lower on-resistance, so that the power supply of the device is in the best working state; when the electronic device is in standby, the gate of the P-channel MOS tube is disconnected from GND, so that each component in the anti-reverse protection circuit has basically no current passing through, thereby obtaining a lower standby static current.

[0006] In one embodiment of the present invention, the drain of the MOS tube Q1 is connected to the positive power supply electrode.

[0007] In one embodiment of the present invention, the GND is connected to the negative power supply electrode.

[0008] In one embodiment of the present invention, the anode of the diode D2 is connected to the VCC of the power management module.

[0009] In one embodiment of the present invention, the VCC value of the power management module is 5V or 3.3V.

[0010] In one embodiment of the present invention, the MOS transistor Q1 is a P-channel MOS transistor.

[0011] In one embodiment of the present invention, the transistor Q2 is an NPN transistor.

[0012] In one embodiment of the present invention, the power management module is connected to a switch signal.

[0013] In one embodiment of the present invention, the diode D2 and the third resistor R3 are connected in series.

[0014] The control method of the anti-reverse protection circuit for maintaining low standby static current of the present invention comprises the following steps: When the device is in standby mode, the power management module of the device does not output VCC, VCC is 0V, and the transistor Q2 is in a cut-off state, thereby disconnecting the gate of the MOS transistor Q1 from GND, and the standby static current is equal to the leakage current of the transistor Q2, thereby achieving a low standby static current; When the device is awakened by the switch signal, the power management module enters the normal working state and outputs VCC. At this time, the transistor Q2 works in the amplification or saturation state, so that the gate of the MOS tube Q1 is connected to GND, and the MOS tube Q1 is bidirectionally conductive, thereby obtaining a low on-resistance; When the power supply is reversely connected, the transistor Q2 is in the cut-off state, the diode D2 is also reversely cut-off, the drain and source of the MOS tube Q1 are in the cut-off state, and the parasitic diode of the MOS tube Q1 is also in the reverse cut-off state, and the standby static current approaches zero.

[0015] The above technical solution of the present invention has the following beneficial effects compared with the prior art: The anti-reverse protection circuit and control method for maintaining low standby static current of the present invention adopts the structure of a high-side P-channel MOS tube and adds a circuit that can control the gate of the P-channel MOS tube; the low standby static current control method is that when the electronic device is in normal operation, the gate control circuit connects the connection between the gate of the P-channel MOS tube and GND, so that the MOS tube is bidirectionally conductive, thereby obtaining a lower on-resistance and putting the power supply of the device in an optimal working state; when the electronic device is in standby, the gate control circuit cuts off the connection between the gate of the P-channel MOS tube and GND, thereby obtaining a lower standby static current. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein Figure 1 The circuit diagram of the anti-reverse protection circuit for maintaining low standby static current in the preferred embodiment of the present invention.

[0017] Description of the accompanying drawings in the specification: MOS tube Q1, voltage regulator tube D1, first resistor R1, transistor Q2, second resistor R2, diode D2, third resistor R3, fourth resistor R4, power management module 100. DETAILED DESCRIPTION

[0018] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0019] Reference Figure 1 As shown, the anti-reverse protection circuit for maintaining low standby static current of the present invention includes: a MOS tube Q1, a voltage regulator tube D1, a first resistor R1, a triode Q2, a second resistor R2, a diode D2, a third resistor R3, a fourth resistor R4 and a power management module 100; wherein, the source of the MOS tube Q1 is connected to the power management module 100 at the back end, the negative electrode of the voltage regulator tube D1 is connected to the source of the MOS tube Q1, and the positive electrode of the voltage regulator tube D1 is connected to the gate of the MOS tube Q1, and the first end of the first resistor R1 is connected to the source of the MOS tube Q1, And the second end of the first resistor R1 is connected to the gate of the MOS transistor Q1, the collector of the transistor Q2 is connected to the gate of the MOS transistor Q1 through the second resistor R2, the emitter of the transistor Q2 is connected to GND, the anode of the diode D1 is connected to VCC, and the cathode of the diode D2 is connected to the base of the transistor Q2 through the third resistor R3, the diode D2 and the third resistor R3 are connected in series, the first end of the fourth resistor R4 is connected to the base of the transistor Q2, and the second end of the fourth resistor R4 is connected to the emitter of the transistor Q2.

[0020] The drain of the MOS transistor Q1 is connected to the positive power supply electrode. The GND is connected to the negative power supply electrode. The MOS transistor Q1 is a P-channel MOS transistor. The transistor Q2 is an NPN transistor.

[0021] In addition, the anode of the diode D2 is connected to the VCC of the power management module 100. VCC is output by the power management module 100 of the electronic device during normal operation, and is generally 5V or 3.3V.

[0022] In addition, the power management module 100 is connected to a switch signal.

[0023] According to the above circuit, the control method of the anti-reverse protection circuit for maintaining low standby static current of the present invention includes the following steps: When the device is in standby mode, the power management module 100 of the device does not output VCC, and VCC is 0V. At this time, the transistor Q2 is in the cut-off state, thereby disconnecting the gate of the MOS tube Q1 from GND. Basically, no current passes through the components described in the anti-reverse protection circuit 200. The standby static current is approximately equal to the leakage current of the transistor Q2, which is approximately 0.1~5 uA, thereby achieving a lower standby static current.

[0024] When the device is awakened by the switch signal, the power management module 100 enters a normal working state and outputs VCC. At this time, the transistor Q2 works in an amplification or saturation state, so that the gate of the MOS tube Q1 is connected to GND, and the MOS tube Q1 is bidirectionally conductive, thereby obtaining a lower on-resistance, so that the power supply of the device is in the best working state.

[0025] When the power supply is reversely connected, the transistor Q2 is in the cut-off state, the diode D2 is also reversely cut-off, the drain and source of the MOS tube Q1 are in the cut-off state, and the parasitic diode of the MOS tube Q1 is also in the reverse cut-off state. The anti-reverse protection circuit realizes anti-reverse protection, and basically no current passes through each component, and the standby static current is approximately equal to zero.

[0026] In the control method of the anti-reverse protection circuit for maintaining low standby quiescent current of the present invention, the transistor Q2 in the anti-reverse protection circuit may also be other components with voltage-controllable switch characteristics, such as relays, MOS tubes or switch ICs; the positive electrode of the diode D2 may also not be connected to VCC, but connected to other ports that can be powered off when the device is in standby mode and powered when the device is working, such as an IO port of the device main control chip, and the device software controls the output of high level (5V or 3.3V) and low level (0V) states to achieve the control of the low standby quiescent current proposed by the present invention.

[0027] Compared with a typical P-channel MOS tube reverse protection circuit, the method proposed in the present invention can reduce the standby static current to about 0.1~5 uA, which is comparable to the reverse protection circuit using a dedicated IC, and has a lower implementation cost.

[0028] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A reverse protection circuit for maintaining low standby static current, characterized in that: include: MOS tube Q1, voltage regulator tube D1, first resistor R1, transistor Q2, second resistor R2, diode D2, third resistor R3, fourth resistor R4 and power management module; The source of the MOS tube Q1 is connected to the power management module at the back end, the cathode of the voltage regulator tube D1 is connected to the source of the MOS tube Q1, and the anode of the voltage regulator tube D1 is connected to the gate of the MOS tube Q1, the first end of the first resistor R1 is connected to the source of the MOS tube Q1, and the second end of the first resistor R1 is connected to the gate of the MOS tube Q1, the collector of the triode Q2 is connected to the gate of the MOS tube Q1 through the second resistor R2, the emitter of the triode Q2 is connected to GND, the anode of the diode D1 is connected to VCC, and the cathode of the diode D2 is connected to the base of the triode Q2 through the third resistor R3, the first end of the fourth resistor R4 is connected to the base of the triode Q2, and the second end of the fourth resistor R4 is connected to the emitter of the triode Q2.

2. The anti-reverse protection circuit for maintaining low standby static current according to claim 1, characterized in that: The drain of the MOS tube Q1 is connected to the positive power supply electrode.

3. The anti-reverse protection circuit for maintaining low standby static current according to claim 1, characterized in that: The GND is connected to the negative power supply electrode.

4. The anti-reverse protection circuit for maintaining low standby static current according to claim 1, characterized in that: The anode of the diode D2 is connected to the VCC of the power management module.

5. The anti-reverse protection circuit for maintaining low standby static current according to claim 4, characterized in that: The VCC value of the power management module is 5V or 3.3V.

6. The anti-reverse protection circuit for maintaining low standby static current according to claim 1, characterized in that: The MOS transistor Q1 is a P-channel MOS transistor.

7. The anti-reverse protection circuit for maintaining low standby static current according to claim 1, characterized in that: The transistor Q2 is an NPN transistor.

8. The anti-reverse protection circuit for maintaining low standby static current according to claim 1, characterized in that: The power management module is connected to a switch signal.

9. The anti-reverse protection circuit for maintaining low standby static current according to claim 1, characterized in that: The diode D2 and the third resistor R3 are connected in series.

10. The control method of the anti-reverse protection circuit for maintaining low standby static current according to any one of claims 1 to 9, characterized in that: These include: When the device is in standby mode, the power management module of the device does not output VCC, VCC is 0V, and the transistor Q2 is in a cut-off state, thereby disconnecting the gate of the MOS transistor Q1 from GND, and the standby static current is equal to the leakage current of the transistor Q2, thereby achieving a low standby static current; When the device is awakened by the switch signal, the power management module enters the normal working state and outputs VCC. At this time, the transistor Q2 works in the amplification or saturation state, so that the gate of the MOS tube Q1 is connected to GND, and the MOS tube Q1 is bidirectionally conductive, thereby obtaining a low on-resistance; When the power supply is reversely connected, the transistor Q2 is in the cut-off state, the diode D2 is also reversely cut-off, the drain and source of the MOS tube Q1 are in the cut-off state, and the parasitic diode of the MOS tube Q1 is also in the reverse cut-off state, and the standby static current approaches zero.

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