Multi-stage junction termination structure of vertical GaN diode and preparation method of multi-stage junction termination structure

Abstract

The invention belongs to the field of semiconductors, and discloses a multistage junction termination structure of a vertical GaN diode and a preparation method. Comprising a sapphire substrate, and a GaN nodule layer grows on the sapphire substrate; a silicon-doped n +-GaN layer is grown on the GaN nodule layer, a silicon-doped n-GaN layer is grown on the n +-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p +-GaN layer is grown on the p-GaN layer; etching from the p < + >-GaN layer to the n < + >-GaN layer, and preparing a negative electrode on the surface of the n < + >-GaN layer; etching from the p +-GaN layer to the p-GaN layer to form a continuous multi-stage step, and preparing a positive electrode on the surface of the p +-GaN layer; after the multi-stage step junction termination structure is introduced, the electric field aggregation phenomenon is obviously relieved, which indicates that the junction termination structure effectively reduces the internal electric field peak value.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a multi-level junction terminal structure of a vertical GaN diode and a preparation method thereof. Background Art

[0002] At present, the problem of withstand voltage of GaN-based diodes is mainly due to the electric field concentration effect at the junction edge, which limits the improvement of the breakdown voltage of GaN-based diodes. Designing efficient junction terminals is the main method to deal with the electric field concentration effect.

[0003] For traditional silicon-based diodes, the method of achieving junction termination is often to inject ions at the edge of the main junction through ion implantation technology to form a junction termination area. However, crystal damage is easily caused during high-energy ion implantation, and the implanted dose and the length and depth of diffusion are difficult to accurately control. Therefore, it is difficult to achieve accurate control of the dose, and too high or too low a dose may lead to unsatisfactory doping effects. The GaN material has a small diffusion coefficient, making it difficult for the injected dopant to diffuse in the crystal. These make it very difficult to ion implant thin layers of P-type GaN. On the other hand, the junction termination achieved by ion implantation usually uses a thicker p-GaN thickness (generally in the range of 300-500nm), which limits the on-resistance of the vertical GaN diode to a certain extent.

[0004] As for GaN materials, the way to form p-type GaN requires Mg doping in GaN, which is a reaction that occurs during vapor deposition, not achieved through ion implantation. Moreover, the acceptor energy level of Mg in GaN is deep, and its activation rate is also low. Therefore, the method of achieving junction termination through ion implantation is unrealistic on GaN-based devices.

[0005] Therefore, it is of great significance to develop a new process that can avoid ion implantation and realize an efficient junction termination structure on a thin layer of P-type GaN with a relatively economical and simple process steps. Summary of the invention

[0006] In view of the above-mentioned defects of the prior art, the object of the present invention is to develop a relatively economical and simple process step to achieve an efficient junction termination structure and a preparation method thereof on a thin layer of P-type GaN, so as to improve the breakdown voltage of a vertical GaN diode.

[0007] In the first aspect of the present invention, the present invention provides a multi-level junction terminal structure of a vertical GaN diode, comprising: a sapphire substrate, a GaN nodule layer grown on the sapphire substrate; a silicon-doped n+-GaN layer grown on the GaN nodule layer, a silicon-doped n-GaN layer grown on the n+-GaN layer, a magnesium-doped p-GaN layer grown on the n-GaN layer, and a magnesium-doped p+-GaN layer grown on the p-GaN layer; etching from the p+-GaN layer to the n+-GaN layer, and preparing a negative electrode on the surface of the n+-GaN layer; etching from the p+-GaN layer to the p-GaN layer to form a continuous multi-step, and preparing a positive electrode on the surface of the p+-GaN layer.

[0008] Furthermore, the size of the multiple steps is obtained by fitting the ellipse boundary so that the area of ​​the rectangular region including the multiple steps is equal to the integral area of ​​the corresponding ellipse boundary.

[0009] Furthermore, the width of the multiple steps is set in a manner that a higher step height is set near the edge of the step, and a lower step height is set near the center of the step.

[0010] Furthermore, the width of the multiple steps is set in a manner that includes setting a wider step width near the edge of the step, and setting a narrower step width near the center of the step.

[0011] Furthermore, the height of the multiple steps and the width of the multiple steps satisfy the following formula:

[0012]

[0013] Where L is the total length of the junction terminal, x is the step width, y is the step height, and T n Represents the total height of the junction terminal.

[0014] In a second aspect of the present invention, the present invention further provides a method for preparing a multi-level junction terminal structure of a vertical GaN diode, the method comprising:

[0015] A GaN nodule layer is grown on a sapphire substrate;

[0016] A silicon-doped n+-GaN layer is grown on the GaN nodule layer;

[0017] A silicon-doped n-GaN layer is grown on the n+-GaN layer;

[0018] A magnesium-doped p-GaN layer is grown on the n-GaN layer;

[0019] A magnesium-doped p+-GaN layer is grown on the p-GaN layer;

[0020] Etching from the p+-GaN layer to the n+-GaN layer;

[0021] Etching from the p+-GaN layer to the p-GaN layer to form a continuous multi-step;

[0022] Prepare a positive electrode on the surface of the p+-GaN layer, and prepare a negative electrode on the surface of the n+-GaN layer;

[0023] The sizes of the multiple steps are obtained by fitting the boundaries of an ellipse.

[0024] Further, the etching from the p+-GaN layer to the n+-GaN layer includes:

[0025] Depositing a silicon dioxide mask on the surface of the p+-GaN layer;

[0026] Using photolithography, the desired mesa pattern is transferred to the mask, leaving the portion not covered by the mask;

[0027] Etching from the p+-GaN layer to the n+-GaN layer by chemical etching or physical etching to remove the hierarchical structure not protected by the mask and form the required mesa structure;

[0028] The silicon dioxide mask is removed using an acidic solution.

[0029] Furthermore, etching from the p+-GaN layer to the p-GaN layer to form a continuous multi-step includes:

[0030] Depositing a silicon dioxide mask on the surface of the p+-GaN layer;

[0031] Using photolithography technology to transfer the desired mesa pattern to a mask, and etching the silicon dioxide mask to expose the p-GaN region that needs to be exposed;

[0032] The p-GaN is etched by physical etching ICP, from the p+-GaN layer to the p-GaN layer;

[0033] In the process of forming each step, repeating the photolithography and ICP etching operations, and finally removing the hierarchical structure not protected by the mask; forming the desired mesa structure; wherein the size of the multiple steps is obtained by fitting the ellipse boundary;

[0034] The silicon dioxide mask is removed using an acidic solution.

[0035] Furthermore, preparing a positive electrode on the surface of the p+-GaN layer and preparing a negative electrode on the surface of the n+-GaN layer comprises:

[0036] Depositing Ni / Au metal on the surface of the p+-GaN layer, and performing rapid thermal annealing after the deposition is completed;

[0037] An ohmic contact Ti / Al / Ti / Au metal is formed on the surface of the n+-GaN layer.

[0038] Furthermore, the dimensions of the multi-steps are obtained by fitting the ellipse boundary and include:

[0039] Dividing the multi-level junction terminal extension structure into corresponding multiple rectangular areas;

[0040] The size of each level of junction terminal is calculated by fitting multiple rectangular areas through elliptical boundaries.

[0041] The beneficial effects of the present invention include:

[0042] Compared with traditional silicon-based semiconductor power devices, the vertical GaN power diode of the present invention can achieve a higher breakdown voltage with the same drift layer thickness due to the high critical breakdown electric field and high electron mobility of the material itself. At the same time, it can achieve lower switching losses and on-resistance under the same current and voltage conditions. These characteristics provide huge potential and opportunities for further development in the field of power semiconductors. The present invention proposes a new type of multi-level junction terminal and a preparation method thereof, which can further improve the breakdown voltage of the device. After the multi-level step junction terminal structure is introduced into the present invention, the electric field concentration phenomenon is significantly alleviated, which indicates that the junction terminal structure effectively reduces the internal electric field peak. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic diagram of a multi-level junction terminal structure of a vertical GaN diode in an embodiment of the present invention;

[0044] Figure 2 Schematic diagram of a multi-level junction terminal structure of a vertical GaN diode in a preferred embodiment of the present invention;

[0045] Figure 3 is a schematic diagram of potential line distribution in a junction terminal extension region according to an embodiment of the present invention;

[0046] Figure 4 is a schematic diagram of a multi-level junction terminal structure according to an embodiment of the present invention;

[0047] Figure 5 is a simulation diagram of the highest and average breakdown voltages of the embodiment of the present invention compared with the prior art;

[0048] Figure 6 It is an electric field simulation diagram under reverse bias comparing the embodiment of the present invention with the prior art. DETAILED DESCRIPTION

[0049] The present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be noted that in the description of the present invention, the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific manner, and therefore cannot be understood as limiting the present invention. The terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0050] In some embodiments of the present invention, Figure 1 As shown, a multi-level junction terminal structure of a vertical GaN diode includes: a sapphire substrate, a GaN nodule layer is grown on the sapphire substrate; a silicon-doped n+-GaN layer is grown on the GaN nodule layer, a silicon-doped n-GaN layer is grown on the n+-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p+-GaN layer is grown on the p-GaN layer.

[0051] The GaN nucleus layer, also called the nucleation layer or the initial growth layer, is a very thin GaN layer that is first grown on a substrate (such as sapphire, SiC, etc.) during the GaN epitaxial growth process. This thin film is crucial for the subsequent growth of high-quality GaN epitaxial layers.

[0052] Exemplarily, the epitaxial layer is grown by metal organic chemical vapor deposition (MOCVD) and includes a layer of p- + -GaN (Mg doping concentration is 10 20 cm -3 ), a layer of p-GaN with a thickness of 100nm (Mg doping concentration of 10 19 cm -3 ), a layer of n-GaN with a thickness of 5 μm (silicon doping concentration of 1-3×10 16 cm -3 ) and a layer of n with a thickness of 1.5 μm + -GaN (silicon doping concentration is 10 18 cm -3 ), which are all grown on sapphire substrates.

[0053] In a preferred embodiment of the present invention, Figure 2As shown, a multi-level junction terminal structure of a vertical GaN diode includes: a sapphire substrate, a GaN nodule layer is grown on the sapphire substrate; a silicon-doped n+-GaN layer is grown on the GaN nodule layer, a silicon-doped n-GaN layer is grown on the n+-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p+-GaN layer is grown on the p-GaN layer; etching from the p+-GaN layer to the n+-GaN layer, and preparing a negative electrode on the surface of the n+-GaN layer; etching from the p+-GaN layer to the p-GaN layer to form a continuous multi-level step, and preparing a positive electrode on the surface of the p+-GaN layer; the embodiment of the present invention uses a GaN diode with a multi-level step terminal structure designed with elliptical boundary fitting. The following takes this structure as an example to describe in detail various implementation methods.

[0054] In the embodiment of the present invention, the design principle of the multi-stage junction terminal is as follows: Figure 3 Calculated as shown. For the design of the junction terminal, two principles are often followed. One is that the amount of charge introduced along the direction of the junction terminal is gradually reduced; the other is to expand the depletion region of the device under reverse bias as much as possible, so that the electric field inside the device is relatively uniform. Therefore, the size of the multi-step step is obtained by fitting the elliptical boundary, and the area of ​​the rectangular area formed by the multi-step step is equal to the integral area of ​​the corresponding elliptical boundary. The width of the multi-step step is set in a manner that includes setting a higher step height near the edge of the step and setting a lower step height near the center of the step. The width of the multi-step step is set in a manner that includes setting a wider step width near the edge of the step and setting a narrower step width near the center of the step. Under this design, the height of the multi-step step and the width of the multi-step step satisfy the following formula:

[0055]

[0056] Where L is the total length of the junction terminal, x is the step width, y is the step height, and T n Represents the total height of the junction terminal, where the height of the junction terminal does not include the thickness of the positive electrode.

[0057] It is understandable that in practical applications, the number of multiple steps is limited, and the actual step height and step width can satisfy the above formula within a certain error range.

[0058] Based on the above embodiments, Figure 3 As shown, the present invention assumes that in the junction terminal extension region, the potential lines at the edge of the depletion region are elliptical in distribution. In this way, the distribution of carriers in p-GaN can be calculated based on the charge conservation law:

[0059]

[0060] Where ρ(x) represents the charge density distribution of p-GaN along the x direction, N * A represents the concentration of activated acceptors in p-GaN, Tp-GaN represents the thickness of p-GaN, and L represents the total length of the junction terminal.

[0061] The embodiment of the present invention uses multiple rectangular step region junction terminals to fit the elliptical curve, and divides the junction terminal extension structure into multiple regions to approximate the effect of the elliptical boundary. Since the electric field is more concentrated closer to the edge, it means that the potential change at the boundary will be more drastic. From the perspective of mathematical fitting accuracy, the smallest possible rectangle should be used for fitting at the edge where the potential changes drastically.

[0062] It should be noted that due to the existence of the edge electric field concentration effect, the electric field peak will appear at the edge position, which means that the change in potential is most drastic at the edge. The embodiment of the present invention uses an elliptical terminal to disperse the electric field, and due to the limited number of steps in the actual design, the elliptical shape can only be fitted as much as possible. Therefore, at the edge position, the embodiment of the present invention sets a denser step width distribution. Taking 4 steps as an example, from the inside to the outside, the step width ratio is 9:7:5:3. In order to ensure that the amount of charge in each step is close to the amount of charge in the elliptical distribution, the present invention designs each step in its interval to satisfy the area of ​​the rectangle equal to the integral of the elliptical boundary in the interval.

[0063] like Figure 4 As shown, the width of the step junction terminal designed by the present invention complies with the principle that the closer to the boundary, the smaller the width, ensuring that a smaller rectangular junction terminal is used to fit the boundary as much as possible; due to the small number of steps, in order to ensure that the charge amount is close to the derived charge amount, the present invention designs each step within its interval to satisfy that the area of ​​the rectangle is equal to the integral of the ellipse boundary within the interval. Figure 4 As shown, taking the four-step step as an example, the width and height of each junction terminal can be obtained. The height and length parameters of each JTE are shown in Table 1.

[0064] Table 1 Height and length of JTE

[0065] JTE height and width (nm) JTE1 0.33×120 JTE2 0.61×120 JTE3 0.79×120 JTE4 0.93×120

[0066] In an embodiment of the present invention, a method for preparing a multi-level junction terminal structure of a vertical GaN diode, wherein etching from a p+-GaN layer to an n+-GaN layer comprises:

[0067] A GaN nodule layer is grown on a sapphire substrate;

[0068] A silicon-doped n+-GaN layer is grown on the GaN nodule layer;

[0069] A silicon-doped n-GaN layer is grown on the n+-GaN layer;

[0070] A magnesium-doped p-GaN layer is grown on the n-GaN layer;

[0071] A magnesium-doped p+-GaN layer is grown on the p-GaN layer;

[0072] Etching from the p+-GaN layer to the n+-GaN layer;

[0073] Etching from the p+-GaN layer to the p-GaN layer to form a continuous multi-step;

[0074] Prepare a positive electrode on the surface of the p+-GaN layer, and prepare a negative electrode on the surface of the n+-GaN layer;

[0075] The sizes of the multiple steps are obtained by fitting the boundaries of an ellipse.

[0076] In an embodiment of the present invention, etching from the p+-GaN layer to the n+-GaN layer includes:

[0077] Depositing a silicon dioxide mask on the surface of the p+-GaN layer;

[0078] Using photolithography, the desired mesa pattern is transferred to the mask, leaving the portion not covered by the mask;

[0079] Etching from the p+-GaN layer to the n+-GaN layer by chemical etching or physical etching to remove the hierarchical structure not protected by the mask and form the required mesa structure;

[0080] The silicon dioxide mask is removed using an acidic solution.

[0081] In an embodiment of the present invention, etching from the p+-GaN layer to the p-GaN layer to form a continuous multi-step includes:

[0082] Depositing a silicon dioxide mask on the surface of the p+-GaN layer;

[0083] Using photolithography technology to transfer the desired mesa pattern to a mask, and etching the silicon dioxide mask to expose the p-GaN region that needs to be exposed;

[0084] The p-GaN is etched by physical etching ICP, from the p+-GaN layer to the p-GaN layer;

[0085] In the process of forming each step, repeating the photolithography and ICP etching operations, and finally removing the hierarchical structure not protected by the mask; forming the desired mesa structure; wherein the size of the multiple steps is obtained by fitting the ellipse boundary;

[0086] The silicon dioxide mask is removed using an acidic solution.

[0087] In an embodiment of the present invention, preparing a positive electrode on the surface of the p+-GaN layer and preparing a negative electrode on the surface of the n+-GaN layer includes:

[0088] Depositing Ni / Au metal on the surface of the p+-GaN layer, and performing rapid thermal annealing after the deposition is completed;

[0089] An ohmic contact Ti / Al / Ti / Au metal is formed on the surface of the n+-GaN layer.

[0090] In an embodiment of the present invention, the size of the multiple steps is obtained by fitting the ellipse boundary and includes:

[0091] Dividing the multi-level junction terminal extension structure into corresponding multiple rectangular areas;

[0092] The size of each level of junction terminal is calculated by fitting multiple rectangular areas through elliptical boundaries.

[0093] The following is a detailed description of each preparation process:

[0094] First, the present invention needs to perform Mesa etching on the device. The Mesa etching of the embodiment of the present invention uses silicon dioxide (SiO2). Next, the exposed area is removed by chemical etching or physical etching to form a step-like structure or a platform-like structure. After that, the silicon dioxide is removed by dry etching, and then the photoresist is cleaned to prepare for etching the GaN layer below.

[0095] Mesa etching is a process technology used to create specific geometric shapes on the surface of semiconductor materials. This process usually involves forming a raised area on the surface of the semiconductor material, which is called a "table" (Mesa). Mesa etching is often used to manufacture semiconductor devices such as laser diodes, solar cells, high-frequency transistors, etc., as well as in the fields of microelectromechanical systems (MEMS) and nanotechnology.

[0096] The basic steps of Mesa etching are as follows: Deposit mask material: First, deposit a layer of resist or other mask material on the surface of the semiconductor material. Pattern mask: Use photolithography or other methods to transfer the desired pattern to the mask, leaving the part not covered by the mask. Etching: Use chemical etching (wet etching) or plasma etching (dry etching) to remove the semiconductor material not protected by the mask to form the desired mesa structure. Remove mask: After etching is completed, remove the mask material.

[0097] Different from the vertical structure GaN epitaxial structure, the present invention uses a GaN epitaxial wafer with a sapphire substrate. Sapphire does not have conductive properties, so the electrode needs to be deposited on the side of the device. Therefore, Mesa etching needs to be etched at least to n + -GaN layer, the etching depth of this embodiment is about 6μm. After the Mesa etching is completed, it is fully immersed in BOE (HF:HCl=1:6) solution to remove the SiO2 mask. Subsequently, a four-step etching process is performed on p-GaN to realize the design of multi-step terminal, the order is from outside to inside, and SiO2 is still used as the mask. Taking the height and length parameters of each JTE in Table 1 as an example, the etching time of each JTE is shown in Table 2.

[0098] Table 2 JTE etching time

[0099] Etching time(s) JTE1 100.8 JTE2 64.8 JTE3 50.4 JTE4 25.2

[0100] In order to minimize etching damage and achieve precise control, the present invention requires low-power ICP slow etching. By reducing the power of ICP, slow ICP etching with an etching rate of 0.33nm / s is achieved. After etching, the SiO2 mask is washed off with BOE. The step after the multi-step terminal etching is completed is electrode preparation, and the technology used is electron beam evaporation. Since the P-type GaN ohmic contact requires high-temperature annealing while the N-type GaN ohmic contact does not, the present invention needs to prepare the positive electrode first. The positive electrode of the process of the present invention uses Ni / Au with a thickness of 25 / 50nm. After deposition, rapid thermal annealing (RTP, Rapidthermalannealing) is performed. The annealing conditions are annealing for 200s at a temperature of 600°C in an air atmosphere. After that, the ohmic contact of the negative electrode is made. The negative electrode ohmic contact uses Ti / Al / Ti / Au with a thickness of 20 / 150 / 50 / 50nm. At this point, a GaN diode device with a multi-step terminal can be prepared.

[0101] In order to verify the effectiveness of the multi-level step terminal structure (sample C) proposed in the present invention in modulating the electric field, the present invention prepared two comparative diodes on the same epitaxial structure: one without junction terminal (sample A), and the other with uniform multi-level step junction terminal (sample B, the same as the simulation model in Chapter 3). Figure 5 (a) and (b) compare the maximum and average breakdown voltages of the three devices, respectively. Ten breakdown voltage tests were performed on each type of device, and the average value was calculated. The error bars represent the range of these breakdown voltage tests. The results show that the average breakdown voltage of the JTE diode proposed in the present invention is 1280V, where Figure 5The 1.32 kV in (a) is the highest breakdown voltage data in the test, which is higher than the breakdown voltage of the diodes without JTE and with uniform JTE.

[0102] The present invention simulates and analyzes the electric field of three devices under reverse bias (Silvaco TCAD). In a diode, when there is no junction terminal structure, the edge electric field concentration phenomenon will cause the electric field intensity at the edge to be higher than that in the internal area of ​​the device. This phenomenon is called the electric field concentration effect. By observing Figure 6 (a), the present invention can clearly see this effect. However, after introducing the multi-level step junction termination structure, such as Figure 6 As shown in (b) and (c), the electric field concentration phenomenon has been significantly alleviated, which indicates that the junction terminal structure effectively reduces the internal electric field peak. Specifically, the electric field peak of the diode with a multi-step terminal structure using elliptical boundary fitting is significantly reduced compared to the diode with a uniform multi-step terminal.

[0103] In summary, the diode having the junction terminal structure of the present invention can significantly improve the breakdown voltage of the GaN diode.

[0104] It can be understood that the multi-level junction terminal structure and preparation method of a vertical GaN diode in the present invention belong to the same inventive concept, and their corresponding features can be referenced to each other, and the present invention does not make specific limitations on this.

[0105] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A multi-level junction termination structure of a vertical GaN diode, characterized in that: include: A sapphire substrate, on which a GaN nodule layer is grown; a silicon-doped n+-GaN layer is grown on the GaN nodule layer, a silicon-doped n-GaN layer is grown on the n+-GaN layer, a magnesium-doped p-GaN layer is grown on the n-GaN layer, and a magnesium-doped p+-GaN layer is grown on the p-GaN layer; etching from the p+-GaN layer to the n+-GaN layer, and providing a negative electrode on the surface of the n+-GaN layer; etching from the p+-GaN layer to the p-GaN layer to form continuous multi-step steps, and providing a positive electrode on the surface of the p+-GaN layer; wherein the size of the multi-step steps is obtained by fitting an ellipse boundary.

2. The multi-level junction termination structure of a vertical GaN diode according to claim 1, characterized in that: The size of the multi-steps is obtained by fitting the ellipse boundary, and the area of ​​the rectangular region including the multi-steps is equal to the integral area of ​​the corresponding ellipse boundary.

3. The multi-level junction terminal structure of a vertical GaN diode according to claim 2, characterized in that: The width of the multi-step steps is set in a manner that includes setting a higher step height near the edge of the step and setting a lower step height near the center of the step.

4. The multi-level junction terminal structure of a vertical GaN diode according to claim 2, characterized in that: The width of the multi-step steps is set in a manner that a wider step width is set near the edge of the step, and a narrower step width is set near the center of the step.

5. The multi-level junction termination structure of a vertical GaN diode according to claim 3 or 4, characterized in that: The height of the multiple steps and the width of the multiple steps satisfy the following formula: Where L is the total length of the junction terminal, x is the step width, y is the step height, and T n Represents the total height of the junction terminal.

6. A method for preparing a multi-level junction terminal structure of a vertical GaN diode, characterized in that: The method comprises: A GaN nodule layer is grown on a sapphire substrate; A silicon-doped n+-GaN layer is grown on the GaN nodule layer; A silicon-doped n-GaN layer is grown on the n+-GaN layer; A magnesium-doped p-GaN layer is grown on the n-GaN layer; A magnesium-doped p+-GaN layer is grown on the p-GaN layer; Etching from the p+-GaN layer to the n+-GaN layer; Etching from the p+-GaN layer to the p-GaN layer to form continuous multi-steps; Prepare a positive electrode on the surface of the p+-GaN layer, and prepare a negative electrode on the surface of the n+-GaN layer; The sizes of the multiple steps are obtained by fitting the boundaries of an ellipse.

7. The method for preparing a multi-level junction terminal structure of a vertical GaN diode according to claim 6, characterized in that: The etching from the p+-GaN layer to the n+-GaN layer comprises: Depositing a silicon dioxide mask on the surface of the p+-GaN layer; Using photolithography, the desired mesa pattern is transferred to the mask, leaving the portion not covered by the mask; Etching from the p+-GaN layer to the n+-GaN layer by chemical etching or physical etching to remove the hierarchical structure not protected by the mask and form the required mesa structure; The silicon dioxide mask is removed using an acidic solution.

8. The method for preparing a multi-level junction terminal structure of a vertical GaN diode according to claim 6, characterized in that: The etching from the p+-GaN layer to the p-GaN layer to form a continuous multi-step comprises: Depositing a silicon dioxide mask on the surface of the p+-GaN layer; Using photolithography technology to transfer the desired mesa pattern to a mask, and etching the silicon dioxide mask to expose the p-GaN region that needs to be exposed; The p-GaN is etched by physical etching ICP from the p+-GaN layer to the p-GaN layer; In the process of forming each step, repeating the photolithography and ICP etching operations, and finally removing the hierarchical structure not protected by the mask; forming the desired mesa structure; wherein the size of the multiple steps is obtained by fitting the ellipse boundary; The silicon dioxide mask is removed using an acidic solution.

9. The method for preparing a multi-level junction terminal structure of a vertical GaN diode according to claim 6, characterized in that: Preparing a positive electrode on the surface of the p+-GaN layer and preparing a negative electrode on the surface of the n+-GaN layer comprises: Depositing Ni / Au metal on the surface of the p+-GaN layer, and performing rapid thermal annealing after the deposition is completed; An ohmic contact Ti / Al / Ti / Au metal is formed on the surface of the n+-GaN layer.

10. The method for preparing a multi-level junction terminal structure of a vertical GaN diode according to claim 6, characterized in that: The dimensions of the multi-step steps are obtained by fitting the ellipse boundary and include: Dividing the multi-level junction terminal extension structure into corresponding multiple rectangular areas; The size of each level of junction terminal is calculated by fitting multiple rectangular areas through elliptical boundaries.

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