Silicon carbide transistor device and power supply circuit

Abstract

The utility model provides a silicon carbide transistor device and a power supply circuit. The silicon carbide transistor device comprises a shielding groove and a well region which are located in an epitaxial layer of a substrate and are isolated from each other; the source injection region and the well region extraction region are located in the well region; the first part of the grid is located above the epitaxial layer, and the second part of the grid is located in the shielding groove; the gate oxide layer is positioned between the first part of the gate and the epitaxial layer; the interlayer dielectric layer covers the surface of the first part of the gate; the second oxide layer is positioned between the second part of the grid electrode and the shielding groove; the thick oxide layer with the thickness larger than that of the gate oxide layer is arranged at the bottom of the shielding groove, and the depth of the shielding groove is set to be smaller than or equal to that of the well region, so that a depletion region can be formed at the bottom of the shielding groove more quickly along with increase of drain voltage in a device turn-off state; and the breakdown voltage of the device and the reliability of the gate oxide layer in a turn-off state can be further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide transistor device and a power supply circuit. Background Art

[0002] As a new generation of power semiconductor devices, SiC (silicon carbide) power semiconductor devices have lower conduction losses, faster switching frequency, and better thermal characteristics compared to traditional silicon-based devices. MOSFET (metal-oxide semiconductor Field Effect Transistor), which is the mainstream product of power semiconductor devices, is highly favored among SiC materials.

[0003] However, due to the material properties of SiC itself, SiC MOSFET (SiC transistor or silicon carbide transistor) devices face many technical challenges, such as the JFET region resistance problem of SiC MOSFET devices, and the voltage resistance and reliability problems of the gate oxide layer. Utility Model Content

[0004] In order to solve the above technical problems, the present application provides a silicon carbide transistor device and a power supply circuit to reduce the JFET region resistance of the device, improve the gate oxide layer reliability of the device in the off state, and increase the breakdown voltage of the device.

[0005] According to a first aspect of the present application, a silicon carbide transistor device is provided, characterized in that it comprises:

[0006] An epitaxial layer, located on a first surface of a substrate, wherein the epitaxial layer and the substrate have a first doping type;

[0007] a shielding trench located in the epitaxial layer;

[0008] a well region, located in the epitaxial layer, the well region being isolated from the shielding trench and located outside the shielding trench, the well region having a second doping type;

[0009] A source injection region, located in the well region, the source injection region having a first doping type;

[0010] A well region lead-out region, located in the well region, the well region lead-out region having a second doping type;

[0011] a gate including a first portion located above the epitaxial layer and a second portion located within the shield trench;

[0012] A first oxide layer, comprising a gate oxide layer located between the first portion of the gate and the epitaxial layer and an interlayer dielectric layer covering the surface of the first portion of the gate;

[0013] A second oxide layer is located between the second portion of the gate and the sidewall and bottom of the shielding trench, and the thickness of the second oxide layer located at the bottom of the shielding trench is greater than the thickness of the gate oxide layer;

[0014] A source metal layer, covering the surface of the interlayer dielectric layer and contacting the source injection region and the well region lead-out region to form a front metal electrode;

[0015] A drain metal layer is located on a second surface of the substrate opposite to the first surface, forming a back metal electrode,

[0016] Wherein, the depth of the shielding trench is less than or equal to the depth of the well region.

[0017] Optionally, the second oxide layer located at the bottom of the shielding trench and the second oxide layer located at the sidewall of the shielding trench have the same thickness.

[0018] Optionally, the silicon carbide transistor device further includes:

[0019] The source trench is located on a side of the source injection region away from the shielding trench.

[0020] Optionally, the bottom of the well region lead-out region is deeper than the bottom of the well region.

[0021] Optionally, the thickness of the second oxide layer located at the bottom of the shielding trench is greater than or equal to 2000 angstroms.

[0022] Optionally, the thickness of the gate oxide layer is in the range of 400 to 600 angstroms.

[0023] Optionally, the cross-sectional shape of the shielding groove includes at least one of an inverted trapezoid, a rectangle, a U-shape and an inverted stepped shape.

[0024] Optionally, the substrate is a silicon carbide substrate.

[0025] Optionally, the doping concentration of the epitaxial layer is lower than the doping concentration of the substrate.

[0026] According to a second aspect of the present application, a power supply circuit is provided, comprising a silicon carbide transistor device as described in any embodiment of the present application.

[0027] The beneficial effects of this application include at least:

[0028] The embodiment of the present application provides a planar silicon carbide transistor device. By adding a shielding trench structure in the planar silicon carbide transistor device and setting a thick oxide layer with a thickness greater than that of the gate oxide layer at the bottom of the shielding trench, the gate oxide electric field of the device can be reduced, and the breakdown voltage of the device and the reliability of the gate oxide layer in the off state are improved. At the same time, in the embodiment of the present application, the depth of the shielding trench is set to be less than or equal to the depth of the well region located outside the shielding trench. Compared with the scheme of setting the depth of the shielding trench to be greater than the depth of the well region located outside the shielding trench, the scheme disclosed in the embodiment of the present application can form a depletion region at the bottom of the shielding trench more quickly when the device is in the off state as the drain voltage increases, and can be laterally connected with the depletion region formed at the bottom of the well region to form protection, thereby further improving the breakdown voltage of the device and the reliability of the gate oxide layer in the off state.

[0029] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A cross-sectional view showing a planar silicon carbide transistor device;

[0031] Figure 2 A cross-sectional view of a silicon carbide transistor device provided according to a first embodiment of the present application is shown;

[0032] Figure 3 A cross-sectional view of a silicon carbide transistor device provided according to a second embodiment of the present application is shown;

[0033] Figure 4 A cross-sectional view of a silicon carbide transistor device provided according to a third embodiment of the present application is shown;

[0034] Figure 5 A cross-sectional view of a silicon carbide transistor device provided according to a fourth embodiment of the present application is shown;

[0035] Figures 6a to 6c A schematic diagram showing simulation results of a silicon carbide transistor device provided in an embodiment of the present application operating at different trench depths. DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0037] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0038] In the description of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or advantageous than other embodiments.

[0039] In the accompanying drawings, for the sake of clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements throughout. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that the words "first", "second", etc. do not limit the quantity and execution order, and the words "first", "second", etc. do not limit them to be necessarily different.

[0040] like Figure 1 As shown, a planar silicon carbide transistor device (such as a SiC MOSFET device) 100 generally includes: a substrate 110, an epitaxial layer 120 located on a first surface (such as an upper surface) of the substrate 110, a well region 130 located in the epitaxial layer 120, a source injection region 140 and a well region lead-out region 150 located in the well region 130, a gate 160 located on the upper surface of the epitaxial layer 120, an oxide layer 170, a source metal layer 180 covering the oxide layer 170, and a drain metal layer 190 located on a second surface (such as a lower surface) of the substrate 110.

[0041] In the planar SiC MOSFET device 100 , the oxide layer 170 includes a gate oxide layer (eg, SiO 2 ) located between the gate 160 and the epitaxial layer 120 and an interlayer dielectric layer covering the side and top surfaces of the gate 160 .

[0042] On the one hand, due to the high bandgap width and high P-region doping concentration, the SiC MOSFET device 100 requires a thinner gate oxide layer than the SiMOSFET device to obtain a reasonable threshold voltage and transconductance value. After applying a certain bias voltage (about 20V), the intrinsic electric field of the gate oxide layer of the SiC MOSFET device 100 can easily reach 5MV / cm. However, under the same conditions, the intrinsic electric field of the Si MOSFET device is only 3MV / cm, that is, the gate oxide layer of the SiC MOSFET device 100 is easily broken down.

[0043] On the other hand, the JFET region resistance of the planar SiC MOSFET device 100 accounts for the largest proportion of the total device resistance. Therefore, reducing the JFET region resistance is the key to optimizing the total resistance. In the SiC MOSFET device 100, the channel is formed at the interface between the epitaxial layer 120 and the gate oxide layer (i.e., the SiC-SiO2 interface). However, due to the SiC-SiO2 interface formed by the silicon carbide material, the defect density is much higher than that of Si-SiO2. These defects will capture electrons when electrons flow through, causing the electron mobility to decrease, thereby causing the resistivity of the JFET region to increase.

[0044] The above problems can be solved by increasing the gate voltage, reducing the thickness of the gate oxide layer, or reducing the threshold voltage of the device. However, these methods will increase the electric field strength in the gate oxide layer of the device, and too high an electric field strength is not conducive to the long-term reliability of the device. For example, the breakdown voltage of the gate oxide layer formed by -SiO2 material is generally 10MV / cm, but a field strength of more than 4MV / cm will increase the long-term potential failure rate of the device.

[0045] Furthermore, the embodiment of the present application further optimizes the planar silicon carbide transistor device. By introducing a shielding trench with a specific depth in the planar silicon carbide transistor device, a depletion region can be formed more quickly at the bottom of the shielding trench when the device is in the off state as the drain voltage increases, thereby further improving the breakdown voltage of the device and the reliability of the gate oxide layer in the off state, and reducing the resistance of the JFET region to a certain extent.

[0046] Figure 2 A cross-sectional view of a silicon carbide transistor device provided according to a first embodiment of the present application is shown, Figure 2As shown, the silicon carbide transistor device (also referred to as the device in this article) 200 disclosed in this embodiment includes: a substrate 211, having a first surface and a second surface opposite to the first surface; an epitaxial layer 212 located on the first surface of the substrate 211; a shielding trench 216 located in the epitaxial layer 212; a well region 213 located in the epitaxial layer 212, the well region 213 is isolated from the shielding trench 216 and is located outside the shielding trench 216; a source injection region 214 and a well region lead-out region 215 located in the well region 213; a gate 218, the gate 218 including a first portion (also referred to as a planar portion) located above the epitaxial layer 212 and a first portion located in the shielding trench 216. The second part of the portion (also referred to as the vertical part or the in-groove part); the first oxide layer 219, the first oxide layer 219 includes a gate oxide layer located between the planar part of the gate 218 and the epitaxial layer 212 and an interlayer dielectric layer covering the surface of the planar part of the gate 218; the second oxide layer 217 located between the in-groove part of the gate 218 and the sidewall and bottom of the shielding trench 216; the source metal layer 220 covering the surface of the interlayer dielectric layer of the first oxide layer 219 and contacting the source injection region 214 and the well region lead-out region 215 to form a front metal electrode; and, located on the second surface of the substrate 211, the drain metal layer 221 for forming a back metal electrode. It can be understood that the gate terminal (G) of the device 200 is led out by the gate 218, the source terminal (S) of the device 200 is led out by the source metal layer 220, and the drain terminal (D) of the device 200 is led out by the drain metal layer 221.

[0047] refer to Figures 2 to 5 In this paper, an N-type silicon carbide transistor device (i.e., SiC NMOSFET device) is mainly used as an example to illustrate the specific structure of the silicon carbide transistor device 200 disclosed in this embodiment. However, for a P-type silicon carbide transistor device (i.e., SiC PMOSFET device), the scheme disclosed in the embodiment of the present application is also equally applicable, and it is only necessary to interchange the doping type or ion implantation type of each region in the device.

[0048] exist Figure 2 In the example shown, the substrate 211 is, for example, a silicon carbide (SiC) substrate having an N-type doping type. The first surface of the substrate 211 is, for example, its upper surface, and the second surface of the substrate 211 is, for example, its lower surface.

[0049] The epitaxial layer 212 also has an N-type doping type, but the doping concentration of the epitaxial layer 212 is less than the doping concentration of the substrate 211. The thickness and resistivity of the epitaxial layer 212 can be adjusted according to the withstand voltage requirement of the device 200. The higher the withstand voltage requirement of the device 200, the thicker the epitaxial layer 212.

[0050] The well region 213 is a P-type well region (PW) having a P-type doping type, and in the cross-sectional view of the device 200, the well region 213 is located on the left and right sides of the shielding groove 216. Optionally, in the corresponding three-dimensional structure, the well region 213 can be, for example, vertically arranged along the horizontal plane where the upper surface of the epitaxial layer 212 is located, or can be arranged around the shielding groove 216. The present application does not impose strict limitations on this.

[0051] The source injection region 214 is an N+ injection region, and the well region lead-out region 215 is a P+ injection region. In the horizontal direction, the source injection region 214 is closer to the inner side of the device than the well region lead-out region 215 .

[0052] A dielectric layer, namely, a second oxide layer 217, is attached to the inner sidewall and the bottom surface of the shielding trench 216 (due to Figure 2 In the example of FIG. 1 , the second oxide layer 217 and the first oxide layer 219 are made of the same material, such as silicon oxide. Figure 2 The two are connected as one).

[0053] The first part and the second part of the gate 218 are made of, for example, polysilicon material, that is, the area in the shielding groove 216 that is not filled by the second oxide layer 217 is filled with polysilicon, and since the first part and the second part of the gate 218 are sampled from the same material, they can be manufactured as an integral part in the same process step during the molding process.

[0054] Optionally, in Figure 2 In the example shown, the cross-sectional shape of the shielding trench 216 and the cross-sectional shape of the second portion of the gate 218 filled therein are inverted trapezoidal. However, other implementation shapes are also feasible, for example, Figure 4 In the example shown, the cross-sectional shape of the shielding trench 216 and the cross-sectional shape of the second portion of the gate 218 filled therein may also be rectangular, inverted stepped (eg, Figure 4 As shown), U-shaped (as Figure 5 shown) etc.

[0055] In this embodiment, the thickness of the second oxide layer 217 located at the bottom of the shielding trench 216 is greater than the thickness of the gate oxide layer.

[0056] Optionally, in some examples, the thickness of the second oxide layer at the bottom of the shielding trench 216 is greater than or equal to 2000 angstroms.

[0057] Optionally, in some examples, the thickness of the gate oxide layer in the first oxide layer 219 is in the range of 400 to 600 angstroms.

[0058] It can be understood that since a shielding trench 216 is provided in the device 200 and a thick oxide layer is introduced at the bottom of the shielding trench 216, when the device is in the off state, the thick oxide layer enables the shielding trench 216 to withstand a higher reverse breakdown voltage, which is equivalent to improving the voltage resistance of the device 200 at the position of the shielding trench 216. At the same time, the shielding trench 216 is also able to form a protection area in the lateral direction together with the depletion area formed by the adjacent P-type well region 213 on the side of the shielding trench 216, thereby reducing the electric field strength of the gate oxide layer of the device 200 at point A, effectively avoiding the risk of breakdown of the gate oxide layer of the device in the off state, and improving the reliability of the gate oxide layer of the device.

[0059] Furthermore, in this embodiment, the depth of the shielding trench 216 is set to be less than or equal to the depth of the well region 213. Figure 6a and Figure 6b ,in, Figure 6a FIG. 2 shows a schematic diagram of a working simulation result when the depth of the shielding trench 216 is less than the depth of the well region 213 . Figure 6b FIG. 2 shows a schematic diagram of the working simulation result when the depth of the shielding trench 216 is greater than the depth of the well region 213. Figure 6a and Figure 6b It can be concluded that, under the same drain voltage, compared with the scheme of setting the depth of the shielding trench 216 to be greater than the depth of the well region 213, in the embodiment of the present application, by setting the depth of the shielding trench 216 to be less than the depth of the well region 213, when the device 200 is in the off state, the bottom of the shielding trench 216 can also be depleted (in the accompanying drawings, the green area above the depletion line is the depletion area). On the one hand, the electric field strength at the bottom of the shielding trench 216 can be further reduced. On the other hand, under the same drain voltage, the embodiment of the present application can more quickly form the shielding trench 216 around or on both sides based on the P-type well region 213. The depletion regions are interconnected, that is, when the drain voltage is low, a coherent lateral depletion region can be formed at a deeper position of the epitaxial layer 212, and the problem of being blocked due to the shielding groove being too deep will not occur. Therefore, the gate oxide layer of the device can be protected more quickly. As the drain voltage is further increased, the breakdown position of the device 200 in the embodiment of the present application when avalanche breakdown occurs is near the planar PN junction corresponding to C, compared with the breakdown near the cylindrical PN junction corresponding to B in the related scheme. The scheme of the present application is equivalent to improving the breakdown position of the device 200 in the off state, which can improve the reliability of the gate oxide layer of the device and improve the breakdown voltage of the device.

[0060] In addition, reference Figure 6c , Figure 6cFIG. 1 shows a schematic diagram of simulation results when the device works at different trench depths, wherein the ordinate represents the electric field strength, the red line represents the simulation result when the shielding trench depth of the device is less than the P-type well region depth, and the green line represents the simulation result when the shielding trench depth of the device is greater than the P-type well region depth. Figure 6c It can be seen that under the same drain voltage, when the depth of the shielding groove 216 is set to be greater than the depth of the P-type well region 213, the electric field strength at A and B in the device 200 is relatively large, and when the depth of the shielding groove 216 is set to be less than the depth of the P-type well region 213, the electric field strength at A and B in the device 200 is relatively small. That is to say, compared with the solution of setting the depth of the shielding groove 216 to be greater than the depth of the P-type well region 213, in the embodiment of the present application, by setting the depth of the shielding groove 216 to be less than the depth of the P-type well region 213, the electric field strength at A and B in the device 200 is effectively reduced, so that the P-type well region 213 can better protect the gate oxide layer of the device 200 together with the shielding groove 216 when it is laterally depleted.

[0061] In some preferred embodiments, the portion of the second oxide layer 217 located at the bottom of the shielding trench 216 and the portion of the second oxide layer 217 located at the side wall of the shielding trench 216 have the same thickness. In this way, the portion of the second oxide layer 217 located at the bottom of the shielding trench 216 and the portion of the second oxide layer 217 located at the side wall of the shielding trench 216 only need to be deposited once during the process manufacturing process, thereby simplifying the process steps and improving efficiency.

[0062] Optionally, the source injection region 214 and the well region lead-out region 215 may be formed at the same height (scheme not shown), or may be formed at different heights, such as Figure 2 As shown, Figure 2 In the example shown, the formation position of the well region lead-out region 215 is lower than the formation position of the source injection region 214. In other words, Figure 2 In the example shown, the silicon carbide transistor device 200 further includes: a source trench 222 located on the left side of the source injection region 214 (i.e., the side away from the shielding trench 216), and at this time, the well region lead-out region 215 is formed below the source trench 222. It can be understood that by providing the source trench 222, the source metal layer 220 can contact the top surface and the side surface of the source injection region 214 at the same time, thereby increasing the contact area between the source metal layer 220 and the source injection region 214, and improving the signal transmission quality at the source end of the device 200 to a certain extent.

[0063] In some other examples, reference Figure 3, the depth of the source trench 222 is greater than the depth of the source injection region 214. At this time, the well region lead-out region 215 includes a portion formed below the bottom of the source trench 222 and a portion formed on at least part of the outer wall of the source trench 222, so as to isolate the source metal layer 220 formed in the source trench 222 from contacting each other with the well region 213.

[0064] Further, in Figure 3 In the example shown, the bottom of the well region lead-out region 215 is deeper than the bottom of the P-type well region 213. In this way, a deeper depletion protection can be formed in the epitaxial layer 212 of the device 200, which can further reduce the electrical stress of the gate oxide layer when the device is turned off. At the same time, the deeper depletion protection can also reduce the base resistance of the device, which is beneficial to improving the EAS capability of the device.

[0065] In addition, an embodiment of the present application further discloses a power supply circuit, which includes the silicon carbide transistor device 200 mentioned in any of the aforementioned embodiments.

[0066] In summary, the embodiment of the present application adds a shielding trench structure to the planar silicon carbide transistor device and sets a thick oxide layer with a thickness greater than the gate oxide layer at the bottom of the shielding trench, thereby reducing the gate oxide electric field of the device and improving the breakdown voltage of the device and the reliability of the gate oxide layer in the off state. At the same time, the embodiment of the present application also sets the depth of the shielding trench to be less than or equal to the depth of the well region located outside it. Compared with the scheme of setting the depth of the shielding trench to be greater than the depth of the well region located outside it, the scheme disclosed in the embodiment of the present application can form a depletion region at the bottom of the shielding trench faster when the device is in the off state as the drain voltage increases, and can be laterally connected with the depletion region formed at the bottom of the well region to form protection, thereby further improving the breakdown voltage of the device and the reliability of the gate oxide layer in the off state.

[0067] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.

Claims

1. A silicon carbide transistor device, characterized in that: include: An epitaxial layer, located on a first surface of a substrate, wherein the epitaxial layer and the substrate have a first doping type; a shielding trench located in the epitaxial layer; a well region, located in the epitaxial layer, the well region being isolated from the shielding trench and located outside the shielding trench, the well region having a second doping type; A source injection region, located in the well region, the source injection region having a first doping type; A well region lead-out region, located in the well region, the well region lead-out region having a second doping type; a gate including a first portion located above the epitaxial layer and a second portion located within the shield trench; A first oxide layer, comprising a gate oxide layer located between the first portion of the gate and the epitaxial layer and an interlayer dielectric layer covering the surface of the first portion of the gate; A second oxide layer is located between the second portion of the gate and the sidewall and bottom of the shielding trench, and the thickness of the second oxide layer located at the bottom of the shielding trench is greater than the thickness of the gate oxide layer; A source metal layer, covering the surface of the interlayer dielectric layer and contacting the source injection region and the well region lead-out region to form a front metal electrode; A drain metal layer is located on a second surface of the substrate opposite to the first surface, forming a back metal electrode, Wherein, the depth of the shielding trench is less than or equal to the depth of the well region.

2. The silicon carbide transistor device according to claim 1, wherein: The second oxide layer located at the bottom of the shielding trench and the second oxide layer located at the sidewall of the shielding trench have the same thickness.

3. The silicon carbide transistor device according to claim 1, wherein: The silicon carbide transistor device further comprises: The source trench is located on a side of the source injection region away from the shielding trench.

4. The silicon carbide transistor device according to claim 1, wherein: The bottom of the well region lead-out region is deeper than the bottom of the well region.

5. The silicon carbide transistor device according to claim 1 or 2, wherein: The thickness of the second oxide layer located at the bottom of the shielding trench is greater than or equal to 2000 angstroms.

6. The silicon carbide transistor device according to claim 1, wherein: The thickness of the gate oxide layer is in the range of 400 to 600 angstroms.

7. The silicon carbide transistor device according to claim 1, wherein: The cross-sectional shape of the shielding groove includes at least one of an inverted trapezoid, a rectangle, a U-shape and an inverted step shape.

8. The silicon carbide transistor device according to claim 1, wherein: The substrate is a silicon carbide substrate.

9. The silicon carbide transistor device according to claim 1 or 8, wherein: The doping concentration of the epitaxial layer is lower than the doping concentration of the substrate.

10. A power supply circuit comprising: A silicon carbide transistor device as claimed in any one of claims 1 to 9.

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