Rate matching method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a rate matching method and device, electronic equipment, a chip and a storage medium, and the method comprises the steps: responding to the condition that coded data transmitted by a PUSCH meets a set condition, carrying out the bit filling of the coded data based on a first filling bit, obtaining the filled coded data, and storing the filled coded data in a single-port random access memory; executing a rate matching process of set times on the filling coding data in the single-port random access memory; wherein the data to be subjected to rate matching in any rate matching process does not comprise the first filling bit, so that memory fragments and storage overhead are reduced, the memory utilization efficiency is improved, the storage area is saved, and the rate matching throughput rate and accuracy rate are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a rate matching method, device, electronic device, chip and storage medium. Background Art

[0002] With the rapid development and widespread application of communication technology, channel transmission environment and business requirements are becoming increasingly complex and changeable. In order to cope with different channel conditions and service quality requirements and ensure the efficiency and reliability of data transmission, it is necessary to rate match the transmitted data so that the data transmission rate between the sender and the receiver can match the actual transmission capacity of the channel. Therefore, how to achieve rate matching of transmitted data is very important. Summary of the invention

[0003] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0004] To this end, the present disclosure proposes a rate matching method, device, electronic device, chip and storage medium, so that when the encoded data meets the set conditions, the first filling bit is used to perform bit filling on the encoded data to obtain filled encoded data, so that the filled encoded data is an integer multiple of the storage unit, and then the filled encoded data is stored in a single-port random access memory (Random Access Memory, RAM for short), thereby reducing memory fragmentation and storage overhead, improving memory utilization efficiency and saving storage area. Finally, multiple rate matching processes are performed on the stored filled encoded data, wherein the first filling bit is not included in the data to be rate matched in any rate matching process, effectively avoiding the problem of a decrease in the rate matching throughput that may be caused when the proportion of the first filling bit in the data to be rate matched is large, thereby improving the rate matching throughput and accuracy.

[0005] On the one hand, an embodiment of the present disclosure proposes a rate matching method, including: obtaining coded data transmitted by a physical uplink shared channel PUSCH; in response to the coded data satisfying a set condition, bit-filling the coded data based on a first filling bit to obtain filled coded data; storing the filled coded data in the single-port random access memory; performing a rate matching process for a set number of times on the filled coded data in the single-port random access memory; wherein the data to be rate matched in any rate matching process does not include the first filling bit.

[0006] On the other hand, an embodiment of the present disclosure proposes a rate matching device, including: an acquisition module, used to acquire coded data transmitted by a physical uplink shared channel PUSCH; a first filling module, used to bit-fill the coded data based on a first filling bit in response to the coded data satisfying a set condition to obtain filled coded data; a storage module, used to store the filled coded data in the single-port random access memory; a processing module, performing a rate matching process for a set number of times on the filled coded data in the single-port random access memory; wherein the data to be rate matched in any rate matching process does not include the first filling bit.

[0007] Another aspect of the present disclosure provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the rate matching method as described in the above-mentioned first aspect of the embodiment.

[0008] Another aspect of the present disclosure provides a chip, including a processing circuit, wherein the processing circuit is configured to execute the rate matching method as described in the above-mentioned first aspect of the embodiment.

[0009] Another aspect of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the rate matching method as described in the above aspect.

[0010] Another aspect of the present disclosure provides a computer program product on which a computer program is stored. When the program is executed by a processor, the rate matching method as described in the above aspect is implemented.

[0011] The rate matching method proposed in the present disclosure obtains coded data transmitted by a physical uplink shared channel PUSCH; in response to the coded data satisfying a set condition, the coded data is bit-filled based on a first filling bit to obtain filled coded data; the filled coded data is stored in the single-port random access memory; a set number of rate matching processes are performed on the filled coded data in the single-port random access memory; wherein the data to be rate matched in any rate matching process does not include the first filling bit, thereby, when the coded data meets the set condition, the first filling bit is used for bit filling to obtain filled coded data, so that the filled coded data is an integer multiple of the storage unit, and then, the filled coded data is stored in the single-port random access memory, thereby reducing memory fragmentation and storage overhead, improving memory utilization efficiency and saving storage area, and finally, performing multiple rate matching processes on the stored filled coded data, wherein the data to be rate matched in any rate matching process does not include the first filling bit, effectively avoiding the problem of rate matching throughput reduction that may be caused when the proportion of the first filling bit in the data to be rate matched is large, thereby improving the rate matching throughput and accuracy.

[0012] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0014] Figure 1 A schematic diagram of a flow chart of a rate matching method provided in an embodiment of the present disclosure;

[0015] Figure 2 A schematic diagram of a flow chart of another rate matching method provided by an embodiment of the present disclosure;

[0016] Figure 3 A schematic diagram of a column transformation sequence provided in an embodiment of the present disclosure;

[0017] Figure 4 A schematic diagram of a column transformation sequence and a corresponding fill indication sequence provided by an embodiment of the present disclosure;

[0018] Figure 5 A schematic diagram of a flow chart of another rate matching method provided by an embodiment of the present disclosure;

[0019] Figure 6 A schematic diagram of a flow chart of another rate matching method provided by an embodiment of the present disclosure;

[0020] Figure 7A schematic diagram of a flow chart of another rate matching method provided by an embodiment of the present disclosure;

[0021] Figure 8 A schematic diagram of a first target row in a first target storage address provided by an embodiment of the present disclosure;

[0022] Fig. 9 A schematic diagram of a first target row in a first target storage address provided by an embodiment of the present disclosure;

[0023] Fig.10 A schematic diagram of a flow chart of another rate matching method provided by an embodiment of the present disclosure;

[0024] Fig.11 A schematic diagram of reading a column transformation sequence provided by an embodiment of the present disclosure;

[0025] Fig.12 A schematic diagram of a flow chart of another rate matching method provided by an embodiment of the present disclosure;

[0026] Fig.13 A schematic diagram of a flow chart of another rate matching method provided by an embodiment of the present disclosure;

[0027] Fig.14 A schematic diagram of a storage structure of encoded data in a single-port RAM provided by an embodiment of the present disclosure;

[0028] Fig.15 A schematic diagram of the structure of a rate matching device provided in an embodiment of the present disclosure;

[0029] Fig.16 A block diagram of an electronic device provided in an embodiment of the present disclosure;

[0030] Fig.17 It is a schematic diagram of the structure of the chip proposed in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0032] In the related technology, the following two schemes are mainly used to achieve rate matching of transmitted data. One of them is to ignore the padding bits when taking the encoded data, remove the padding bits when the rate matching is output, and splice the data after removing the padding bits for output. Although this processing method is simple, when the proportion of padding bits to the total data volume is large, it will greatly reduce the throughput of rate matching. When 8 parallel rate matching is performed, the throughput in the worst scenario is only 64% of the original. If the number of bit retransmissions is large, it will lead to a significant increase in processing delay.

[0033] The other is to first interleave and de-fill the encoded multi-bit parallel data, and then read it for rate matching; due to the "row-to-column" rule of rate matching, the order of writing and reading is different, which also means that the encoded multi-bit data needs to be stored in different addresses, so this processing method cannot be implemented using a single-port RAM. The rate matching includes one data stream and two check streams, with a maximum bit number of 6144*3=18432bit. Whether a single RAM is converted into a register group or a single RAM is split into multiple RAMs, it will bring a huge area improvement.

[0034] In view of the above problems, the present disclosure proposes a rate matching method, device, electronic device, chip and storage medium.

[0035] The rate matching method, device, electronic device, chip and storage medium of the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0036] Figure 1 A flow chart of a rate matching method provided in an embodiment of the present disclosure.

[0037] This embodiment is illustrated by taking the rate matching method as a rate matching device, and the rate matching device can be set in an electronic device, specifically, for example, in a terminal. It should be noted that the execution subject of the embodiment of the present disclosure can be, for example, a central processing unit (CPU) of an electronic device in hardware, and can be, for example, a related background service of the electronic device in software, and there is no limitation on this.

[0038] like Figure 1 As shown, the rate matching method may include the following steps:

[0039] Step 101: Obtain coded data transmitted by a physical uplink shared channel PUSCH.

[0040] As an example, a transport block (TB) in uplink shared channel (UL_SCH) data transmitted on a physical uplink shared channel (PUSCH) is obtained, and then a cyclic redundancy check (CRC), code block segmentation and encoding are performed on the TB to obtain code block coded data, and the code block coded data is used as coded data; wherein the code block coded data includes: a system bit stream, a first check bit stream and a second check bit stream.

[0041] As another example, a channel quality indicator (Channel Quality Indicator, CQI for short) is encoded to obtain code block encoded data, and the code block encoded data is used as the encoded data.

[0042] Step 102: In response to the coded data satisfying a set condition, bit padding is performed on the coded data based on a first padding bit to obtain padded coded data.

[0043] In order to reduce memory fragmentation and storage overhead, as a possible implementation method, when the coded data meets the set conditions, the first filling bit is used to perform bit filling on the coded data to obtain filled coded data.

[0044] As a possible implementation method, in response to the length of the system bit stream being a non-integer multiple of the standard storage length of a storage unit in a single-port random access memory, a first filling bit is used to fill the system bit stream to obtain a filled system bit stream; wherein the length of the filled system bit stream is an integer multiple of the standard storage length.

[0045] As another possible implementation, in response to the length of the first check bit stream being a non-integer multiple of the standard storage length, the first check bit stream is padded with a first padding bit to obtain a padded first check bit stream; wherein the length of the padded first check bit stream is an integer multiple of the standard storage length;

[0046] As another possible implementation, in response to the length of the second check bit stream being a non-integer multiple of the standard storage length, the second check bit stream is filled with the first filling bit to obtain a filled second check bit stream; wherein the length of the filled second check bit stream is an integer multiple of the standard storage length.

[0047] It should be noted that the above three possible implementation methods may be satisfied at the same time, or only one or two of them may be satisfied, and the present disclosure does not make any specific limitations.

[0048] In addition, it should be noted that the length of the system bit stream, the first check bit stream or the second check bit stream is equal to K+4 (where K is the length of the corresponding code block and 4 is the tail bit added by the encoding). Taking the standard storage length of the storage unit as 32 bits as an example, since the communication protocol stipulates that K is an integer multiple of 8, the first filling bit is used to fill the system bit stream, the first check bit stream or the second check bit stream to obtain a filled bit stream. The length of the filled bit stream is an integer multiple of the standard storage length, that is, K+4+first filling bit=32. The length of the first filling bit is one of 4, 12, 20 and 28.

[0049] Step 103, storing the padding coded data in a single-port random access memory.

[0050] In order to improve memory utilization efficiency and save storage area, as an example, padding coded data is stored in a RAM with only a single access port, wherein this single-port RAM allows data to be read and written through a unique port, and only one of the read or write operations can be performed at a time.

[0051] In order to avoid writing conflicts in a single-port random access memory, as a possible implementation, the system bit stream, the first check bit stream and the second check bit stream are written into the single-port RAM at different peaks.

[0052] As an example, the padded coded data includes: a padded system bit stream, a padded first check bit stream and a padded second check bit stream. The padded system bit stream, the padded first check bit stream and the padded second check bit stream are written into a single-port RAM in sequence.

[0053] For example, after CRC, the system bit stream can be stored in the single-port RAM, while the first check bit stream and the second check bit stream are stored in the single-port RAM after Turbo encoding, and finally the tail bits of the system bit stream after encoding are written. The three can be written at staggered times to prevent write conflicts in the single-port RAM.

[0054] Step 104, performing a set number of rate matching processes on the padding coded data in the single-port random access memory; wherein the data to be rate matched in any rate matching process does not include the first padding bit.

[0055] In order to avoid the problem of rate matching throughput reduction that may be caused by a large proportion of the first filling bit in the data to be rate matched, as an example, multiple rate matching processes are performed on the stored filling coded data, wherein the first filling bit is not included in the data to be rate matched in any rate matching process, that is, when the filling coded data is read from a single-port random access memory, the first filling bit is skipped and the data to be rate matched that does not include the first filling bit is used for rate matching.

[0056] In summary, when the coded data meets the set conditions, the first filling bit is used for bit filling to obtain the filled coded data, so that the filled coded data is an integer multiple of the standard storage length of the storage unit. Then, the filled coded data is stored in the single-port RAM, which reduces memory fragmentation and storage overhead, improves memory utilization efficiency and saves storage area. Finally, multiple rate matching processes are performed on the stored filled coded data, wherein the first filling bit is not included in the data to be rate matched in any rate matching process, effectively avoiding the problem of decreased rate matching throughput due to a large proportion of the first filling bit in the data to be rate matched, thereby improving the rate matching throughput and accuracy.

[0057] In order to clearly explain how to read the data to be rate matched in any rate matching process from the single-port random access memory in the above embodiment, the present disclosure proposes another rate matching method.

[0058] Figure 2 A flowchart of another rate matching method provided in an embodiment of the present disclosure.

[0059] like Figure 2 As shown, reading the data to be rate matched in any rate matching process from the single-port random access memory includes the following steps:

[0060] Step 201: obtain an interleaving matrix corresponding to padding coded data, and obtain a column transformation sequence associated with the interleaving matrix.

[0061] The elements in the column transformation sequence are used to indicate the data fetching position of each row in any rate matching process.

[0062] As an example, the padding coded data is written row by row into an interleaving matrix, where the number of columns of the interleaving matrix may be 32, and the interleaving matrix is ​​permuted in rows and columns to obtain a column transformation sequence associated with the interleaving matrix, wherein it should be noted that the column transformation sequences corresponding to the system bit stream and the first check bit stream may be the same or different, and the column transformation sequence corresponding to the first check bit stream and the column transformation sequence corresponding to the second check bit stream may be the same or different.

[0063] For example, Figure 3 As shown, Figure 3 The column transformation sequence corresponding to the interleaving matrix of the system bit stream in is the same as the column transformation sequence corresponding to the interleaving matrix of the first check bit stream, and the column transformation sequence corresponding to the interleaving matrix of the first check bit stream is different from the column transformation sequence corresponding to the interleaving matrix of the second check bit stream; wherein, it should be noted that, Figure 3 In the figure, only the column transformation sequence corresponding to the interleaving matrix of the system bit stream and the column transformation sequence corresponding to the interleaving matrix of the first check bit stream are the same, and the column transformation sequence corresponding to the interleaving matrix of the first check bit stream and the column transformation sequence corresponding to the interleaving matrix of the second check bit stream are different are used as examples to illustrate that in practice, the column transformation sequences corresponding to the system bit stream and the first check bit stream may be different, and the column transformation sequence corresponding to the interleaving matrix of the first check bit stream and the column transformation sequence corresponding to the interleaving matrix of the second check bit stream may also be the same.

[0064] Step 202: Determine a padding indication sequence that matches the column transformation sequence according to the number of first padding bits.

[0065] The filling indication sequence is used to indicate whether the filling coded data at each access position is the first filling bit.

[0066] It should be understood that, taking the standard storage length of the storage unit as 32 bits as an example, the length of the first padding bit is one of 4, 12, 20 and 28, such as Figure 4 As shown, according to any value of the first filling bit, it can be determined whether the filling coded data at each access position in the column transformation sequence is the first filling bit; wherein, Figure 4 In the figure, only the filling information of the value positions of the 1st to 8th elements in the column transformation sequence is taken as an example to illustrate. The filling information of the value positions of the 9th to 16th elements, the filling information of the value positions of the 17th to 24th elements, and the filling information of the value positions of the 25th to 32nd elements are the same as the filling information of the value positions of the 1st to 8th elements.

[0067] Step 203: acquiring the data to be rate matched in any rate matching process from the padded coded data according to the column transformation sequence and the padding indication sequence.

[0068] In order to avoid the problem of rate matching throughput decrease that may be caused by a large proportion of the first filling bits in the data to be rate matched, as an example, according to the column transformation sequence and the filling indication sequence, valid bits except the first filling bits are read from a single-port random access memory, and the read valid bits are used as the data to be rate matched.

[0069] In summary, the interleaving matrix corresponding to the padding coded data is obtained, and the column transformation sequence associated with the interleaving matrix is ​​obtained; wherein the elements in the column transformation sequence are used to indicate the data access position of each row in any rate matching process; according to the number of the first padding bits, the padding indication sequence matching the column transformation sequence is determined; wherein the padding indication sequence is used to indicate whether the padding coded data at each data access position is the first padding bit; according to the column transformation sequence and the padding indication sequence, the data to be rate matched in any rate matching process is obtained from the padding coded data, thereby, the column transformation sequence provides a flexible data access position indication for the rate matching process, and the padding indication sequence realizes the accurate distinction between the valid bit and the first padding bit for each data access position, and then, by combining the column transformation sequence and the padding indication sequence, the data to be rate matched in the current rate matching process and excluding the first padding bit can be accurately extracted from the padding coded data.

[0070] In order to clearly explain how to obtain the data to be rate matched in any rate matching process from the padding coded data according to the column transformation sequence and the padding indication sequence in the above embodiment, the present disclosure proposes another rate matching method.

[0071] Figure 5 A flowchart of another rate matching method provided in an embodiment of the present disclosure.

[0072] like Figure 5 As shown, according to the column transformation sequence and the padding indication sequence, obtaining the data to be rate matched in any rate matching process from the padding coded data includes the following steps:

[0073] Step 501, determining a first target storage address to be read in any rate matching process from a plurality of storage addresses of a single-port random access memory.

[0074] It should be noted that the storage method of the system bit stream in the single-port RAM is different from the storage method of the first check bit stream and the second check bit stream in the single-port RAM. Therefore, the method of obtaining the first target storage address of the system bit stream to be read and the method of obtaining the first target storage address of the first check bit stream and the second check bit stream to be read from the multiple storage addresses of the single-port RAM are different. Please see the description of the subsequent embodiments for details.

[0075] Step 502: Determine a first target row to be read and a data fetching position in the first target row from a first target storage address according to a column transformation sequence and a fill indication sequence.

[0076] It should be noted that since the elements in the column transformation sequence indicate the data access position of each row in any rate matching process, and the fill indication sequence indicates whether the fill coding data of each data access position is the first filling bit, therefore, according to the column transformation sequence and the fill indication sequence, the first target row to be read in any rate matching process and the data access position in the first target row can be accurately located from the first target storage address, wherein the fill coding data of the data access position in the first target row is not the first filling bit.

[0077] Step 503: Read the data to be rate matched in any rate matching process from the first target row according to the data fetching position in the first target row.

[0078] Furthermore, based on the data fetching position in the first target row, the data to be rate matched in any rate matching process can be accurately read from the first target row.

[0079] In summary, the first target storage address to be read in any rate matching process is determined from multiple storage addresses of a single-port random access memory; the first target row to be read and the data access position in the first target row are determined from the first target storage address according to the column transformation sequence and the fill indication sequence; according to the data access position in the first target row, the data to be rate matched in any rate matching process is read from the first target row. Therefore, by combining the column transformation sequence and the fill indication sequence, the data access position to be read in any rate matching process can be accurately determined from the first target storage address, and according to the value access position, the data to be rate matched in any rate matching process and excluding the first filling bit can be accurately obtained.

[0080] In order to clearly explain how to determine the first target storage address of the system bit stream to be read in any rate matching process from multiple storage addresses of the single-port random access memory in the above embodiment, the present disclosure proposes another rate matching method.

[0081] Figure 6 A flowchart of another rate matching method provided in an embodiment of the present disclosure.

[0082] like Figure 6 As shown, determining the first target storage address of the system bit stream to be read in any rate matching process from a plurality of storage addresses of the single-port random access memory includes the following steps:

[0083] Step 601: Determine a first candidate storage address to be read in any rate matching process from a plurality of storage addresses.

[0084] As an example, in response to any rate matching process being the first rate matching process, a redundant version number associated with the first rate matching process is obtained; based on the redundant version number associated with the first rate matching process, a first candidate storage address to be read for the first rate matching process is determined; in response to any rate matching process being a non-first rate matching process, the first candidate storage address to be read for this rate matching process is determined based on the storage addresses of the rows read in the previous rate matching process.

[0085] That is to say, for the first rate matching process, the starting position of the rate matching can be determined according to the redundant version number, that is, according to the redundant version number, the starting storage position to be read in the matching process, that is, the first candidate storage address, can be determined; for the non-first rate matching process, the first candidate storage address to be read in this rate matching process is determined according to the storage address of the rows that have been read in the previous rate matching process; for example, the storage address of the rows that have been read in the previous rate matching process is address 2, if there are unread rows in address 2, then the first candidate storage address to be read in this rate matching process is address 2; if there are no unread rows in address 2, then the first candidate storage address to be read in this rate matching process is address 3, address 3 is the next storage address of address 2, and address 3 and address 2 have the same bit stream data type stored.

[0086] Step 602, in response to the total number of unread rows in the first candidate storage address being less than the parallelism of any rate matching process, when there is a second candidate storage address among multiple storage addresses, obtain the sum of the total number of unread rows in the first candidate storage address and the second candidate storage address.

[0087] The second candidate storage address is the next storage address of the first candidate storage address, and the first candidate storage address and the second candidate storage address are used to store the system bit stream.

[0088] It should be noted that the parallelism of any rate matching process is the number of data bits processed in parallel. For example, if the parallelism is 8, the number of data bits processed in parallel by any rate matching process is 8, that is, 8 valid bits need to be obtained in any rate matching process.

[0089] As an example, determine whether the total number of unread rows in the first candidate storage address (for example, a cell of a single-port RAM can represent a row of 32-bit data) is less than the corresponding parallelism. If so, determine whether there is a next storage address of the first candidate storage among multiple storage addresses, that is, determine whether the first candidate storage address is the storage address of the last storage system bit stream; wherein the first candidate storage address and the second candidate storage address are both used to store the system bit stream.

[0090] It should be understood that if the second candidate storage address is the storage address of the last storage system bit stream, the total number of rows in the second candidate storage address may be less than or equal to the degree of parallelism (e.g., 8). When the total number of rows in the second candidate storage address is equal to the degree of parallelism, the sum of the total number of rows that have not been read in the first candidate storage address and the total number of rows in the second candidate storage address is greater than the degree of parallelism. When the total number of rows in the second candidate storage address is less than the degree of parallelism, the sum of the total number of rows that have not been read in the first candidate storage address and the total number of rows in the second candidate storage address may also be less than the degree of parallelism. Therefore, it is necessary to determine whether the sum of the total number of rows that have not been read in the first candidate storage address and the total number of rows in the second candidate storage address is greater than or equal to the degree of parallelism.

[0091] Step 603, when the sum of the total number of unread rows in the first candidate storage address and the second candidate storage address is greater than or equal to the parallelism, the first candidate storage address and the second candidate storage address are used as the first target storage address to be read in any rate matching process.

[0092] As a possible implementation method, when the sum of the total number of unread rows in the first candidate storage address and the second storage address is greater than or equal to the parallelism, the first candidate storage address and the second candidate storage address are used as the first target storage address to be read in any rate matching process.

[0093] As another possible implementation, in response to the sum of the total number of unread rows in the first candidate storage address and the second storage address being less than the degree of parallelism, and any rate matching process is not the last rate matching process, a third candidate storage address to be read by any rate matching process is obtained; wherein the third candidate storage address is the storage address of the first storage system bit stream; the first candidate storage address, the second candidate storage address and the third candidate storage address are used as the first target storage address to be read by any rate matching process.

[0094] That is to say, when the total number of rows in the second candidate storage address is less than the degree of parallelism, the sum of the total number of rows that have not been read in the first candidate storage address and the total number of rows in the second candidate storage address is also less than the degree of parallelism, which means that the second candidate storage address is the last storage address of the storage system bit stream. Therefore, when any rate matching process is not the last rate matching process, the storage address of the first storage system bit stream is obtained from multiple storage addresses, and the first candidate storage address, the second candidate storage address and the third candidate storage address are used as the first target storage address to be read in any rate matching process.

[0095] As another possible implementation, in response to the sum of the total number of unread rows in the first candidate storage address and the second storage address being less than the degree of parallelism, and any rate matching process is the last rate matching process, the first candidate storage address and the second candidate storage address are used as the first target storage addresses to be read in any rate matching process.

[0096] That is to say, when the total number of rows in the second candidate storage address is less than the degree of parallelism, the sum of the total number of rows that have not been read in the first candidate storage address and the total number of rows in the second candidate storage address is also less than the degree of parallelism, which means that the second candidate storage address is the last storage address of the storage system bit stream. Since any rate matching process is the last rate matching process, the corresponding data to be rate matched is obtained only from the unread rows in the first candidate storage address and the second candidate storage address. Therefore, the first candidate storage address and the second candidate storage address are used as the first target storage address to be read in any rate matching process.

[0097] As another possible implementation, in response to the total number of unread rows in the first candidate storage address being less than the degree of parallelism, and there being no second candidate storage address among the multiple storage addresses, when any rate matching process is not the last rate matching process, the first candidate storage address and the third candidate storage address are used as the first target storage address to be read in any rate matching process.

[0098] That is to say, when the first candidate storage address is the last storage address of the storage system bit stream, but the total number of rows that have not been read in the first candidate storage address is less than the degree of parallelism and any rate matching process is not the last rate matching process, the first candidate storage address and the storage address of the first storage system bit stream are used as the first target storage address to be read in any rate matching process.

[0099] As another possible implementation method, in response to the total number of unread rows in the first candidate storage address being less than the degree of parallelism, and there being no second candidate storage address among the multiple storage addresses, when any rate matching process is the last rate matching process, the first candidate storage address is used as the first target storage address to be read in any rate matching process.

[0100] That is to say, when the first candidate storage address is the last storage address of the storage system bit stream, but the total number of unread rows in the first candidate storage address is less than the parallelism and any rate matching process is the last rate matching process, the first candidate storage address will be used as the first target storage address to be read in any rate matching process.

[0101] It should be noted that the above possible implementation methods are parallel implementation methods, and when actually executing, you need to choose one to execute.

[0102] In summary, the first candidate storage address to be read in any rate matching process is determined from multiple storage addresses; in response to the total number of rows not read in the first candidate storage address being less than the parallelism of any rate matching process, when there is a second candidate storage address in multiple storage addresses, the sum of the total number of rows not read by the first candidate storage address and the second candidate storage address is obtained; when the sum of the total number of rows not read in the first candidate storage address and the second candidate storage address is greater than or equal to the parallelism, the first candidate storage address and the second candidate storage address are used as the first target storage address to be read in any rate matching process, thereby, the first target storage address to be read in any rate matching process can be accurately determined from multiple storage addresses.

[0103] In order to clearly explain how to determine the first target row to be read from the first target storage address storing the storage system bit stream according to the column transformation sequence and the fill indication sequence in the above embodiment, the present disclosure proposes another rate matching method.

[0104] Figure 7 A flowchart of another rate matching method provided in an embodiment of the present disclosure.

[0105] like Figure 7 As shown, according to the column transformation sequence and the fill indication sequence, determining the first target row to be read from the first target storage address of the storage system bit stream includes the following steps:

[0106] Step 701 : in response to the total number of unread rows in the first target storage address being greater than the degree of parallelism, determining a second target row matching the degree of parallelism from the unread rows in the first target storage address.

[0107] As an example, the total number of unread rows in the first target storage address is greater than the degree of parallelism, indicating that there are multiple first target storage addresses. According to the sequence of the first target storage addresses and the order of the storage units from front to back, the second target row matching the degree of parallelism is determined from the unread rows of the first target storage address. For example, the first target storage address includes address 1 and address 2, address 2 is the next storage address of address 1, address 1 includes 5 unread rows, and address 2 includes 8 unread rows. The 5 unread rows in address 1 and the first 3 unread rows in address 2 are used as the second target rows.

[0108] Step 702: Determine whether there is a third target row in the second target row according to the column transformation sequence and the fill indication sequence.

[0109] The third target row is the row whose number is the first filling bit in this rate matching process.

[0110] Furthermore, according to the column transformation sequence and the filling indication sequence, it is queried whether there is a first filling bit in each number taken in the second target row during the current rate matching process. When there is a first filling bit in each number taken in the second target row during the current rate matching process, it is determined that there is a third target row in the second target row; when there is no first filling bit in each number taken in the second target row during the current rate matching process, it is determined that there is no third target row in the second target row; wherein, the third target row is a row whose number taken in the current rate matching process is the first filling bit.

[0111] Step 703: when the third target row exists in the second target row, the next row of the second target row and the other rows of the second target row except the third target row are used as the first target row to be read in this rate matching process.

[0112] As an example, when there is a third target row in the second target row, that is, when there is a first filling bit in each number taken in the second target row during this rate matching process, the next row of the second target row and other rows of the second target row except the third target row are used as the first target row to be read in this rate matching process.

[0113] For example, Figure 8 As shown, the first target storage address includes the last storage address of the storage system bit stream, the second to last storage address of the storage system bit stream, and the storage address of the first storage system bit stream. Since the number of the first storage unit of the storage address of the first storage system bit stream in this rate matching process is the first filling bit, that is, the first filling bit exists in each number of the second target row in this rate matching process, then the next row of the second target row (that is, Figure 8 The row where number 7 is located in the figure), and then, the next row of the second target row and the other rows of the second target row except the third target row are used as the first target row to be read in this rate matching process, that is, the rows where numbers 0 to 7 are located in the figure are the first target rows to be read in this rate matching process.

[0114] As an example, in response to the total number of unread rows in the first target storage address being less than or equal to the parallelism, the unread rows in the first target storage address are used as first target rows to be read in any rate matching process.

[0115] For example, for the last rate matching process of the system bit stream, when the first target storage address includes the last storage address for storing the system bit stream and the second to last storage address for storing the system bit stream, and when the total number of rows that are not read in the first target storage address is less than or equal to the parallelism, the rows that are not read in the first target storage address are directly used as the first target rows to be read in any rate matching process.

[0116] For another example, for the first rate matching process of the system bit stream, the first target storage address is the storage address of the first storage system bit stream. When the total number of rows that have not been read in the first target storage address is equal to the degree of parallelism, the rows that have not been read in the first target storage address are directly used as the first target rows to be read in any rate matching process. For example, the storage address of the first storage system bit stream includes 8 rows, and the 8 rows in the first storage address are used as the first target rows to be read in this rate matching process. It should be noted that when the first storage unit in the storage address of the first storage system bit stream includes the first padding bit, valid bit data can be obtained from the first storage unit by traversing the corresponding column transformation sequence.

[0117] Step 704: When there is no third target row in the second target row, the second target row is used as the first target row to be read in any rate matching process.

[0118] As another example, when the third target row does not exist in the second target row, that is, when the first filling bit does not exist in each number taken in the second target row during this rate matching process, the second target row is directly used as the first target row to be read in any rate matching process.

[0119] For example, Fig. 9 As shown, there is no third target row in the rows where numbers 0 to 7 are located, and the rows where numbers 0 to 7 are located are directly used as the first target row to be read in any rate matching process.

[0120] In summary, in response to the total number of unread rows in the first target storage address being greater than the degree of parallelism, a second target row matching the degree of parallelism is determined from the unread rows in the first target storage address; based on the column transformation sequence and the fill indication sequence, it is determined whether there is a third target row in the second target row; in the case where there is a third target row in the second target row, the next row of the second target row and the other rows in the second target row except the third target row are used as the first target row to be read in this rate matching process; in the case where there is no third target row in the second target row, the second target row is used as the first target row to be read in any rate matching process, thereby accurately and flexibly determining the first target row to be read in any rate matching process from the first target storage address.

[0121] In order to clearly illustrate how to determine the first target storage address of the first check bit stream and the second check bit stream to be read in any rate matching process from multiple storage addresses of the single-port random access memory in the above embodiment, the present disclosure proposes another rate matching method.

[0122] Fig.10 A flowchart of another rate matching method provided in an embodiment of the present disclosure.

[0123] like Fig.10 As shown, determining the first target storage address of the first check bit stream and the second check bit stream to be read in any rate matching process from a plurality of storage addresses of the single-port random access memory includes the following steps:

[0124] Step 1001: Determine, from a plurality of storage addresses, a fourth candidate storage address to be read in any rate matching process.

[0125] The fourth candidate storage address includes a first candidate sub-storage address and a second candidate sub-storage address, the first candidate sub-storage address is used to store the first check bit stream, and the second candidate sub-storage address is used to store the second check bit stream.

[0126] As an example, in response to any rate matching process being the first rate matching process, a redundant version number associated with the first rate matching process is obtained; based on the redundant version number associated with the first rate matching process, a first candidate storage address to be read for the first rate matching process is determined; in response to any rate matching process being a non-first rate matching process, the first candidate storage address to be read for this rate matching process is determined based on the storage addresses of the rows read in the previous rate matching process.

[0127] That is to say, for the first rate matching process, the starting position of the rate matching can be determined according to the redundant version number, that is, the starting storage position of the data to be read in the rate matching process can be determined according to the redundant version number, that is, the fourth candidate storage address; for the non-first rate matching process, the fourth candidate storage address to be read in this rate matching process is determined according to the storage addresses of the rows read in the previous rate matching process.

[0128] It should be understood that, when the first check bit stream and the second check bit stream are stored in the single-port RAM, the first check bit stream and the second check bit stream are stored in the same storage address at the same time, for example, the bit width of the single-port RAM is 8, the 0th to 3rd storage units are used to store the first check bit stream, and the 4th to 7th storage units are used to store the second check bit stream. Therefore, the fourth candidate storage address includes the first candidate sub-storage address and the second candidate sub-storage address, the first candidate sub-storage address is used to store the first check bit stream, and the second candidate sub-storage address is used to store the second check bit stream.

[0129] To improve rate matching efficiency, as a possible implementation, it is determined whether the sum of the total number of unread rows in the first candidate sub-storage address and the total number of unread rows in the second candidate sub-storage address is equal to the parallelism.

[0130] Step 1002, in response to the sum of the total number of unread rows in the first candidate sub-storage address and the second candidate sub-storage address being equal to the parallelism, and the first filling bit does not exist at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, the fourth candidate storage address is used as the first target storage address to be read in any rate matching process.

[0131] To improve rate matching efficiency, as a possible implementation, it is determined whether the sum of the total number of unread rows in the first candidate sub-storage address and the total number of unread rows in the second candidate sub-storage address is equal to the parallelism.

[0132] As an example, when the sum of the number of unread rows in the first candidate sub-storage address and the second candidate sub-storage address is equal to the degree of parallelism, a fill indication sequence, a column transformation sequence corresponding to the first check bit stream, and a column transformation sequence corresponding to the second check bit stream are obtained, and then, in order to align the reading order of the first check bit stream and the second check bit stream, it is determined whether the first fill bit exists at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream, and the fill indication sequence.

[0133] For example, Fig.11As shown, based on the column transformation sequence corresponding to the first check bit stream, when the 3rd column of the first check bit stream is read (the value of the first filling bit is 4), according to the column transformation sequence corresponding to the second check bit stream, when the 4th column of the second check bit is read, the first check bit column will have the first filling bit, while the second check bit column will not have the first filling bit; and when the first check bit is read to the 31st column, the second check bit needs to read the 0th column, at this time, the second check bit column will have the first filling bit, while the first check bit column will not have the first filling bit; when the first check bit is read to the 1st column, the second check bit needs to read the 2nd column, at this time, the first check bit column will have the first filling bit, while the second check bit column will also have the first filling bit.

[0134] In order to align the reading order of the first check bit stream and the second check bit stream, as a possible implementation method, when the first filling bit does not exist at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, there is no need to delete the first filling bit read in any rate matching process of the fourth candidate storage address, and the fourth candidate storage address can be used as the first target storage address.

[0135] As another possible implementation, in response to the simultaneous presence of a first filling bit at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, when there is a fifth candidate storage address among multiple storage addresses, the total number of rows of the first check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is obtained; when the total number of rows of the first check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and any rate matching process is not the last rate matching process, the sixth candidate storage address is obtained; wherein the sixth candidate storage address is the first storage address for storing the first check bit stream and the second check bit stream; the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage address to be read in any rate matching process;.

[0136] That is to say, according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream and the filling bit sequence, it is determined that in any rate matching process, the first filling bit exists at the access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, such as, there is a first filling bit in the 0th row and 0th column of the first candidate sub-storage address, and there is a first filling bit in the 0th row and 1st column of the second candidate sub-storage address. Since the first filling bit exists at the access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, the first filling bit needs to be skipped during reading, and the number of valid bits is less than the degree of parallelism. Therefore, it can be determined whether the fourth candidate storage address is the last storage address for storing the first check bit stream and the second check bit stream.

[0137] If not, obtain the next storage address of the fourth candidate storage address, that is, the fifth candidate storage address, and then determine whether the total number of rows of the unread first check bit stream in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism. If not, it means that the total number of rows of the unread first check bit stream in the fifth candidate storage address is less than half of the parallelism; wherein, the fifth candidate storage address is the last storage address for storing the first check bit stream and the second check bit stream in the single-port RAM. When any rate matching process is not the last rate matching process, the first storage address for storing the first check bit stream and the second check bit stream can be obtained, that is, the sixth candidate storage address. Then, the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0138] As another possible implementation method, in response to the simultaneous presence of a first filling bit at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, when there is a fifth candidate storage address among multiple storage addresses, the total number of rows of the second check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is obtained; if the total number of rows of the second check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the degree of parallelism, and when any rate matching process is not the last rate matching process, the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage addresses to be read in any rate matching process.

[0139] That is to say, there is a first filling bit at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address. When there is a fifth candidate storage address among multiple storage addresses, it is determined whether the total number of rows of the unread second check bit streams in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and the total number of rows of the unread second check bit streams in the fifth candidate storage address is less than half of the parallelism. The fifth candidate storage address is the last storage address for storing the first check bit stream and the second check bit stream in the single-port RAM. When any rate matching process is not the last rate matching process, the first storage address for storing the first check bit stream and the second check bit stream can be obtained, that is, the sixth candidate storage address. Then, the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0140] As another possible implementation, when the total number of rows of the first check bit stream that have not been read in the fourth candidate storage address and the fifth candidate storage address is less than half of the parallelism, and any rate matching process is the last rate matching process, the fourth candidate storage address and the fifth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0141] As another possible implementation, when the total number of rows of the second check bit stream that have not been read in the fourth candidate storage address and the fifth candidate storage address is less than half of the parallelism, and any rate matching process is the last rate matching process, the fourth candidate storage address and the fifth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0142] As another possible implementation, the total number of rows of the unread second check bit stream is less than half of the parallelism, and any rate matching process is the last rate matching process, and the fourth candidate storage address and the fifth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0143] As another possible implementation, when the total number of rows of the first check bit stream that have not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and the total number of rows of the second check bit stream that have not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, the fourth candidate storage address and the fifth candidate storage address are used as the first target storage address to be read in any rate matching process.

[0144] As another possible implementation, in response to the absence of the fifth candidate storage address among the multiple storage addresses and when any rate matching process is the last rate matching process, the fourth candidate storage address is used as the first target storage address to be read in any rate matching process.

[0145] That is to say, when there is no fifth candidate storage address among multiple storage addresses, that is, the fourth candidate storage address is the last storage address for storing the first check bit stream and the second check bit stream in the single-port RAM, and when any rate matching process is the last rate matching process, the fourth candidate storage address is used as the first target storage address to be read in any rate matching process; when there is no fifth candidate storage address among multiple storage addresses, and when any rate matching process is not the last rate matching process, the fourth candidate storage address and the first storage address for storing the first check bit stream and the second check bit stream (sixth candidate storage address) are used as the first target storage address to be read in any rate matching process.

[0146] It should be noted that the above possible implementation methods are parallel implementation methods, and when actually executing, you need to choose one to execute.

[0147] In summary, the fourth candidate storage address to be read in any rate matching process is determined from multiple storage addresses; in response to the sum of the total number of rows that have not been read in the first candidate sub-storage address and the second candidate sub-storage address being equal to the parallelism, and the first filling bit does not exist at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, the fourth candidate storage address is used as the first target storage address to be read in any rate matching process, thereby, while ensuring that the reading order of the first check bit stream and the second check bit stream read in any rate matching process is aligned, the first target storage address to be read in any rate matching process is flexibly and accurately determined.

[0148] In order to clearly illustrate how to determine the first target row to be read from the first target storage address storing the first check bit stream and the second check bit stream according to the column transformation sequence and the fill indication sequence in the above embodiment, the present disclosure proposes another rate matching method.

[0149] Fig.12 A flowchart of another rate matching method provided in an embodiment of the present disclosure.

[0150] like Fig.12 As shown, according to the column transformation sequence and the fill indication sequence, determining the first target row to be read from the first target storage address storing the first check bit stream and the second check bit stream includes the following steps:

[0151] Step 1201, based on the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream, and the fill indication sequence, determine whether the first fill bit exists simultaneously at the data access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address.

[0152] The first target sub-storage address is used to store the first check bit stream, and the second target sub-storage address is used to store the second check bit stream.

[0153] In order to obtain valid bits that match the degree of parallelism, as an example, by traversing the column transformation sequence corresponding to the first check bit stream and the column transformation sequence corresponding to the second check bit stream, and querying the fill indication sequence, it is determined whether the first fill bit exists at the same time at the access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address. For example, the first target storage address includes address 1 and address 2, and it is determined whether the first fill bit exists at the same time at the access position of the same row of the first target sub-storage address and the second target sub-storage address in address 1.

[0154] Step 1202, when the first filling bit exists at the data access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, the first target row is determined according to the fourth target row in the first target sub-storage address and the second target sub-storage address, and the rows of subsequent first target storage addresses of the same first target storage address.

[0155] The fourth target row is a row whose number is not the first filling bit in this rate matching process.

[0156] Continuing with the example that the first target storage address includes address 1 and address 2, there is a first filling bit at the data access position of the same row of the first target sub-storage address and the second target sub-storage address in address 1. The rows of the first target sub-storage address and the second target sub-storage address in address 1 that do not include the first filling bit, as well as each row in address 2, are taken as the first target row.

[0157] Step 1203, when there are no first filling bits at the data access positions of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, each row of the first target storage address to be read by any rate matching process is used as the first target row to be read by any rate matching process.

[0158] As an example, if the first filling bit does not exist at the data access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, then the rows of the first target storage address to be read by any rate matching process are directly used as the first target rows to be read by any rate matching process.

[0159] In order to avoid the problem of decreased rate matching throughput that may be caused by a large proportion of the first filling bits in the data to be rate matched, as an example, the first filling bits are not simultaneously present at the data access positions of the same row of the first target sub-storage address and the second target sub-storage address, and according to the data access positions in the first target row to be read by any rate matching process, the intermediate data of any rate matching process is read from the first target row to be read by any rate matching process, and the first filling bits are deleted from the intermediate data to obtain the data to be rate matched by any rate matching process.

[0160] That is to say, when reading the first check bit stream and the second check bit stream from the single-port RAM, if the first filling bit does not exist at the data access position of the same row of the first target sub-storage address and the second target sub-storage address at the same time, the first filling bit is not skipped during reading, so the data of any rate matching process read may include the first filling bit. Therefore, when performing rate matching, the first filling bit is deleted from the data read from any rate matching process to obtain the data to be rate matched for any rate matching process. That is, the intermediate data of any rate matching process is read from the first target row to be read by any rate matching process, and the first filling bit is deleted to obtain the data to be rate matched for any rate matching process. In addition, the first filling bit read in any rate matching process can also be deleted when the rate matching is output, which is not specifically limited in the present disclosure.

[0161] In summary, by determining whether the first filling bit exists simultaneously at the access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream, and the filling indication sequence; in the case where the first filling bit exists simultaneously at the access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, the first target row is determined according to the fourth target row in the first target sub-storage address and the second target sub-storage address, and each row of the subsequent first target storage address of the same first target storage address; in the case where the first filling bit does not exist simultaneously at the access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, each row of the first target storage address to be read by any rate matching process is used as the first target row to be read by any rate matching process, thereby accurately and flexibly determining the first target row to be read by any rate matching process from the first target storage address to be read by any rate matching process while ensuring that the reading order of the first check bit stream and the second check bit stream are aligned.

[0162] In order to clearly explain how the above embodiment obtains the coded data transmitted by the physical uplink shared channel PUSCH, the present disclosure proposes another rate matching method.

[0163] Fig.13 A flowchart of another rate matching method provided in an embodiment of the present disclosure.

[0164] like Fig.13 As shown, the rate matching method includes the following steps:

[0165] Step 1301: obtain the TB transmitted by the PUSCH, and perform a cyclic redundancy check CRC on the TB to obtain a system bit stream containing a CRC code.

[0166] In order to improve the accuracy of data transmission, as an example, the TB in the UL_SCH data transmitted on the PUSCH is obtained, and the TB is subjected to CRC, so that a system bit stream containing a CRC code can be obtained.

[0167] Step 1302: In response to the length of the system bit stream including the CRC code being a non-integer multiple of the code block length, second padding bits are used to perform bit padding on the system bit stream including the CRC code to obtain a padded system bit stream.

[0168] In order to completely divide the system bit stream containing the CRC code into code blocks, as an example, when the length of the system bit stream containing the CRC code is a non-integer multiple of the code block length, the second filling bit (also called FILL_TB) is used to bit-fill the system bit stream containing the CRC code to obtain the filled system bit stream.

[0169] Step 1303, segmenting the padded system bit stream into code blocks to obtain multiple code blocks.

[0170] Furthermore, the padded system bit stream is segmented into code blocks to obtain multiple code blocks.

[0171] Step 1304: encode any code block to obtain a first check bit stream and a second check bit stream corresponding to any code block.

[0172] In order to improve the reliability and anti-interference capability of data transmission, as an example, Turbo encoding is performed on any code block to obtain a first check bit stream and a second check bit stream corresponding to any code block.

[0173] Step 1305: Use the system bit stream, the first check bit stream and the second check bit stream corresponding to any code block as coded data.

[0174] In order to improve the reliability of data transmission, as an example, the system bit stream, the first check bit stream and the second check bit stream corresponding to any code block are taken together as the encoded data.

[0175] Step 1306: In response to the coded data satisfying the set condition, bit padding is performed on the coded data based on the first padding bit to obtain padded coded data.

[0176] Step 1307, store the padding coded data into a single-port random access memory.

[0177] Step 1308, performing a set number of rate matching processes on the padding coded data in the single-port random access memory; wherein the data to be rate matched in any rate matching process does not include the first padding bit.

[0178] As a possible implementation method, taking the coded data as code block coded data as an example, since in the process of obtaining the code block coded data, it may be necessary to fill the second filling bit when performing code block segmentation on the system bit stream containing the CRC code so that the filled system bit stream can be completely code block segmented, therefore, in order to rate match the output of valid bit data, when the second filling bit is included in any code block coded data, rate matching is performed on the data to be rate matched to obtain an initial coded bit sequence of rate matching output; from the initial coded bit sequence, the second filling bit is deleted to obtain a target coded bit sequence.

[0179] In summary, the TB transmitted by the PUSCH is obtained, and a cyclic redundancy check CRC is performed on the TB to obtain a system bit stream including a CRC code; in response to the length of the system bit stream including the CRC code being a non-integer multiple of the code block length, the system bit stream including the CRC code is bit-filled with a second filling bit to obtain a filled system bit stream; the filled system bit stream is segmented into code blocks to obtain a plurality of code blocks; any code block is encoded to obtain a first check bit stream and a second check bit stream corresponding to any code block; the system bit stream, the first check bit stream and the second check bit stream corresponding to any code block are used as encoded data, thereby, by performing CRC, code block segmentation and encoding on the TB, the encoded data can be accurately obtained.

[0180] In any embodiment of the present disclosure, the rate matching method of the embodiment of the present disclosure may also be implemented based on the following steps:

[0181] 1. The Turbo-encoded data is stored in a single-port RAM (also called single-port RAM). The storage method is as follows: Fig.14 As shown, one cell represents a row of 32-bit data; the RAM bit width is 256 and the depth is 74, wherein the system bits are stored in RAM addresses 0-24, the first check bit stream or the second check bit stream is stored in RAM addresses 25-73, the first check bit stream occupies 0-127 bits of each storage address, and the second check bit stream occupies 128-255 bits of each storage address;

[0182] Among them, it should be noted that the bit width selection of the single-port RAM is determined based on the parallelism of the rate matching. The rate matching of this technical solution is 8 parallel. Since the rate matching follows the read and write rules listed in the process, it is necessary to read 8 rows of 1-bit data at a time (8 rows of system bits, or a combination of 4 rows of first check bits and 4 rows of second check bits). Therefore, the bit width selection of the single-port RAM is 32*8=256bit; in terms of the depth selection of the RAM, the number of rows of the system bit stream, the first check bit stream or the second check bit stream is at most 193, so the address depth required for the storage of the system bit stream is ceil(193*32 / 256)=25, the address depth required for the first check bit stream or the second check bit stream is ceil(2*193*32 / 256)=49, and the required total address depth is 25+49=74.

[0183] In addition, it should be noted that the system bit stream can be stored in the RAM after CRC, and the check bit stream is stored in the RAM after Turbo encoding, and finally the tail bits of the system bit stream encoding are written. The three can be written at staggered times to prevent RAM write conflicts.

[0184] 2. Pre-store RAM address 0 and address 25 (corresponding to address 0 of the system bit stream and address 0 of the first and second check bit streams) into two registers (ram_rdat_first);

[0185] 3. Calculate the row and column positions (row0-7, column0-7) of the 8 bits to be taken for this rate matching. When selecting the row and column positions of the 8 bits, skip the padding bits (FILL_32B) added in the rate matching, but do not skip the padding bits (FILL_TB) added during CB segmentation.

[0186] As an example, if 8 bits are located in the same column, the row position of the 8 bits is easy to get (rowN=row0+N). If an 8-parallel rate matching may span multiple columns, the number of columns spanned is related to the difference N between bitN and bit0 (bitN=bit0+N) and the number of valid rows spanning each column. If a column has a fill bit FILL_32B (the first fill bit), the number of valid rows of the column is the total number of rows minus 1. Because the fill bit is related to the number of valid rows of each column, it is necessary to know whether there is a fill bit FILL_32B in the spanned columns.

[0187] It should be noted that when the rows and columns of the first check bit stream and the second check bit stream are generated, the even bits (0, 2, 4, 6) are fixedly selected as the first check bit, and the odd bits (bit1, 3, 5, 7) are fixedly selected as the second check bit. FILL_32B also needs to be skipped when reading the bit.

[0188] 4. Take the address of row0 plus 1 as the RAM read address, read the RAM data (ram_rdat) at the corresponding address, beat ram_rdat to get ram_rdat_d1; that is, ram_rdat_d1 is the value of ram_rdat after one clock cycle delay, that is, data is stored in ram_rdat to get ram_rdat_d1;

[0189] How to select the RAM read address:

[0190] In general, 8 bits are distributed in two different addresses. Only when the 8 bits have data stored in the first address, the 8 bits will be distributed in three different addresses. Therefore, in the first step of rate matching, the data in the 0 address of the system bit stream, the first check bit stream and the second check bit stream need to be pre-stored (ram_rdat_first). The address of row0 plus 1 is used as the RAM read address, and the RAM data (ram_rdat) of the corresponding address is read, and ram_rdat is tapped to get ram_rdat_d1; the 8-bit data to be read must be located in ram_rdat_first, ram_rdat and ram_rdat_d1, and can be selected and read according to the row and column number corresponding to the bit.

[0191] The bit reading of the first and second check bits is similar to that of the system bits, and will not be described in detail here.

[0192] 5. According to the row and column positions of the 8 bits, take the corresponding bit from ram_rdat_first / ram_rdat / ram_rdat_d1;

[0193] Among them, it should be noted that at the junction of the system bit stream and the check bit stream, there may be a scenario where the system bits read are less than 8 bits. In this case, the 8-bit data read in the same cycle (i.e., a rate matching process) will not cross the boundary of the system bit stream and the check bit stream, and only valid system bit data or check bit data will be read. For example, if there are only 3 bits left in the system bit stream, only the 3 bits of data are read this time, and the remaining 5 bits are regarded as invalid bits and removed, and then spliced ​​with the check bits after reading. The reason why the system bit stream and the check bit stream are not required to be read in the same cycle here is, on the one hand, because the reading rules of the two are different (the first check bit stream and the second check bit stream are output alternately, and the system bit stream is output directly), and on the other hand, the frequency of crossing between the system bit stream and the check bit stream bits is low, and the impact on the overall delay is not obvious;

[0194] In addition, it should be noted that the column transformation rule of the second check bit is different from that of the first check bit, and some special processing is required in the specific implementation. Figure 4 As shown;

[0195] It can be found that when the first check bit stream reads 3 / 19 / 11 / 27, the second check bit stream reads columns 4 / 20 / 12 / 28. At this time, there will be a situation where the columns of the first check bit stream have padding bits (first padding bits), while the columns of the second check bit stream do not have padding bits (first padding bits). When the first check bit stream reads the 31st column, the second check bit stream needs to read the 0th column. At this time, there will be a situation where the columns of the second check bit stream have padding bits, while the columns of the first check bit stream do not have padding bits. Both scenarios will disrupt the reading order of the first and second check bits.

[0196] In order to prevent the order from being disrupted, for the above two scenarios, the padding bits are not skipped when acquiring data, so that the reading order of the first check bit stream and the second check bit stream is aligned. The first check bit stream with padding bits is used as an example to illustrate:

[0197] When the first check bit stream reads the FILL_32B-1 column, the padding bits are not skipped, so that the reading order of the second check bit can be aligned. The read bits are regarded as invalid bits and are removed during rate matching output.

[0198] 6. Determine whether the 8 bits taken out are valid bits, and remove invalid bits including FILL_TB;

[0199] After 8 bits of data are read from RAM, the validity of the 8 bits of data needs to be judged and invalid bits need to be removed. Invalid bits can be summarized into the following three types:

[0200] (1) The read bits are fill bits FILL_TB;

[0201] (2) The read bit is located at an invalid position at the junction of the systematic bit and the check bit;

[0202] (3) The read bits are the first and second check bits that need to be removed during special processing;

[0203] 7. Concatenate the valid bits and output 8 bits of valid data as the output of rate matching.

[0204] As an example, after adding 24-bit CRC to the transmission data, the length is 57. It is necessary to first add 7-bit FILL_TB to form a CB block with a length of 64. After adding 4-bit tail bits, it is necessary to add 28-bit padding bits FILL_32B to form 96 bits during rate matching. The data throughput is (57+4) / 96=63.5%;

[0205] As another example, after adding 24-bit CRC to the transmission data, the length is 41, and 7-bit FILL_TB needs to be added to form a CB block with a length of 48. After adding 4-bit tail bits, 12-bit padding bits FILL_32B need to be added during rate matching (the padding bits will be skipped during reading), and the data throughput is (41+4) / (41+4+7)=86.5%;

[0206] In order to intuitively show the throughput comparison between the comparison scheme in the related art and the present scheme, Table 1 is used to show the throughput comparison results between the comparison scheme and the present scheme when the TB+CRC length ranges from 40 to 100.

[0207] Table 1. Comparison of throughput between the comparison scheme and this scheme when the TB+CRC length ranges from 40 to 100

[0208]

[0209]

[0210] The beneficial effects brought by this solution include: compared with direct data access, this solution greatly improves the rate matching throughput, and the throughput in extreme scenarios increases from 63.5% to 86.5%; compared with the solution of first removing the padding bits to store the data and then reading it, the storage unit of this solution only needs to use a single-port RAM, which greatly optimizes the storage area.

[0211] In order to implement the above embodiment, the embodiment of the present disclosure also proposes a rate matching device.

[0212] Fig.15 A schematic diagram of the structure of a rate matching device provided in an embodiment of the present disclosure.

[0213] like Fig.15 As shown, the rate matching device 1500 includes: an acquisition module 1510 , a first filling module 1520 , a storage module 1530 , and a processing module 1540 .

[0214] Among them, the acquisition module 1510 is used to obtain the coded data transmitted by the physical uplink shared channel PUSCH; the first filling module 1520 is used to fill the coded data based on the first filling bit in response to the coded data meeting the set condition to obtain the filled coded data; the storage module 1530 is used to store the filled coded data in the single-port random access memory; the processing module 1540 is used to perform a set number of rate matching processes on the filled coded data in the single-port random access memory; wherein the first filling bit is not included in the data to be rate matched in any rate matching process.

[0215] As a possible implementation method of an embodiment of the present disclosure, any rate matching process includes: reading the data to be rate matched of any rate matching process from a single-port random access memory; wherein the data to be rate matched does not include the first filling bit; and performing rate matching on the data to be rate matched to obtain a target coded bit sequence obtained by any rate matching process.

[0216] As a possible implementation method of an embodiment of the present disclosure, the processing module 1540 is used to obtain an interleaving matrix corresponding to padding coded data, and obtain a column transformation sequence associated with the interleaving matrix; wherein the elements in the column transformation sequence are used to indicate the data access position of each row in any rate matching process; according to the number of first padding bits, a padding indication sequence matching the column transformation sequence is determined; wherein the padding indication sequence is used to indicate whether the padding coded data at each data access position is the first padding bit; according to the column transformation sequence and the padding indication sequence, the data to be rate matched in any rate matching process is obtained from the padding coded data.

[0217] As a possible implementation method of the embodiment of the present disclosure, the processing module 1540 is used to determine the first target storage address to be read in any rate matching process from multiple storage addresses of the single-port random access memory; determine the first target row to be read and the data access position in the first target row from the first target storage address according to the column transformation sequence and the fill indication sequence; and read the data to be rate matched in any rate matching process from the first target row according to the data access position in the first target row.

[0218] As a possible implementation method of the embodiment of the present disclosure, the encoded data includes multiple code block encoded data, and any code block encoded data includes: a system bit stream, a processing module 1540, which is used to determine a first candidate storage address to be read in any rate matching process from multiple storage addresses; in response to the total number of rows that have not been read in the first candidate storage address being less than the parallelism of any rate matching process, when there is a second candidate storage address in the multiple storage addresses, the sum of the total number of rows that have not been read by the first candidate storage address and the second candidate storage address is obtained; wherein the second candidate storage address is the next storage address of the first candidate storage address, and the first candidate storage address and the second candidate storage address are used to store the system bit stream; when the sum of the total number of rows that have not been read in the first candidate storage address and the second candidate storage address is greater than or equal to the parallelism, the first candidate storage address and the second candidate storage address are used as the first target storage address to be read in any rate matching process.

[0219] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to obtain a redundant version number associated with the first rate matching process in response to any rate matching process being a first rate matching process; and determine a first candidate storage address to be read for the first rate matching process based on the redundant version number associated with the first rate matching process.

[0220] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to determine the first candidate storage address to be read in this rate matching process in response to any rate matching process being a non-first rate matching process, based on the storage addresses of the rows read in the previous rate matching process.

[0221] As a possible implementation method of the embodiment of the present disclosure, the processing module 1540 is used to obtain a third candidate storage address to be read by any rate matching process in response to the sum of the total number of unread rows in the first candidate storage address and the second storage address being less than the parallelism, and any rate matching process is not the last rate matching process; wherein the third candidate storage address is the storage address of the first storage system bit stream; and the first candidate storage address, the second candidate storage address and the third candidate storage address are used as the first target storage address to be read by any rate matching process.

[0222] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to respond to the sum of the total number of unread rows in the first candidate storage address and the total number of unread rows in the second storage address being less than the degree of parallelism, and any rate matching process is the last rate matching process, using the first candidate storage address and the second candidate storage address as the first target storage addresses to be read in any rate matching process.

[0223] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to respond to the total number of unread rows in the first candidate storage address being less than the degree of parallelism, and there being no second candidate storage address among the multiple storage addresses, and when any rate matching process is not the last rate matching process, use the first candidate storage address and the third candidate storage address as the first target storage address to be read in any rate matching process.

[0224] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to respond to the total number of unread rows in the first candidate storage address being less than the degree of parallelism, and there being no second candidate storage address among the multiple storage addresses, and when any rate matching process is the last rate matching process, use the first candidate storage address as the first target storage address to be read in any rate matching process.

[0225] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to determine a second target row matching the degree of parallelism from the unread rows of the first target storage address in response to the total number of rows that have not been read in the first target storage address being greater than the degree of parallelism; determine whether there is a third target row in the second target row based on a column transformation sequence and a fill indication sequence; wherein the third target row is a row whose number is the first fill bit in this rate matching process; and when there is a third target row in the second target row, use the next row of the second target row and the other rows of the second target row except the third target row as the first target row to be read in this rate matching process.

[0226] As a possible implementation manner of the embodiment of the present disclosure, when there is no third target row in the second target row, the second target row is used as the first target row to be read in any rate matching process.

[0227] As a possible implementation method of an embodiment of the present disclosure, the processing module 1540 is used to, in response to the total number of unread rows in the first target storage address being less than or equal to the parallelism, use the unread rows in the first target storage address as the first target rows to be read in any rate matching process.

[0228] As a possible implementation method of an embodiment of the present disclosure, any code block encoding data includes: a first check bit stream and a second check bit stream, and a processing module 1540 is used to determine, from multiple storage addresses, a fourth candidate storage address to be read in any rate matching process; wherein the fourth candidate storage address includes a first candidate sub-storage address and a second candidate sub-storage address, the first candidate sub-storage address is used to store the first check bit stream, and the second candidate sub-storage address is used to store the second check bit stream; in response to the sum of the total number of rows that have not been read in the first candidate sub-storage address and the second candidate sub-storage address being equal to the parallelism, and the first filling bit does not exist at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, the fourth candidate storage address is used as the first target storage address to be read in any rate matching process.

[0229] As a possible implementation method of an embodiment of the present disclosure, a processing module 1540 is used to obtain the total number of rows of the first check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address in response to the simultaneous presence of a first filling bit at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, when there is a fifth candidate storage address in multiple storage addresses; wherein the fifth candidate storage address is the next storage address of the fourth candidate storage address, and the fifth candidate storage address is used to store the first check bit stream and the second check bit stream; when the total number of rows of the first check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and any rate matching process is not the last rate matching process, obtain the sixth candidate storage address; wherein the sixth candidate storage address is the first storage address for storing the first check bit stream and the second check bit stream; and use the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address as the first target storage address to be read in any rate matching process.

[0230] As a possible implementation method of an embodiment of the present disclosure, a processing module 1540 is used to obtain the total number of rows of unread second check bit streams in the fourth candidate storage address and the fifth candidate storage address in response to the simultaneous presence of a first filling bit at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, when there is a fifth candidate storage address among the multiple storage addresses; and when the total number of rows of unread second check bit streams in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the degree of parallelism and any rate matching process is not the last rate matching process, use the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address as the first target storage address to be read by any rate matching process.

[0231] As a possible implementation method of an embodiment of the present disclosure, the processing module 1540 is used to use the fourth candidate storage address and the fifth candidate storage address as the first target storage address to be read in any rate matching process when any of the following items is met: the total number of rows of the unread first check bit stream is less than half of the parallelism, and any rate matching process is the last rate matching process; the total number of rows of the unread second check bit stream is less than half of the parallelism, and any rate matching process is the last rate matching process; the total number of rows of the unread first check bit stream is greater than or equal to half of the parallelism, and the total number of rows of the unread second check bit stream is greater than or equal to half of the parallelism.

[0232] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to, in response to the absence of the fifth candidate storage address among multiple storage addresses, use the fourth candidate storage address as the first target storage address to be read in any rate matching process when any rate matching process is the last rate matching process.

[0233] As a possible implementation method of an embodiment of the present disclosure, a processing module 1540 is used to determine whether a first filling bit exists simultaneously at the access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address according to a column transformation sequence corresponding to the first check bit stream, a column transformation sequence corresponding to the second check bit stream, and a filling indication sequence; wherein the first target sub-storage address is used to store the first check bit stream, and the second target sub-storage address is used to store the second check bit stream; in the case where the first filling bit exists simultaneously at the access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, the first target row is determined according to a fourth target row in the first target sub-storage address and the second target sub-storage address, and each row of subsequent first target storage addresses of the same first target storage address; wherein the fourth target row is a row whose data access in this rate matching process is not the first filling bit.

[0234] As a possible implementation manner of the embodiment of the present disclosure, the processing module 1540 is used to use each row of the first target storage address to be read in any rate matching process as the first target row to be read in any rate matching process.

[0235] As a possible implementation method of an embodiment of the present disclosure, processing module 1540 is used to respond to the fact that the first filling bit does not exist at the data access position of the same row of the first target sub-storage address and the second target sub-storage address at the same time, and read the intermediate data of any rate matching process from the first target row to be read by any rate matching process according to the data access position in the first target row to be read by any rate matching process; delete the first filling bit from the intermediate data to obtain the data to be rate matched by any rate matching process.

[0236] As a possible implementation method of the embodiment of the present disclosure, the acquisition module 1510 is used to obtain the TB transmitted by the PUSCH, and perform a cyclic redundancy check CRC on the TB to obtain a system bit stream containing the CRC code; in response to the length of the system bit stream containing the CRC code being a non-integer multiple of the code block length, the system bit stream containing the CRC code is bit-filled with a second filling bit to obtain a filled system bit stream; the filled system bit stream is divided into code blocks to obtain multiple code blocks; any code block is encoded to obtain a first check bit stream and a second check bit stream corresponding to any code block; the system bit stream, the first check bit stream and the second check bit stream corresponding to any code block are used as encoded data.

[0237] As a possible implementation of an embodiment of the present disclosure, a first filling module 1520 is used to, in response to the length of a system bit stream being a non-integer multiple of a standard storage length of a storage unit in a single-port random access memory, use the first filling bit to fill the system bit stream to obtain a filled system bit stream; wherein the length of the filled system bit stream is an integer multiple of the standard storage length; and / or, in response to the length of a first check bit stream being a non-integer multiple of the standard storage length, use the first filling bit to fill the first check bit stream to obtain a filled first check bit stream; wherein the length of the filled first check bit stream is an integer multiple of the standard storage length; and / or, in response to the length of a second check bit stream being a non-integer multiple of the standard storage length, use the first filling bit to fill the second check bit stream to obtain a filled second check bit stream; wherein the length of the filled second check bit stream is an integer multiple of the standard storage length.

[0238] As a possible implementation of the embodiment of the present disclosure, the storage module 1530 is used to write the padded system bit stream, the padded first check bit stream and the padded second check bit stream into the single-port random access memory in sequence.

[0239] As a possible implementation method of an embodiment of the present disclosure, the processing module 1540 is used to perform rate matching on the rate-matched data in response to the second filling bit included in the encoded data to obtain an initial encoded bit sequence of rate matching output; and delete the second filling bit from the initial encoded bit sequence to obtain a target encoded bit sequence.

[0240] The rate matching device of the disclosed embodiment obtains the padded coded data by performing bit padding with the first padding bit when the coded data meets the set conditions, thereby realizing that the padded coded data is an integer multiple of the storage unit, and then storing the padded coded data in a single-port RAM, thereby reducing memory fragmentation and storage overhead, improving memory utilization efficiency and saving storage area. Finally, multiple rate matching processes are performed on the stored padded coded data, wherein the first padding bit is not included in the data to be rate matched in any rate matching process, effectively avoiding the problem of decreased rate matching throughput that may be caused when the proportion of the first padding bit in the data to be rate matched is large, thereby improving the rate matching throughput and accuracy.

[0241] In order to implement the above-mentioned embodiments, the present disclosure also proposes an electronic device, comprising a processor and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the rate matching method as described in the above-mentioned method embodiments.

[0242] In order to implement the above embodiments, the present disclosure further proposes a chip, wherein the chip includes a processing circuit, and the processing circuit is configured to execute the rate matching method as described in the above method embodiments.

[0243] In order to implement the above embodiment, the present disclosure further proposes a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the rate matching method described in the above method embodiment.

[0244] In order to implement the above embodiments, the present disclosure further proposes a computer program product, on which a computer program is stored. When the computer program is executed by a processor, the rate matching method as described in the above method embodiments is implemented.

[0245] Fig.16 The electronic device 1600 is a block diagram of an electronic device provided by an embodiment of the present disclosure. For example, the electronic device 1600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0246] Reference Fig.16 , the electronic device 1600 may include one or more of the following components: a processing component 1602 , a memory 1604 , a power component 1606 , a multimedia component 1608 , an audio component 1610 , an input / output (I / O) interface 1612 , a sensor component 1614 , and a communication component 1616 .

[0247] The processing component 1602 generally controls the overall operation of the electronic device 1600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 1602 may include one or more processors 1620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 1602 may include one or more modules to facilitate the interaction between the processing component 1602 and other components. For example, the processing component 1602 may include a multimedia module to facilitate the interaction between the multimedia component 1608 and the processing component 1602.

[0248] The memory 1604 is configured to store various types of data to support operations on the electronic device 1600. Examples of such data include instructions for any application or method operating on the electronic device 1600, contact data, phone book data, messages, pictures, videos, etc. The memory 1604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0249] The power component 1606 provides power to the various components of the electronic device 1600. The power component 1606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 1600.

[0250] The multimedia component 1608 includes a screen that provides an output interface between the electronic device 1600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 1608 includes a front camera and / or a rear camera. When the electronic device 1600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and the rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0251] The audio component 1610 is configured to output and / or input audio signals. For example, the audio component 1610 includes a microphone (MIC), and when the electronic device 1600 is in an operation mode, such as a call mode, a recording mode, and a speech recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 1604 or sent via the communication component 1616. In some embodiments, the audio component 1610 also includes a speaker for outputting audio signals.

[0252] I / O interface 1612 provides an interface between processing component 1602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0253] The sensor assembly 1614 includes one or more sensors for providing various aspects of status assessment for the electronic device 1600. For example, the sensor assembly 1614 can detect the open / closed state of the electronic device 1600, the relative positioning of components, such as the display and keypad of the electronic device 1600, and the sensor assembly 1614 can also detect the position change of the electronic device 1600 or a component of the electronic device 1600, the presence or absence of user contact with the electronic device 1600, the orientation or acceleration / deceleration of the electronic device 1600, and the temperature change of the electronic device 1600. The sensor assembly 1614 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 1614 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1614 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0254] The communication component 1616 is configured to facilitate wired or wireless communication between the electronic device 1600 and other devices. The electronic device 1600 can access a wireless network based on a communication standard, such as WiFi, 4G or 5G, or a combination thereof. In an exemplary embodiment, the communication component 1616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 1616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0255] In an exemplary embodiment, the electronic device 1600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0256] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1604 including instructions, and the instructions can be executed by a processor 1620 of the electronic device 1600 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0257] Fig.17 is a schematic diagram of the structure of the chip proposed in the embodiment of the present disclosure. Fig.17 The structure of the chip 1700 is shown, but is not limited to this.

[0258] The chip 1700 includes a processing circuit 1701 , and the processing circuit 1701 is configured to execute any of the above methods.

[0259] In some embodiments, the chip 1700 further includes one or more interface circuits 1702. Optionally, the interface circuit 1702 is connected to the memory 1703. The interface circuit 1702 can be used to receive signals from the memory 1703 or other devices, and the interface circuit 1702 can be used to send signals to the memory 1703 or other devices. For example, the interface circuit 1702 can read instructions stored in the memory 1703 and send the instructions to the processing circuit 1701.

[0260] In some embodiments, the interface circuit 1702 performs at least one of the communication steps such as sending and / or receiving in the above method, and the processing circuit 1701 performs other steps.

[0261] In some embodiments, terms such as interface circuit, interface, transceiver pin, and transceiver may be used interchangeably.

[0262] In some embodiments, the chip 1700 further includes one or more memories 1703 for storing instructions. Alternatively, all or part of the memory 1703 may be outside the chip 1700.

[0263] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0264] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0265] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present disclosure belong.

[0266] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0267] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0268] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0269] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0270] The storage medium mentioned above may be a read-only memory, a disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present disclosure. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure.

Claims

1. A rate matching method, characterized in that: include: Obtaining coded data transmitted by a physical uplink shared channel PUSCH; In response to the coded data satisfying a set condition, performing bit padding on the coded data based on a first padding bit to obtain padded coded data; Storing the padding coded data in the single-port random access memory; A rate matching process is performed a set number of times on the padding coded data in the single-port random access memory; wherein the data to be rate matched in any rate matching process does not include the first padding bit.

2. The method according to claim 1, characterized in that Any rate matching process includes: Reading the data to be rate matched of any rate matching process from the single-port random access memory; wherein the data to be rate matched does not include the first padding bit; Rate matching is performed on the data to be rate matched to obtain a target coded bit sequence obtained by any rate matching process.

3. The method according to claim 2, characterized in that The step of reading the data to be rate matched in any rate matching process from the single-port random access memory comprises: Obtaining an interleaving matrix corresponding to the padding coded data, and obtaining a column transformation sequence associated with the interleaving matrix; wherein the elements in the column transformation sequence are used to indicate the data acquisition position of each row in any rate matching process; Determine, according to the number of the first padding bits, a padding indication sequence matching the column transformation sequence; wherein the padding indication sequence is used to indicate whether the padding coded data at each of the access positions is the first padding bit; According to the column transformation sequence and the padding indication sequence, the data to be rate matched in any rate matching process is obtained from the padding coded data.

4. The method according to claim 3, characterized in that The obtaining, according to the column transformation sequence and the padding indication sequence, the data to be rate matched of any rate matching process from the padding coded data comprises: Determine a first target storage address to be read in any rate matching process from a plurality of storage addresses of the single-port random access memory; Determine a first target row to be read and a data fetching position in the first target row from the first target storage address according to the column transformation sequence and the fill indication sequence; The data to be rate matched in any rate matching process is read from the first target row according to the data fetching position in the first target row.

5. The method according to claim 4, characterized in that The coded data includes a plurality of code block coded data, any code block coded data includes: a system bit stream, and determining a first target storage address to be read in any rate matching process from a plurality of storage addresses of the single-port random access memory includes: Determining, from the plurality of storage addresses, a first candidate storage address to be read by any rate matching process; In response to the total number of rows that have not been read in the first candidate storage address being less than the parallelism of any rate matching process, when there is a second candidate storage address in the multiple storage addresses, obtaining the sum of the total number of rows that have not been read by the first candidate storage address and the second candidate storage address; wherein the second candidate storage address is the next storage address of the first candidate storage address, and the first candidate storage address and the second candidate storage address are used to store the system bitstream; When the sum of the total number of unread rows in the first candidate storage address and the second candidate storage address is greater than or equal to the degree of parallelism, the first candidate storage address and the second candidate storage address are used as the first target storage address to be read in any rate matching process.

6. The method according to claim 5, characterized in that The step of determining, from the plurality of storage addresses, a first candidate storage address to be read in any rate matching process comprises: In response to any of the rate matching processes being a first rate matching process, obtaining a redundancy version number associated with the first rate matching process; A first candidate storage address to be read in the first rate matching process is determined according to the redundancy version number associated with the first rate matching process.

7. The method according to claim 5, characterized in that The step of determining, from the plurality of storage addresses, a first candidate storage address to be read in any rate matching process comprises: In response to any rate matching process being a non-first rate matching process, a first candidate storage address to be read in this rate matching process is determined according to the storage addresses of the rows read in the previous rate matching process.

8. The method according to claim 5, characterized in that The method further comprises: In response to the sum of the total number of unread rows in the first candidate storage address and the second storage address being less than the parallelism, and the any rate matching process is not the last rate matching process, obtaining a third candidate storage address to be read by the any rate matching process; wherein the third candidate storage address is the first storage address storing the system bitstream; The first candidate storage address, the second candidate storage address and the third candidate storage address are used as the first target storage address to be read in any rate matching process.

9. The method according to claim 5, characterized in that The method further comprises: In response to the sum of the total number of unread rows in the first candidate storage address and the second storage address being less than the degree of parallelism, and any rate matching process is the last rate matching process, the first candidate storage address and the second candidate storage address are used as the first target storage addresses to be read in any rate matching process.

10. The method according to claim 8, characterized in that The method further comprises: In response to the total number of unread rows in the first candidate storage address being less than the degree of parallelism, and the second candidate storage address does not exist among the multiple storage addresses, when any rate matching process is not the last rate matching process, the first candidate storage address and the third candidate storage address are used as the first target storage address to be read in any rate matching process.

11. The method according to claim 8, characterized in that The method further comprises: In response to the total number of unread rows in the first candidate storage address being less than the degree of parallelism, and the second candidate storage address does not exist among the multiple storage addresses, when any rate matching process is the last rate matching process, the first candidate storage address is used as the first target storage address to be read in any rate matching process.

12. The method according to claim 4, characterized in that The step of determining a first target row to be read from the first target storage address according to the column transformation sequence and the fill indication sequence comprises: In response to the total number of unread rows in the first target storage address being greater than the parallelism, determining a second target row matching the parallelism from the unread rows of the first target storage address; Determine whether there is a third target row in the second target row according to the column transformation sequence and the filling indication sequence; wherein the third target row is a row whose number is the first filling bit in the current rate matching process; In the case that the third target row exists in the second target rows, the next row of the second target row and other rows of the second target rows except the third target row are used as the first target row to be read in the current rate matching process.

13. The method according to claim 12, characterized in that The method further comprises: In a case where the third target row does not exist in the second target rows, the second target row is used as the first target row to be read in any rate matching process.

14. The method according to claim 4, characterized in that The step of determining a first target row to be read from the first target storage address according to the column transformation sequence and the fill indication sequence comprises: In response to the total number of unread rows in the first target storage address being less than or equal to the degree of parallelism, the unread rows in the first target storage address are used as first target rows to be read in any rate matching process.

15. The method according to claim 5, characterized in that Any code block encoding data includes: a first check bit stream and a second check bit stream, Determining a first target storage address to be read in any rate matching process from a plurality of storage addresses of the single-port random access memory comprises: Determine, from the multiple storage addresses, a fourth candidate storage address to be read by any rate matching process; wherein the fourth candidate storage address includes a first candidate sub-storage address and a second candidate sub-storage address, the first candidate sub-storage address is used to store the first check bit stream, and the second candidate sub-storage address is used to store the second check bit stream; In response to the sum of the total number of unread rows in the first candidate sub-storage address and the second candidate sub-storage address being equal to the degree of parallelism, and the first filling bit does not exist at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, the fourth candidate storage address is used as the first target storage address to be read in any rate matching process.

16. The method according to claim 15, characterized in that The method further comprises: In response to the simultaneous presence of the first filling bit at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address, and in the case where there is a fifth candidate storage address among the multiple storage addresses, obtaining the total number of rows of the first check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address; wherein the fifth candidate storage address is the next storage address of the fourth candidate storage address, and the fifth candidate storage address is used to store the first check bit stream and the second check bit stream; When the total number of rows of the first check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism, and any rate matching process is not the last rate matching process, a sixth candidate storage address is obtained; wherein the sixth candidate storage address is the first storage address storing the first check bit stream and the second check bit stream; The fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage address to be read in any rate matching process.

17. The method according to claim 16, characterized in that The method further comprises: In response to the first padding bit being present at the data access position of the same row of the first candidate sub-storage address and the second candidate sub-storage address at the same time, and in the case that the fifth candidate storage address is present in the plurality of storage addresses, obtaining the total number of rows of the unread second check bit streams in the fourth candidate storage address and the fifth candidate storage address; When the total number of rows of the second check bit stream that has not been read in the fourth candidate storage address and the fifth candidate storage address is greater than or equal to half of the parallelism and any rate matching process is not the last rate matching process, the fourth candidate storage address, the fifth candidate storage address and the sixth candidate storage address are used as the first target storage address to be read by any rate matching process.

18. The method according to claim 16, characterized in that The method further comprises: In the case where any of the following conditions is met, the fourth candidate storage address and the fifth candidate storage address are used as the first target storage address to be read in any rate matching process: The total number of rows of the unread first check bit stream is less than half of the parallelism, and any rate matching process is the last rate matching process; The total number of rows of the unread second check bit stream is less than half of the parallelism, and any rate matching process is the last rate matching process; The total number of rows of the unread first parity bit stream is greater than or equal to half of the parallelism, and the total number of rows of the unread second parity bit stream is greater than or equal to half of the parallelism.

19. The method according to claim 16, characterized in that The method further comprises: In response to the fifth candidate storage address not existing in the multiple storage addresses, when any rate matching process is the last rate matching process, the fourth candidate storage address is used as the first target storage address to be read in any rate matching process.

20. The method according to claim 15, characterized in that The step of determining a first target row to be read from the first target storage address according to the column transformation sequence and the fill indication sequence comprises: Determine whether the first filling bit exists at the same access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address according to the column transformation sequence corresponding to the first check bit stream, the column transformation sequence corresponding to the second check bit stream, and the filling indication sequence; wherein the first target sub-storage address is used to store the first check bit stream, and the second target sub-storage address is used to store the second check bit stream; In the case where the first filling bit exists simultaneously at the data access position of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, the first target row is determined according to the fourth target row in the first target sub-storage address and the second target sub-storage address, and each row of subsequent first target storage addresses of the same first target storage address; wherein the fourth target row is a row whose data access is not the first filling bit in this rate matching process.

21. The method according to claim 20, characterized in that The method further comprises: When the first filling bit does not exist simultaneously at the data access positions of the same row of the first target sub-storage address and the second target sub-storage address in the same first target storage address, each row of the first target storage address to be read by any rate matching process is used as the first target row to be read by any rate matching process.

22. The method according to claim 20, characterized in that The acquiring, according to the data acquisition position in the first target row, the to-be-rate-matched data of any rate matching process from the first target row includes: In response to the first padding bit not being simultaneously present at the data access positions of the same row of the first target sub-storage address and the second target sub-storage address, reading the intermediate data of any rate matching process from the first target row to be read by any rate matching process according to the data access position in the first target row to be read by any rate matching process; The first filling bit is deleted from the intermediate data to obtain the data to be rate matched in any rate matching process.

23. The method according to claim 1, characterized in that The obtaining of coded data transmitted by a physical uplink shared channel PUSCH includes: Acquire a TB transmitted by a PUSCH, and perform a cyclic redundancy check CRC on the TB to obtain a system bit stream including a CRC code; In response to the length of the system bit stream including the CRC code being a non-integer multiple of the code block length, bit-filling the system bit stream including the CRC code with second filling bits to obtain a filled system bit stream; Performing code block segmentation on the padded system bit stream to obtain a plurality of code blocks; Encoding any code block to obtain a first check bit stream and a second check bit stream corresponding to the any code block; The system bit stream, the first check bit stream and the second check bit stream corresponding to any one of the code blocks are used as the encoded data.

24. The method according to claim 23, characterized in that In response to the coded data satisfying a set condition, bit padding the coded data based on a first padding bit to obtain padded coded data includes: In response to the length of the system bit stream being a non-integer multiple of a standard storage length of a storage unit in the single-port random access memory, the system bit stream is padded with the first padding bit to obtain a padded system bit stream; wherein the length of the padded system bit stream is an integer multiple of the standard storage length; and / or, In response to the length of the first check bit stream being a non-integer multiple of the standard storage length, the first check bit stream is padded with the first padding bit to obtain a padded first check bit stream; wherein the length of the padded first check bit stream is an integer multiple of the standard storage length; and / or, In response to the length of the second check bit stream being a non-integer multiple of the standard storage length, the first filling bit is used to fill the second check bit stream to obtain a filled second check bit stream; wherein the length of the filled second check bit stream is an integer multiple of the standard storage length.

25. The method according to claim 24, characterized in that The storing the padding coded data into the single-port random access memory comprises: The padded system bit stream, the padded first check bit stream and the padded second check bit stream are sequentially written into the single-port random access memory.

26. The method according to claim 2, characterized in that The performing rate matching on the data to be rate matched to obtain a target coded bit sequence obtained by any rate matching process includes: In response to the coded data including the second padding bit, performing rate matching on the data to be rate matched to obtain an initial coded bit sequence output by the rate matching; The second filling bits are deleted from the initial coded bit sequence to obtain the target coded bit sequence.

27. A rate matching device, characterized in that: include: An acquisition module, used to acquire coded data transmitted by a physical uplink shared channel PUSCH; A first filling module, configured to perform bit filling on the coded data based on a first filling bit in response to the coded data satisfying a set condition, so as to obtain filled coded data; A storage module, used for storing the padding coded data in the single-port random access memory; A processing module is used to perform a set number of rate matching processes on the padding coded data in the single-port random access memory; wherein the data to be rate matched in any rate matching process does not include the first padding bit.

28. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 26.

29. A chip, characterized in that: The chip comprises a processing circuit configured to perform the method of any one of claims 1-26.

30. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 26 when executed by a processor.

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