Naked eye 3D image processing drive circuit based on FPGA and algorithm thereof

Abstract

The invention provides a naked eye 3D image processing drive circuit based on an FPGA and an algorithm thereof. The driving circuit comprises an FPGA (Field Programmable Gate Array) data processing module, an SD (Secure Digital) card image storage module, a DDR2 SDRAM (Synchronous Dynamic Random Access Memory) cache module and a naked eye 3D display screen module. Wherein the SD card image storage module is used for storing a 3D view in a left-right format; the SD card image storage module is connected with the FPGA data processing module, and the FPGA data processing module obtains an RGB view in a three-dimensional view; the DDR2 SDRAM cache module is connected with the FPGA data processing module and is used for caching a three-dimensional pair RGB view; the FPGA data processing module reads the cached three-dimensional RGB view data and divides the RGB view data to obtain a left-eye view and a right-eye view; and the naked-eye 3D display screen module is connected with the FPGA data processing module and is used for naked-eye 3D display.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits and image processing, and in particular relates to a naked-eye 3D image processing driving circuit based on FPGA and an algorithm thereof. Background Art

[0002] Naked-eye 3D display technology, which does not require viewers to use auxiliary equipment such as 3D glasses, meets people's ultimate demand for 3D display technology. This technology has become a key image display technology for virtual reality and augmented reality, and has been widely used in the fields of video and image display, with huge market potential.

[0003] At present, although the problems of naked-eye 3D optical mechanism and effect evaluation have been solved, the logical processing method of 3D video images still needs to be further studied. Unlike two-dimensional display technology, naked-eye 3D display requires special processing of video image data. Among them, pixel re-matching is the key technology for industrial application. However, there is no mature MCU or graphics chip on the market that can meet the image processing requirements of naked-eye 3D, which limits the application field of naked-eye 3D technology to a certain extent. Summary of the invention

[0004] The present invention is made to solve the above-mentioned problem, and its purpose is to provide a naked-eye 3D image processing driving circuit and its algorithm based on FPGA.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: The present invention provides a naked eye 3D television pixel configuration system, characterized in that it includes: an FPGA data processing module, an SD card image storage module, a DDR2 SDRAM cache module, a naked eye 3D display screen module and an auxiliary module, wherein the naked eye 3D display screen module, wherein the SD card image storage module is used to store a stereoscopic 3D view in a left-right format, and it is connected to the FPGA data processing module so that the FPGA can obtain the RGB view in the stereoscopic 3D view; the DDR2 SDRAM cache module here mainly plays a role of caching, and it is connected to the FPGA data processing module, and is used to temporarily store the stereoscopic RGB view data read from the SD card. Then, the FPGA data processing module reads these cached data and performs segmentation to finally obtain the left eye view and the right eye view; the naked eye 3D display screen module is connected to the FPGA data processing module, and after the processed left eye view and the right eye view are pixel reconfigured, they are output to the naked eye 3D display screen according to the display drive timing for display. In addition, this circuit also includes some other auxiliary modules. For example, the clock generation module clk_gen provides working clocks for each sub-functional module, external SD card and DDR2 SDRAM; the image data read control module data_rd_ctrl controls the SD card read-write controller to read the data of the image to be displayed in the SD card. The SD card read-write controller sd_ctrl is responsible for reading the image data to be displayed in the SD card.

[0006] The FPGA-based naked-eye 3D image processing driving circuit provided by the present invention also has the following features: wherein the FPGA data processing module includes: a clock and reset module, an SD card operation module, a FIFO control module, a DDR2 SDRAM controller module and a display driver module, wherein the clock and reset module is responsible for controlling the operating clock and reset signal of the entire system, and providing stable working clock and reset signal for all other modules; the SD card operation module is responsible for performing various operations on the SD card image storage module, including reading image data, etc. The DDR2 SDRAM controller module is communicated with the FIFO control module, and its main function is to write the stereo pair RGB view into the DDR2 SDRAM cache module, and generate the state of the left eye view and the right eye view of the stereo pair RGB view in a time-sharing interleaved manner according to the DDR2 SDRAM read address generation logic; the FIFO control module is used for cross-clock domain operations, and it can obtain the RGB view in the stereo pair 3D view, and divide the stereo pair RGB view to obtain the left eye view and the right eye view; the display driver module is used for pixel reallocation of the processed left eye view and right eye view, and then output them to the naked-eye 3D display screen for display according to the display drive timing.

[0007] In the FPGA-based naked-eye 3D image processing driving circuit provided by the present invention, there is also such a feature: wherein the FIFO control module includes a wrFIFO module, a rdFIFO_L module and a rdFIFO_R module, the wrFIFO module is connected in communication with the SD card operation module and the DDR2 SDRAM controller module, and is responsible for obtaining the RGB view in the stereo pair 3D view and caching it; obtaining the left eye view and caching it. Similarly, the rdFIFO_R module is also connected in communication with the DDR2 SDRAM controller module and the display driver module, and its function is to obtain the right eye view and cache it.

[0008] The FPGA-based naked-eye 3D image processing driving circuit provided by the present invention also has the following feature: wherein the SD card operation module includes an SD card control module and an SPI bus control module.

[0009] The FPGA-based naked-eye 3D image processing driving circuit provided by the present invention also has the following feature: wherein, pixel reallocation is column interpolation fusion processing.

[0010] The FPGA-based naked-eye 3D image processing driving circuit provided by the present invention also has the following feature: wherein the FPGA data processing module is also connected to an external 3D view input device to obtain a stereoscopic 3D view therefrom.

[0011] The FPGA-based naked-eye 3D image processing driving circuit provided by the present invention also has the following features: the stereoscopic 3D view is in 24-bit BMP format, the image resolution is 800×600, and the naked-eye 3D display screen module is a naked-eye 3D liquid crystal display screen with a TTL interface.

[0012] The present invention provides an algorithm for the above-mentioned FPGA-based naked-eye 3D image processing driving circuit, which is characterized in that: The method comprises the following steps: step 1: obtaining a stereo pair 3D view; step 2: caching the RGB view in the stereo pair 3D view; step 3: dividing the stereo pair RGB view into left and right eye views, and caching the left eye view and the right eye view; step 4: realigning pixels of the left eye view and the right eye view; step 5: outputting to a naked eye 3D display screen module according to a display drive timing to realize naked eye 3D display.

[0013] The algorithm of the FPGA-based naked-eye 3D image processing driving circuit provided by the present invention also has the following feature: wherein, step 1 is to obtain a stereoscopic 3D view from a 3D view input device or to obtain a 3D view from an SD card image storage module.

[0014] In the present invention, an algorithm of a naked-eye 3D image processing driving circuit based on FPGA is provided. The algorithm has the following features: When reading or writing to an SD card, you first need to power it on and wait for the SD card to be ready.

[0015] Send at least 74 SPI clock cycles to ensure the SD card is initialized correctly.

[0016] Through the defined internal logic state machine, the initialization command is sent step by step to complete the initialization process of the SD card.

[0017] When the SD card is initialized and enters the IDLE state, you can start reading and writing operations.

[0018] During the SD card initialization process, send the command CMD16 to set the size of a read / write BLOCK to 512 bytes, which is the size of a sector in the SD card.

[0019] After initialization is completed, read the stereo pair image data stored in the SD card.

[0020] Send command CMD17 and wait for receiving the read data start token 0xfe.

[0021] Read 512 bytes of data and 2 bytes of CRC check code.

[0022] In the logic design, a 32-bit read sector start address register arg is defined.

[0023] Each time the command CMD17 is sent, the value of the arg register is updated and increased by 512 (arg<=arg+32'd512).

[0024] In summary, the algorithm of the present invention realizes the function of reading stereo pair image data from the SD card by performing appropriate initialization and read and write operations on the SD card.

[0025] Functions and effects of the present invention: The FPGA-based naked-eye 3D image processing driving circuit of the present invention fills the gap of the current lack of MCU and graphics chip that meet the image processing requirements of naked-eye 3D. The present invention adopts a modular design, and divides the hardware logic inside the FPGA into a clock and reset module, an SD card operation module, a FIFO control module, a DDR2 SDRAM controller module, and a display driver module. The circuit runs a logic algorithm to realize reading left and right format stereoscopic image data from the SD card, pixel reconfiguration, and naked-eye 3D LCD display driving. By dividing the left and right eye view data, and performing pixel reconfiguration on the naked-eye 3D LCD sub-screen, the naked-eye 3D display effect is finally realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram of a naked-eye 3D image processing driving circuit based on FPGA in an embodiment of the present invention; Figure 2 is a logic function diagram of a naked-eye 3D image processing driving circuit based on FPGA in an embodiment of the present invention; Figure 3 Schematic diagram of the SD card initialization process in an embodiment of the present invention; Figure 4 is a block diagram of a data processing module of the present invention; Figure 5 This is a block diagram of the LVDS interface naked-eye 3D liquid crystal screen data processing of the present invention. DETAILED DESCRIPTION

[0027] In order to make the technical means, creative features, objectives and effects of the present invention easy to understand, The following embodiments specifically describe the FPGA-based naked-eye 3D image processing driving circuit and its algorithm in conjunction with the accompanying drawings.

[0028] like Figure 1 As shown, the FPGA-based naked-eye 3D image processing driving circuit of this embodiment includes: an FPGA data processing module 1, an SD card image storage module 2, a DDR2 SDRAM cache module 3, a naked-eye 3D display screen module 4, a signal source 5, a crystal oscillator module 6, a JTAG module 7, and a power supply 8.

[0029] The SD card image storage module is used to store stereoscopic 3D views in left and right formats. The 3D view input device has a 3D view input interface for transmitting 3D video images. The SD card image storage module and the signal source are respectively connected to the FPGA data processing module. The FPGA data processing module obtains 3D video image data from the SD card image storage module or the signal source. The FPGA data processing module is responsible for completing cross-clock domain operations and pixel reallocation. The DDR2 SDRAM cache module is connected to the FPGA data processing module for caching image data. The naked eye 3D display screen module is connected to the FPGA data processing module for realizing naked eye 3D display. The crystal oscillator module is used to execute the crystal oscillator configuration mode. The JTAG module is used to execute the JTAG configuration mode. Independent buttons are used for manual operation by the operator.

[0030] In this embodiment, the stereoscopic 3D view is in 24-bit BMP format, the image resolution is 800×600, the naked-eye 3D display screen module is a naked-eye 3D LCD display screen based on parallax barrier technology, and the naked-eye 3D display screen is a TTL, LVDS interface screen. This setting achieves resolution matching and makes the display effect better.

[0031] like Figure 2 As shown, the hardware logic inside the FPGA data processing module is divided into five modules: clock and reset module, SD card operation module, FIFO control module, DDR2 SDRAM controller module and display driver module.

[0032] The clock and reset module is used to control the operating sequence of the SD card operation module, FIFO control module, DDR2 SDRAM controller module, and display driver module.

[0033] The main function of the SD card operation module is to perform various operations on the SD card image storage module. It contains two important submodules: the SD card control module and the SPI bus control module. The main task of the SD card control module is to perform some basic operations of the SD card, such as power-on initialization and read and write operations. The SPI bus control module is responsible for simulating and generating the SPI protocol to control the command or data interaction between the FPGA and the SD card. Before performing read and write operations, the SD card must be initialized first. Only when the SD card is successfully initialized and enters the IDLE state can the stereo pair image data stored in it be read, or read and write operations can be performed on it.

[0034] The communication link between the DDR2 SDRAM control module and the FIFO control module is mainly used to write the RGB stereo pair representation of the wrFIFO cache into the DDR2 SDRAM cache module. The specific implementation of this process is as follows: 1. In the DDR2 SDRAM control module, a state is generated to control the reading and writing of data. 2. According to the logic of the DDR2 SDRAM read address generator, the left and right eye stereo pair display data is read in a time-sharing interlaced manner. This is achieved by reading the left and right eye data at different times. 3. According to the change of the read state, the left and right eye view data are buffered in the rdFIFO_L module and the rdFIFO_R module. This is to complete the segmentation of the left and right eye views and prepare the necessary data for subsequent pixel reallocation. This process is to establish a communication link between the DDR2 SDRAM control module and the FIFO control module, write the RGB stereo pair representation of the wrFIFO cache into the DDR2 SDRAM cache module, and then read the left and right eye stereo pair display data in a time-sharing interlaced manner according to the logic of the DDR2 SDRAM read address generator. Finally, the left and right eye view data are buffered in the rdFIFO_L module and the rdFIFO_R module to complete the segmentation of the left and right eye views and prepare the necessary data for the subsequent pixel reallocation.

[0035] The display driver module plays an important role in the circuit design. It is responsible for pixel reallocation and driving the naked-eye 3D display screen. Specifically, L1, L2 and L3 are some column pixels of the left eye view, and R1, R2 and R3 are some column pixels of the right eye view. By using column interpolation fusion processing and precise timing control, the display driver module displays the left eye view and the right eye view in the stereo pair image on the left view sub-screen and the right view sub-screen of the naked-eye 3D in units of pixels.

[0036] The algorithm of the naked-eye 3D image processing driving circuit based on FPGA in this embodiment is operated according to the following steps: Step 1: Get a stereo pair 3D view from a 3D view input device or get a 3D view from an SD card image storage module; Step 2: Cache the RGB view in the stereo 3D view; Step 3: Segment the stereoscopic RGB view into left and right eye views, and cache the left eye view and the right eye view; Step 4: re-match pixels of the left-eye view and the right-eye view; Step 5: Display the left eye view in pixels on the left view sub-screen of the naked eye 3D screen according to the display driving timing, and display the right eye view in pixels on the right view sub-screen of the naked eye 3D screen to achieve naked eye 3D display.

[0037] like Figure 3 As shown, in the present invention, an algorithm of a naked-eye 3D image processing driving circuit based on FPGA is provided. The algorithm has the following features: When reading or writing to an SD card, you first need to power it on and wait for the SD card to be ready.

[0038] Send at least 74 SPI clock cycles to ensure the SD card is initialized correctly.

[0039] Through the defined internal logic state machine, the initialization command is sent step by step to complete the initialization process of the SD card.

[0040] When the SD card is initialized and enters the IDLE state, you can start reading and writing operations.

[0041] During the SD card initialization process, send the command CMD16 to set the size of a read / write BLOCK to 512 bytes, which is the size of a sector in the SD card.

[0042] After initialization is completed, read the stereo pair image data stored in the SD card.

[0043] Send command CMD17 and wait for receiving the read data start token 0xfe.

[0044] Read 512 bytes of data and 2 bytes of CRC check code.

[0045] In the logic design, a 32-bit read sector start address register arg is defined.

[0046] Each time the command CMD17 is sent, the value of the arg register is updated and increased by 512 (arg<=arg+32'd512).

[0047] In summary, the algorithm of the present invention realizes the function of reading stereo pair image data from the SD card by performing appropriate initialization and read and write operations on the SD card.

[0048] In this embodiment, the FPGA-based naked-eye 3D image processing driving circuit uses hardware description language to design logic codes such as reading left and right format stereoscopic image data, pixel reallocation, and naked-eye 3D LCD display driving from the SD card according to the naked-eye 3D sub-screen partition characteristics, completes the left and right eye view data segmentation, and performs pixel reallocation on the naked-eye 3D LCD sub-screen, thereby realizing naked-eye 3D display. The present invention provides a useful reference method for the design of integrated circuits for naked-eye 3D video and image data processing.

Claims

1. A naked eye 3D image processing driving circuit based on FPGA and its algorithm, characterized in that: include: FPGA data processing module, SD card image storage module, DDR2 SDRAM cache module and naked eye 3D display module, Wherein, the SD card image storage module is used to store the stereoscopic 3D views in left and right formats; The SD card image storage module is connected to the FPGA data processing module, and the FPGA data processing module obtains the RGB view in the stereo pair 3D view; The DDR2 SDRAM cache module is connected to the FPGA data processing module and is used to cache the stereo pair RGB view; the FPGA data processing module also reads the cached stereo pair RGB view data and divides it into a left eye view and a right eye view; The naked-eye 3D display screen module is connected to the FPGA data processing module, and the FPGA data processing module performs pixel reallocation on the left-eye view and the right-eye view and outputs them to the naked-eye 3D display screen module for display according to a display driving timing.

2. The naked eye 3D TV pixel configuration system according to claim 1, characterized in that: in, The FPGA data processing module includes: a system clock and reset module, an SD card operation module, a FIFO control module, a DDR2 SDRAM controller module and an LVDS transmission display module, wherein the clock and reset module is used to control the operation timing of the SD card operation module, the FIFO control module, the DDR2 SDRAM controller module and the display driver module; The SD card operation module is used to read and write image data in the SD card, including controlling the communication between the SD card and the SPI bus; The DDR2 SDRAM controller module is in communication with the FIFO control module, manages and controls the read and write operations of the DDR2 SDRAM, provides a high-speed cache for image data processing, and generates a state of reading the left eye view and the right eye view of the stereo pair RGB view in a time-sharing interleaved manner according to the DDR2 SDRAM read address generation logic; The FIFO control module is used to manage the input and output of data, obtain the RGB view in the stereo pair 3D view, and segment the stereo pair RGB view into left and right eye views; The LVDS transmission display module is used for high-speed image and video data transmission and displaying on the naked-eye 3D display screen module.

3. The naked eye 3D television pixel configuration system according to claim 2, characterized in that: in, The FIFO control module includes a write DDR2 SDRAM cache FIFO module, a read DDR2 SDRAM cache FIFO module, a rdFIFO_L module and a rdFIFO_R module, the write DDR2 SDRAM cache FIFO module, the read DDR2 SDRAM cache FIFO module and the SD card operation module and the DDR2 SDRAM controller module, Communication connection for obtaining RGB view of the stereo pair 3D view for caching and display; The rdFIFO_L module is in communication with the DDR2 SDRAM controller module and the display driver module, and is used to obtain the left eye view for caching; The rdFIFO_R module is in communication with the DDR2 SDRAM controller module and the display driver module, and is used to obtain the right eye view for caching.

4. The naked eye 3D television pixel configuration system according to claim 2, characterized in that: in, The SD card operation module includes an SD card control module and an SPI bus control module.

5. The naked eye 3D television pixel configuration system according to claim 1, characterized in that: in, The pixel reallocation is a column interpolation fusion process.

6. The naked eye 3D television pixel configuration system according to claim 1, characterized in that: in, The FPGA data processing module is also connected to an external 3D view input device to obtain a stereo pair 3D view therefrom.

7. The naked-eye 3D TV pixel configuration system according to any one of claims 1 to 6, characterized in that: in, The stereoscopic 3D view is in 24-bit BMP format with an image resolution of 800×600. The naked-eye 3D display screen module is a naked-eye 3D liquid crystal display screen with a TTL interface.

8. The algorithm based on the naked eye 3D TV pixel configuration system as claimed in any one of claim 7, characterized in that: The steps include: Step 1: Get a stereo pair 3D view; Step 2: Cache the RGB view in the stereo 3D view; Step 3: Segment the stereoscopic RGB view into left and right eye views, and cache the left eye view and the right eye view; Step 4: re-match pixels of the left-eye view and the right-eye view; Step 5: Output the pixel-reconfigured left-eye view and right-eye view to the naked-eye 3D display screen module according to the display driving timing to realize naked-eye 3D display.

9. The algorithm based on the naked eye 3D TV pixel configuration system as claimed in claim 8, characterized in that: in, Step 1 is to obtain a stereo pair 3D view from a 3D view input device or obtain a 3D view from an SD card image storage module.

10. The algorithm based on the naked eye 3D TV pixel configuration system as claimed in claim 9, wherein: When the SD card image storage module is read and written, the following initialization operations are performed in advance: (1) When reading and writing to an SD card, you first need to power it on and wait for the SD card to be ready. (2) Send at least 74 SPI clock cycles to ensure that the SD card is initialized correctly; (3) Through the defined internal logic state machine, the initialization command is sent step by step to complete the initialization process of the SD card; (4) After the SD card is initialized and enters the IDLE state, you can start reading and writing operations; (5) During the SD card initialization process, send the command CMD16 to set the size of a read / write block to 512 bytes, which is the size of a sector in the SD card; (6) After initialization is completed, read the stereo pair image data stored in the SD card; (7) Send command CMD17 and wait for receiving the read data start token 0xfe; (8) Read 512 bytes of data and 2 bytes of CRC check code; (9) In the logic design, define a 32-bit read sector start address register arg; (10) After each command CMD17 is sent, update the value of the arg register to increase it by 512 (arg<=arg+32'd512).

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