Semiconductor module

Abstract

A semiconductor device is flip-chip mounted on a mounting substrate. The molding resin encapsulates the semiconductor device. An insulating thermally conductive member having a thermal conductivity higher than that of the molding resin is disposed on a surface of the semiconductor device facing the mounting substrate. The semiconductor device includes: a device layer in which a transistor is formed; a plurality of bumps disposed on a surface of the device layer facing the mounting substrate and connected to the mounting substrate; and an insulating layer disposed on a surface of the device layer opposite to a surface facing the mounting substrate. In a plan view of the mounting substrate, the transistor has a non-overlapping portion that does not overlap any of the plurality of bumps. The thermally conductive member is disposed continuously from a region overlapping the non-overlapping portion to at least one of the plurality of bumps.

Description

Technical Field

[0001] The invention relates to a semiconductor module. Background Art

[0002] In a semiconductor device in which a high-frequency circuit is formed on an SOI substrate in which an insulating layer and a semiconductor layer are stacked on a supporting substrate composed of silicon, there is a case where high-order harmonic distortion is generated due to parasitic capacitance between the semiconductor layer and the supporting substrate. Patent document 1 below discloses a semiconductor device in which parasitic capacitance is reduced by removing a supporting substrate composed of silicon after a semiconductor device made of an SOI substrate is mounted on a mounting substrate. Resin is arranged in the space after the supporting substrate is removed.

[0003] Patent document 1: U.S. Patent Application Publication No. 2019 / 0326159.

[0004] The heat generated by the transistor formed in the semiconductor layer is mainly conducted to the mounting substrate via the nearest bump. However, according to the research of the inventor of the present application, it is clear that in the semiconductor device of the structure disclosed in Patent Document 1, the temperature of the transistor is easy to rise compared with the structure of the support substrate composed of Si with the SOI substrate remaining. Summary of the invention

[0005] An object of the present invention is to provide a semiconductor module capable of suppressing an increase in parasitic capacitance generated in a semiconductor layer and suppressing a temperature rise of a transistor formed in the semiconductor layer.

[0006] According to one aspect of the present invention, there is provided a semiconductor module comprising:

[0007] Install the base plate;

[0008] A semiconductor device is mounted on the mounting substrate in a flip-chip manner;

[0009] molding resin to seal the semiconductor device; and

[0010] an insulating heat-conductive member disposed on a surface of the semiconductor device facing the mounting substrate and having a heat conductivity higher than that of the molding resin,

[0011] The semiconductor device comprises:

[0012] a device layer, in which transistors are formed;

[0013] A plurality of bumps are arranged on a surface of the device layer opposite to the mounting substrate and connected to the mounting substrate;

[0014] an insulating layer disposed on a surface of the device layer opposite to a surface facing the mounting substrate,

[0015] The transistor has a non-overlapping portion that does not overlap with any of the plurality of bumps when the mounting substrate is viewed from above, and the thermally conductive member is disposed continuously from a region overlapping with the non-overlapping portion to at least one of the plurality of bumps.

[0016] Effects of the Invention

[0017] The heat generated in the non-overlapping portion of the transistor is conducted to the bumps connected to the thermally conductive member via the thermally conductive member, thereby suppressing the temperature rise of the non-overlapping portion of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram showing the planar positional relationship of some components of the semiconductor device mounted on the semiconductor module provided in the first embodiment.

[0019] Figure 2 is a cross-sectional view of a portion of the semiconductor module provided by the first embodiment.

[0020] FIG. 3A to FIG. 3D The accompanying drawing is a schematic cross-sectional view of a semiconductor device mounted on a semiconductor module provided in the first embodiment at a mid-stage of manufacturing.

[0021] Figure 4A is a diagram showing the positional relationship between a transistor and a plurality of bumps of a semiconductor device when viewed from above. Figure 4B This is a schematic perspective view of a state where a semiconductor device is mounted on a mounting substrate.

[0022] Figure 5A is a schematic cross-sectional view of a semiconductor module provided in the first embodiment, Figure 5B It is a schematic cross-sectional view of a semiconductor device and a mounting substrate provided as a comparative example.

[0023] FIG. 6A to FIG. 6D The accompanying drawing is a schematic cross-sectional view of a semiconductor device mounted on a semiconductor module provided in a modified example of the first embodiment at a mid-stage of manufacturing.

[0024] Fig. 7A as well as Figure 7B It is a diagram showing the planar positional relationship of a plurality of components of a semiconductor device mounted on a semiconductor module provided in another modified example of the first embodiment.

[0025] Figure 8 FIG. 1 is a schematic cross-sectional view of a semiconductor module provided in the second embodiment.

[0026] Fig.9A as well as Fig. 9B FIG. 1 is a cross-sectional view of a semiconductor module provided in the second embodiment at an intermediate stage of manufacturing.

[0027] Fig.10 is a block diagram of a high frequency module provided by the third embodiment. DETAILED DESCRIPTION

[0028] [First embodiment]

[0029] Reference Figures 1 to 5B The semiconductor module provided by the first embodiment is described with reference to the accompanying drawings.

[0030] Figure 1 The schematic diagram shows the planar positional relationship of some components of the semiconductor device 10 mounted on the semiconductor module provided in the first embodiment. The insulating layer 20 and the device layer 30 are arranged to be almost overlapped in a plan view. A transistor 31 is arranged in a region inside the device layer 30 .

[0031] The transistor 31 is, for example, a multi-finger MOS-FET, including a plurality of source regions 31S, a plurality of drain regions 31D, and a plurality of gate electrodes 31G. The plurality of source regions 31S and the plurality of drain regions 31D are arranged alternately in a single direction in the active region. The xy plane is defined as the plane parallel to the surface of the device layer 30, and the direction in which the plurality of source regions 31S and the plurality of drain regions 31D are arranged is defined as an xyz orthogonal coordinate system in the x direction. A gate electrode 31G is respectively arranged between mutually adjacent source regions 31S and drain regions 31D.

[0032] In a plan view, a plurality of source contact regions 32S arranged along the y direction are divided inside each of the plurality of source regions 31S. Similarly, a plurality of drain contact regions 32D arranged along the y direction are divided inside each of the plurality of drain regions 31D. Here, the source contact region 32S refers to the source region 31S and the source contact electrode (see below). Figure 2 Note) The ohmic contact region, the drain contact region 32D refers to the drain region 31D and the drain contact electrode (see below) Figure 2 Here, “when viewed from above” means when the device layer 30 in which the transistor 31 is arranged is viewed from above from the stacking direction of the insulating layer 20 and the device layer 30 .

[0033] Through the transistor 31 and the wiring ( Figure 1 A is not shown. ) constitutes a high-frequency circuit. Examples of high-frequency circuits include a low-noise amplifier that amplifies high-frequency signals, a switch that selects one from a plurality of duplexers, filters, etc. provided for each frequency band, and the like. The switch is constituted by, for example, a CMOS-FET.

[0034] In a plan view, the rectangle with the smallest area including all of the plurality of source contact regions 32S and the plurality of drain contact regions 32D of the transistor 31 is referred to as the smallest including rectangle 40. Figure 1 In FIG. 4 , the outer periphery of the minimum inclusion rectangle 40 is indicated by a dotted line, and the interior of the minimum inclusion rectangle 40 is hatched. The region within the minimum inclusion rectangle 40 can be regarded as a region where the transistor 31 is actually arranged.

[0035] A metal layer 37 is arranged slightly inside the outer circumference of the device layer 30 so as to surround the inner region of the device layer 30 in a plan view. The metal layer 37 is also called a guard ring. The metal layer 37 is separated into a plurality of parts in the circumferential direction. In addition, the metal layer 37 may be configured to be continuous in the circumferential direction so that the metal layer 37 has a closed ring shape in a plan view.

[0036] Figure 2 1 is a cross-sectional view of a portion of the semiconductor module provided in the first embodiment. The semiconductor module provided in the first embodiment includes a mounting substrate 80 , a semiconductor device 10 mounted on the mounting substrate 80 , a heat conducting member 85 , and a molding resin 86 .

[0037] The semiconductor device 10 includes a device layer 30, an insulating layer 20, a support substrate 50 made of an insulating resin, and a plurality of bumps 70. Figure 2 , one of the plurality of bumps 70 is shown. A direction from the semiconductor device 10 toward the mounting substrate 80 is defined as an upward direction.

[0038] The device layer 30 is arranged on the upper surface of the insulating layer 20, and the support substrate 50 is arranged on the lower surface. The insulating layer 20 can be composed of a single layer or a plurality of layers. For example, when the insulating layer 20 is composed of a single layer, silicon oxide is used as the material of the insulating layer 20. When the insulating layer 20 is composed of a plurality of layers, for example, silicon oxide, silicon nitride, etc. are used as the material of each layer. As the resin material of the support substrate 50, it is preferred to use a material with low electrical conductivity and dielectric loss tangent to avoid negatively affecting the high-frequency characteristics of the semiconductor device 10. For example, polyimide can be used as the material of the support substrate 50. The thermal conductivity of polyimide is about 0.25 W / m·K.

[0039] The device layer 30 includes an element formation layer 39 made of semiconductor in contact with the insulating layer 20, and a multilayer wiring layer arranged on the element formation layer 39. The element formation layer 39 includes an active region made of silicon and an insulating element isolation region 39I surrounding the active region. A plurality of source regions 31S, a plurality of drain regions 31D, and a plurality of channel regions 31C of the transistor 31 are arranged in the active region of the element formation layer 39.

[0040] The plurality of source regions 31S and the plurality of drain regions 31D are arranged in the x direction at intervals. The channel region 31C is defined between the mutually adjacent source regions 31S and drain regions 31D. A gate electrode 31G is arranged on the channel region 31C via a gate insulating film (not shown).

[0041] The multilayer wiring layer on the element formation layer 39 includes a plurality of insulating layers 60. For example, a low dielectric constant material (Low-k material) is used for the plurality of insulating layers 60. For example, SiN or an organic insulating material is used for the uppermost insulating layer 60.

[0042] The source contact electrode 33S and the drain contact electrode 33D are filled in the through hole of the lowest insulating layer 60 provided in the multilayer wiring layer. The source contact electrode 33S is in ohmic contact with the source region 31S in the source contact region 32S, and the drain contact electrode 33D is in ohmic contact with the drain region 31D in the drain contact region 32D. The source contact electrode 33S and the drain contact electrode 33D are formed of W, for example. It is also possible to configure a close contact layer such as TiN for the purpose of improving close contact as needed. In addition, it is also possible to have the following structure: a film composed of metal silicide such as CoSi and NiSi is formed on the surface of each of the source region 31S and the drain region 31D to reduce the resistance of the contact portion.

[0043] A plurality of wirings 34 or a plurality of through holes 35 are respectively arranged on the plurality of insulating layers 60 above the second layer. The wirings 34 or through holes 35 are formed using a damascene method, a dual damascene method, or a subtractive method. A plurality of wirings 34T and a plurality of pads 34P are arranged on the uppermost wiring layer of the device layer 30. As an example, the wirings 34, 34T and the pads 34P are formed of Cu or Al, and the through holes are formed of Cu or W. In addition, a close-fitting layer such as TiN may be arranged as needed for the purpose of preventing diffusion and improving close-fitting. A metal layer 37 called a guard ring is arranged on the periphery of the multilayer wiring layer.

[0044] A protective film 61 made of an organic insulating material is disposed on the device layer 30 to cover the wiring 34T and the pad 34P of the uppermost layer. Examples of the organic insulating material used for the protective film 61 include polyimide, benzocyclobutene (BCB), etc. The protective film 61 is provided with a plurality of openings for exposing the upper surfaces of the plurality of pads 34P, and a bump 70 is disposed on the pad 34P in the opening. The bump 70 is composed of, for example, an under-bump metal layer, a Cu column, and a solder layer. In addition, components of other structures may also be used as the bump 70.

[0045] The bump 70 is connected to the pad 81 of the mounting substrate 80, whereby the semiconductor device 10 is mounted on the mounting substrate 80 in a flip chip manner. A heat conducting member 85 is arranged on the surface of the device layer 30 that faces the mounting substrate 80 via the protective film 61. In addition, the heat conducting member 85 is not arranged in the region where the bump 70 is arranged. The heat conducting member 85 is thermally coupled to the device layer 30 via the protective film 61. In addition, the heat conducting member 85 contacts the side surface of the bump 70 and is thermally coupled to the bump 70.

[0046] The semiconductor device 10 and the heat-conducting component 85 are sealed by the molding resin 86. Specifically, the molding resin 86 contacts the surface of the semiconductor device 10 opposite to the surface facing the mounting substrate 80 and the side surface, and fills the space between the heat-conducting component 85 and the mounting substrate 80. The molding resin 86 uses, for example, an epoxy resin containing a filler. The filler uses, for example, silicon dioxide, and the filling rate of the filler is, for example, 70wt%.

[0047] The heat conducting member 85 is formed of an insulating material, and the heat conductivity of the heat conducting member 85 is higher than that of the molded resin 86. In addition, the heat conductivity of the heat conducting member 85 is higher than that of the support substrate 50. The heat conducting member 85 uses, for example, an epoxy resin containing a filler. The filler uses, for example, silicon dioxide, and the filling rate of the filler is, for example, 80 wt%. In addition, other resins such as silicon oxide resins may be used instead of epoxy resins. As for the filler, alumina may be used instead of silicon dioxide, or alumina may be used together with silicon dioxide.

[0048] The material and filling rate of the filler mixed in the resin material of the heat conductive component 85 and the molded resin 86 are adjusted so that the thermal conductivity of the heat conductive component 85 is higher than the thermal conductivity of the molded resin 86. For example, the weight filling rate of the filler of the heat conductive component 85 is higher than the weight filling rate of the filler of the molded resin 86.

[0049] The thickness of the device layer 30 is, for example, 10 μm, and the thickness of the bump 70 is, for example, 160 μm. The thickness of the heat-conducting component 85 is, for example, 1 / 10 or more of the thickness of the bump 70. That is, the thickness of the heat-conducting component 85 is 100 times or more of the thickness of the device layer 30. In addition, the thermal conductivity of the heat-conducting component 85 is higher than the thermal conductivity of the support substrate 50 and the molding resin 86. Therefore, the heat generated in the transistor 31 is mainly conducted in the multilayer wiring layer of the device layer 30 in the thickness direction and reaches the heat-conducting component 85, and then conducted in the heat-conducting component 85 in the in-plane direction and reaches the bump 70.

[0050] Next, refer to FIG. 3A to FIG. 3D The following describes a method for manufacturing a semiconductor device 10 mounted on a semiconductor module provided in the first embodiment with reference to the accompanying drawings. FIG. 3A to FIG. 3DThe drawing is a schematic cross-sectional view of a semiconductor device 10 mounted on a semiconductor module provided in the first embodiment at a mid-stage of manufacturing.

[0051] like Figure 3A As shown in FIG. 1 , an SOI substrate 90 including a temporary support substrate 91 made of silicon, an insulating layer 20 made of silicon oxide, and an element formation layer 39 made of silicon is prepared. An element isolation region 39I is formed in a portion of the element formation layer 39, and a transistor 31 is formed in an active region. Figure 3A , a source region 31S, a drain region 31D, and a gate electrode 31G are schematically shown one each. In addition, a multilayer wiring layer of an element formation layer 39 is formed. The multilayer wiring layer includes a pad 34P on the top layer. The element formation layer 39 and the multilayer wiring layer constitute a device layer 30. A protective film 61 made of an organic insulating material is formed on the device layer 30, and a bump 70 is further formed. These structures can be formed using a general semiconductor wafer process.

[0052] like Figure 3B As shown, temporary support substrate 91 is etched away. Before temporary support substrate 91 is etched away, a protective tape (not shown) or the like is previously attached to the surface opposite to temporary support substrate 91. By removing temporary support substrate 91, one surface of insulating layer 20 is exposed.

[0053] like Figure 3C As shown in FIG. 1 , a support substrate 50 made of polyimide or the like is attached to the exposed surface of the insulating layer 20. Figure 3D As shown, a heat conducting member 85 is formed on the surface exposed by the protective film 61. For example, a coating method can be used to form the heat conducting member 85. After the heat conducting member 85 is formed, the stacked structure from the support substrate 50 to the heat conducting member 85 is cut into individual pieces.

[0054] Next, refer to Figure 4A as well as Figure 4B , the positional relationship between the transistor 31 of the semiconductor device 10 and the plurality of bumps 70 in a plan view will be described. Figure 4A 1 is a diagram showing the positional relationship between the transistor 31 of the semiconductor device 10 and a plurality of bumps 70 when viewed from above. Figure 4B 8 is a schematic perspective view of a state where the semiconductor device 10 is mounted on a mounting substrate 80. Figure 2 ), a plurality of transistors are arranged in addition to the transistor 31. In a plan view, the heat conducting member 85 is arranged in the entire area of ​​the insulating layer 20 and the device layer 30 where the bump 70 is not arranged. Figure 4A In FIG. 1 , the region where the heat conducting member 85 is arranged is shaded.

[0055] The plurality of bumps 70 of the semiconductor device 10 are connected to the mounting substrate 80. When viewed from above, a portion of the transistor 31 overlaps with one bump 70, and the other portion does not overlap with any of the bumps 70. “A portion of the transistor 31 overlaps with the other portion when viewed from above” means Figure 1 The smallest enclosing rectangle 40 is shown overlapping with other portions.

[0056] The portion of transistor 31 that overlaps with bump 70 is called overlapping portion 31X, and the portion that does not overlap is called non-overlapping portion 31Y. In a plan view, the area of ​​non-overlapping portion 31Y is larger than the area of ​​overlapping portion 31X. When semiconductor device 10 is operated, transistor 31 becomes a main heat source.

[0057] Next, refer to Figure 5A as well as Figure 5B , the excellent effects of the first embodiment are explained.

[0058] Figure 5B FIG. 1 is a schematic cross-sectional view of a semiconductor device 10A and a mounting substrate 80 provided in a comparative example. The semiconductor device 10 is mounted on the mounting substrate 80 by connecting the semiconductor device 10A to the mounting substrate 80 through a plurality of bumps 70. In the semiconductor device 10A provided in the comparative example, the heat conducting member 85 ( Figure 5A ). In the structure of the support substrate composed of Si with the SOI substrate remaining, the problem caused by the temperature rise of the transistor 31 is not significant. The heat generated by the transistor 31 is conducted to the mounting substrate 80 via the nearest bump 70, so it is considered that sufficient heat dissipation efficiency can be obtained.

[0059] However, if Figure 5B As shown in FIG. 1 , the inventors have conducted experiments to find that if the support substrate made of Si is removed and a support substrate 50 made of resin is arranged instead, the temperature rise of the transistor 31 becomes significant. The phenomenon that the heat generated by the transistor 31 is conducted to the mounting substrate 80 via the nearest bump 70 is Figure 5B The structure in which the support substrate composed of Si remains is common to the structure in which the support substrate composed of Si remains. It is believed that the sufficient heat dissipation efficiency is obtained in the structure in which the support substrate composed of Si remains because the support substrate composed of Si also functions as a heat conduction path. That is, the heat generated in the non-overlapping portion 31Y of the transistor 31 is conducted to the bump 70 via the support substrate.

[0060] If the support substrate made of Si is replaced with a support substrate 50 made of a resin having low thermal conductivity, the support substrate 50 will not actually function as a heat conduction path. Therefore, the thermal resistance from the non-overlapping portion 31Y of the transistor 31 to the nearest bump 70 increases. As a result, the temperature rise of the non-overlapping portion 31Y of the transistor 31 becomes significant.

[0061] Figure 5A FIG. 1 is a schematic cross-sectional view of a semiconductor module provided in the first embodiment. Figure 5A The arrows shown indicate main heat transfer paths through which heat generated in the transistor 31 is transferred to the mounting substrate 80 .

[0062] The heat generated in the overlapping portion 31X of the transistor 31 is mainly transferred to the mounting substrate 80 via the bump 70 that overlaps the overlapping portion 31X of the transistor 31 in a plan view. The heat generated in the non-overlapping portion 31Y of the transistor 31 is mainly transferred to the bump 70 that has a portion overlapping the transistor 31 via the heat-conducting member 85. Furthermore, the heat generated in the transistor 31 is diffused in the in-plane direction via the heat-conducting member 85 and is also transferred to the bump 70 that has no portion overlapping the transistor 31.

[0063] In the structure in which the support substrate composed of Si remains, in the semiconductor module provided in the first embodiment, the heat conducting member 85 assumes the role of the support substrate composed of Si as a heat conduction path. Therefore, the heat generated in the non-overlapping portion 31Y of the transistor 31 is diffused in the in-plane direction within the heat conducting member 85 and conducted to the bump 70. As a result, the heat dissipation efficiency from the non-overlapping portion 31Y of the transistor 31 is improved, and the temperature rise of the non-overlapping portion 31Y can be suppressed.

[0064] Furthermore, in the first embodiment, the heat conducting member 85 is also in contact with the bump 70 having no portion overlapping with the transistor 31 in a plan view. Therefore, the bump 70 having no portion overlapping with the transistor 31 also functions as a heat conduction path from the transistor 31 to the mounting substrate 80. Since the plurality of bumps 70 function as a heat conduction path, the heat dissipation efficiency from the transistor 31 is improved, and the temperature rise of the transistor 31 can be suppressed.

[0065] In the configuration where the heat conducting member 85 is not provided, the thermal resistance from the non-overlapping portion 31Y of the transistor 31 to the bump 70 is higher than the thermal resistance from the overlapping portion 31X to the bump 70. The heat conducting member 85 has a function of reducing the thermal resistance from the non-overlapping portion 31Y of the transistor 31 to the bump 70. Therefore, in the case where the area of ​​the non-overlapping portion 31Y of the transistor 31 is larger than the area of ​​the overlapping portion 31X, the effect of providing the heat conducting member 85 is further improved.

[0066] Furthermore, since the heat conducting member 85 is formed of an insulating material, the parasitic capacitance generated in the device layer 30 is not increased. Therefore, the degradation of the high frequency characteristics of the semiconductor device 10 is suppressed.

[0067] Next, a semiconductor module provided by a modified example of the first embodiment is described. In the first embodiment, a resin containing a filler is used as the heat conducting component 85 ( Figure 5A), but in this modification, an inorganic insulating material having a higher thermal conductivity than the mold resin 86 is used. As an example of the inorganic insulating material used for the heat conductive member 85, diamond-like carbon (DLC) is cited.

[0068] When the heat-conducting member 85 is formed of DLC, for example, when X-ray photoelectron spectroscopy (XPS) analysis is performed toward the lower surface of the insulating layer 20 (the surface in contact with the supporting substrate 50), a peak of sp3 is detected in the spectrum analysis of carbon. In addition, the material of the heat-conducting member 85 is not limited to DLC. For example, the heat-conducting member 85 may also include materials such as aluminum oxide (including sapphire), aluminum nitride, or boron nitride. The thermal conductivity of these materials is shown in the following table.

[0069]

Table 1

[0070] Material Thermal conductivity [W / m·k] DLC 1000 Alumina (including sapphire) 42 Aluminum Nitride 320 Boron Nitride 410

[0071] Next, refer to FIG. 6A to FIG. 6D A method for manufacturing a semiconductor device 10 mounted on a semiconductor module provided in this variation is described with reference to the accompanying drawings. FIG. 6A to FIG. 6D The drawing is a schematic cross-sectional view of a semiconductor device 10 mounted on a semiconductor module according to the present modification example at a mid-stage of manufacturing.

[0072] In the first embodiment, when forming the heat conducting member 85 ( Figure 3D ) before forming the bump 70 ( Figure 3A ). In contrast, in this variation, if Fig. 6A As shown, after forming the protective film 61 and before forming the bump 70, a heat conducting component 85 made of DLC is formed on the protective film 61. For example, the heat conducting component 85 made of DLC can be formed by plasma chemical vapor deposition (P-CVD) using hydrocarbon gas, sputtering using a solid carbon target, or the like.

[0073] like Figure 6B As shown, in the region where the bump 70 is to be formed, an opening is formed penetrating the heat conducting member 85 and the protective film 61 to reach the pad 34P, and the bump 70 is formed on the pad 34P in the opening.

[0074] like Figure 6C As shown in FIG. 1 , the temporary support substrate 91 is removed by etching to expose the lower surface of the insulating layer 20. Fig.6D As shown, a support substrate 50 is attached to the exposed lower surface of the insulating layer 20 .

[0075] As in this modification, a mold resin 86 ( Figure 5A) is used as the heat conducting member 85. In this modification, as in the first embodiment, the excellent effect of suppressing the temperature rise of the transistor 31 and not increasing the parasitic capacitance generated in the device layer 30 can be obtained.

[0076] Next, refer to Fig. 7A as well as Figure 7B A semiconductor module provided in another modified example of the first embodiment will be described. Fig. 7A as well as Figure 7B 1 is a diagram showing the planar positional relationship of a plurality of components of a semiconductor device 10 mounted on a semiconductor module provided in this modification. Fig. 7A as well as Figure 7B In the figure, the area where the heat conducting member 85 is arranged is shaded. Figure 4A ), in addition to the area where the bumps 70 are arranged, the heat conducting member 85 is arranged in the entire area of ​​the device layer 30. Fig. 7A , Figure 7B In the illustrated modification, the thermally conductive member 85 is disposed only in a partial region of the device layer 30 .

[0077] exist Fig. 7A In the illustrated modification, the heat conducting member 85 includes the non-overlapping portion 31Y of the transistor 31 in a plan view, and contacts one bump 70 having a portion overlapping the transistor 31. The heat generated in the non-overlapping portion 31Y of the transistor 31 is conducted to the bump 70 having a portion overlapping the transistor 31 via the heat conducting member 85. Therefore, the heat dissipation efficiency of the heat generated in the non-overlapping portion 31Y can be improved.

[0078] exist Figure 7B In the modified example shown, the heat conducting member 85 includes the non-overlapping portion 31Y of the transistor 31 in a plan view, and contacts the bump 70 having a portion overlapping with the transistor 31 and one bump 70 having a portion not overlapping with the transistor 31. The heat generated in the overlapping portion 31X and the non-overlapping portion 31Y of the transistor 31 is transferred to the two bumps 70 via the heat conducting member 85. Fig. 7A Compared with the modified example shown, the heat dissipation efficiency from the transistor 31 can be further improved.

[0079] like Fig. 7A as well as Figure 7B As shown in the modified example, the heat conducting member 85 does not necessarily need to be arranged in the entire area of ​​the device layer 30. In particular, in order to improve the heat dissipation efficiency from the non-overlapping portion 31Y of the transistor 31, the heat conducting member 85 can be arranged continuously from the area overlapping with the non-overlapping portion 31Y to the position in contact with at least one of the plurality of bumps 70.

[0080] exist Fig. 7A as well as Figure 7B In the top view, the heat conducting component 85 includes one or two bumps 70, but the heat conducting component 85 may overlap or contact with a portion of one or more bumps 70. Fig. 7A as well as Figure 7B In the embodiment, the heat conducting member 85 may include the non-overlapping portion 31Y in a plan view, but the heat conducting member 85 may overlap a portion of the non-overlapping portion 31Y. That is, the configuration in which "the heat conducting member 85 is continuously arranged from the region overlapping with the non-overlapping portion 31Y to the position in contact with at least one of the plurality of bumps 70" includes a configuration in which the heat conducting member 85 overlaps a portion of the non-overlapping portion 31Y in a plan view, and a configuration in which the heat conducting member 85 overlaps or contacts a portion of one bump 70.

[0081] The transistor 31 ( Figure 2 ) is a MOS-FET, but the transistor 31 may be a bipolar transistor. When the transistor 31 is a bipolar transistor, the smallest rectangle including the emitter region, the base region, and the collector region in a plan view may be regarded as the region where the transistor 31 is arranged.

[0082] [Second embodiment]

[0083] Next, refer to Figure 8 , Fig.9A as well as Fig. 9B The semiconductor module provided by the second embodiment is described below. Figures 1 to 5A Description of the common structure of the semiconductor module provided in the first embodiment of the accompanying drawings is omitted.

[0084] Figure 8 2 is a schematic cross-sectional view of a semiconductor module provided in the second embodiment. Figure 5A ), a space is ensured between the heat-conducting component 85 and the mounting substrate 80, and the space is filled with the molding resin 86. In contrast, in the semiconductor device module provided in the second embodiment, the heat-conducting component 85 reaches the mounting substrate 80 from the surface of the semiconductor device 10 that is opposite to the mounting substrate 80. That is, the space between the device layer 30 and the mounting substrate 80 is filled with the heat-conducting component 85.

[0085] Next, refer to Fig.9A as well as Fig. 9B A method for manufacturing a semiconductor module provided in the second embodiment will be described. Fig.9A as well as Fig. 9B FIG. 1 is a cross-sectional view of a semiconductor module provided in the second embodiment at an intermediate stage of manufacturing.

[0086] like Fig.9A As shown, the semiconductor device 10 is mounted on the mounting substrate 80 in a flip chip manner. At this stage, a cavity is ensured between the surface of the semiconductor device 10 facing the mounting substrate 80 and the mounting substrate 80, and the heat conduction member 85 is not arranged ( Figure 8 ).like Fig. 9B As shown, a heat conducting member 85 is filled in a space between the surface of the semiconductor device 10 facing the mounting substrate 80 and the mounting substrate 80 .

[0087] An example of the process of filling the heat conductive component 85 is described below. Liquid resin containing fillers is injected along the end of the semiconductor device 10. The liquid resin and the fillers enter the space between the surface of the semiconductor device 10 facing the mounting substrate 80 and the mounting substrate 80 by capillary action. Then, the resin is cured by heating to form the heat conductive component 85.

[0088] Next, the excellent effects of the second embodiment will be described.

[0089] In the second embodiment, similarly to the first embodiment, the excellent effect of suppressing the temperature rise of the transistor 31 and not increasing the parasitic capacitance generated in the device layer 30 is obtained. In addition, in the second embodiment, the heat conducted to the heat conducting member 85 is conducted to the bump 70 and directly to the mounting substrate 80. Therefore, the heat dissipation efficiency from the transistor 31 can be further improved.

[0090] [Third embodiment]

[0091] Next, refer to Fig.10 The high-frequency module provided by the third embodiment is described below. The high-frequency module provided by the third embodiment includes the semiconductor module provided by the first embodiment or the second embodiment.

[0092] Fig.10 : is a block diagram of a high-frequency module provided in the third embodiment. The high-frequency module provided in the third embodiment includes a semiconductor device 10, a driver-stage amplifier circuit 110, a power-stage amplifier circuit 111, and a plurality of duplexers 112. The semiconductor device 10 includes an input switch 101, a frequency band selection switch 102 for transmission, an antenna switch 104, a frequency band selection switch 105 for reception, a low-noise amplifier 106, a power amplifier control circuit 107, a low-noise amplifier control circuit 108, and an output terminal selection switch 109 for reception. The high-frequency module has the function of receiving and transmitting in a frequency division duplex (FDD) manner. In addition, in Fig.10 In the figure, the description of the impedance matching circuit inserted as needed is omitted.

[0093] The two input side contacts of the input switch 101 are connected to the high-frequency signal input terminals IN1 and IN2, respectively. A high-frequency signal is input from the two high-frequency signal input terminals IN1 and IN2. When the input switch 101 selects one contact from the two input side contacts, the high-frequency signal input to the selected contact is input to the driver stage amplifier circuit 110.

[0094] The high-frequency signal amplified by the driver stage amplifier circuit 110 is input to the power stage amplifier circuit 111. The high-frequency signal amplified by the power stage amplifier circuit 111 is input to the contact on the input side of the frequency band selection switch 102. If the frequency band selection switch 102 selects one contact from a plurality of contacts on the output side, the high-frequency signal amplified by the power stage amplifier circuit 111 is output from the selected contact.

[0095] The multiple contacts on the output side of the band selection switch 102 are respectively connected to the transmission input nodes of the multiple duplexers 112 prepared for each frequency band. The high-frequency signal is input to the duplexer 112 connected to the contact on the output side selected by the band selection switch 102. The band selection switch 102 has a function of selecting a duplexer 112 from the multiple duplexers 112 prepared for each frequency band.

[0096] The antenna switch 104 has a plurality of contacts on the circuit side and two contacts on the antenna side. The plurality of contacts on the circuit side of the antenna switch 104 are respectively connected to the input / output shared nodes of the plurality of duplexers 112. The two contacts on the antenna side are respectively connected to the antenna terminals ANT1 and ANT2. The antennas are respectively connected to the antenna terminals ANT1 and ANT2.

[0097] The antenna switch 104 connects two antenna-side contacts to two contacts selected from a plurality of contacts on the circuit side. When communicating using one frequency band, the antenna switch 104 connects one contact on the circuit side to one contact on the antenna side. The high-frequency signal amplified by the power stage amplifier circuit 111 and passed through the duplexer 112 for the corresponding frequency band is transmitted from the antenna connected to the selected antenna-side contact.

[0098] The receiving frequency band selection switch 105 has 6 contacts on the input side. The 6 contacts on the input side of the frequency band selection switch 105 are respectively connected to the receiving output node of the duplexer 112. The contacts on the output side of the frequency band selection switch 105 are connected to the low noise amplifier 106. The reception signal that has passed through the duplexer 112 connected to the contacts on the input side selected by the frequency band selection switch 105 is input to the low noise amplifier 106.

[0099] The contact point on the circuit side of the output terminal selection switch 109 is connected to the output node of the low noise amplifier 106. The contacts on the three terminal sides of the output terminal selection switch 109 are respectively connected to the reception signal output terminals LNAOUT1, LNAOUT2, and LNAOUT3. The reception signal amplified by the low noise amplifier 106 is output from the reception signal output terminal selected by the output terminal selection switch 109.

[0100] Power supply voltages are applied from power supply terminals Vcc1 and Vcc2 to the driver stage amplifier circuit 110 and the power stage amplifier circuit 111, respectively. The power amplifier control circuit 107 is connected to the power supply terminal VIO1, the control signal terminal SDATA1, and the clock terminal SCLK1. The power amplifier control circuit 107 controls the driver stage amplifier circuit 110 and the power stage amplifier circuit 111 based on a digital control signal applied to the control signal terminal SDATA1.

[0101] The low noise amplifier control circuit 108 is connected to the power supply terminal VIO2, the control signal terminal SDATA2, and the clock terminal SCLK2. The low noise amplifier control circuit 108 controls the low noise amplifier 106 according to the digital control signal applied to the control signal terminal SDATA2.

[0102] The input switch 101, the transmission band selection switch 102, the antenna switch 104, the reception band selection switch 105, and the output terminal selection switch 109 are formed in the device layer 30 ( Figure 2 The main heat sources are the band selection switch 102 and the antenna switch 104 through which high-power high-frequency signals are transmitted.

[0103] Next, the excellent effects of the third embodiment will be described.

[0104] The high-frequency module provided in the third embodiment is equipped with the semiconductor device 10 provided in the first embodiment or the second embodiment. Therefore, the heat dissipation efficiency of the transistors constituting the transmission band selection switch 102 and the antenna switch 104, which are the main heat sources, is improved, and the temperature rise of the transistors can be suppressed. In addition, the degradation of the high-frequency characteristics of the transmission band selection switch 102 and the antenna switch 104 caused by parasitic capacitance is suppressed.

[0105] The heat generated by the transistors constituting the input switch 101, the low noise amplifier 106, and the output terminal selection switch 109, which do not pass the high-power high-frequency signal, is less than the heat generated by the transistors constituting the transmission frequency band selection switch 102 and the antenna switch 104. Therefore, the transistors constituting the input switch 101, the low noise amplifier 106, and the output terminal selection switch 109 do not necessarily need to have a contact with the bump 70 and the heat conducting member 85 ( Figure 4A ) but these transistors may also have overlapping portions with the bump 70 and the thermally conductive component 85.

[0106] The above-mentioned embodiments are illustrative, and of course, partial replacement or combination of the structures shown in different embodiments can be performed. The same effects of the same structures of multiple embodiments are not mentioned in sequence in each embodiment. In addition, the present invention is not limited to the above-mentioned embodiments. For example, it is obvious to those skilled in the art that various changes, improvements, combinations, etc. can be made.

[0107] Description of Reference Numerals

[0108] 10, 10A…semiconductor device; 20…insulating layer; 30…device layer; 31…transistor; 31C…channel region; 31D…drain region; 31G…gate electrode; 31S…source region; 31X…overlapping portion; 31Y…non-overlapping portion; 32D…drain contact region; 32S…source contact region; 33D…drain contact electrode; 33S…source contact electrode; 34…wiring; 34P…pad; 34T…uppermost wiring; 35…through hole; 37 peripheral metal layer; 39…element formation layer; 39I…element separation region; 40…minimum enclosing rectangle; 50… Support substrate; 60…insulating layer; 61…protective film; 70…bump; 80…mounting substrate; 81…solder pad; 85…heat-conducting component; 86…molding resin; 90…SOI substrate; 91…temporary support substrate; 101…input switch; 102…frequency band selection switch for transmission; 104…antenna switch; 105 frequency band selection switch for reception; 106…low noise amplifier; 107…power amplifier control circuit; 108…low noise amplifier control circuit; 109…output terminal selection switch; 110…driving stage amplifier circuit; 111…power stage amplifier circuit; 112…duplexer.

Claims

1. A semiconductor module comprising: Install the base plate; The semiconductor device is mounted on the mounting substrate in a flip-chip manner; molding resin to seal the semiconductor device; and an insulating heat-conductive member disposed on a surface of the semiconductor device facing the mounting substrate and having a heat conductivity higher than that of the molding resin, The semiconductor device comprises: a device layer, in which transistors are formed; a plurality of bumps disposed on a surface of the device layer facing the mounting substrate and connected to the mounting substrate; and an insulating layer disposed on a surface of the device layer opposite to a surface facing the mounting substrate, The transistor has a non-overlapping portion that does not overlap with any of the plurality of bumps when the mounting substrate is viewed from above, and the thermally conductive member is disposed continuously from a region overlapping with the non-overlapping portion to at least one of the plurality of bumps.

2. The semiconductor module according to claim 1, wherein: The semiconductor device further includes a support substrate made of a resin material, and the support substrate is disposed on a surface of the insulating layer that faces the side opposite to the device layer.

3. The semiconductor module according to claim 1 or 2, wherein: In a plan view of the device layer, the thermally conductive member is disposed over the entire region of the device layer except for a region where the plurality of bumps are disposed.

4. The semiconductor module according to any one of claims 1 to 3, wherein: The thermally conductive member extends from a surface of the semiconductor device facing the mounting substrate to the mounting substrate.

5. The semiconductor module according to any one of claims 1 to 4, wherein: The molding resin and the thermally conductive component contain a filler, and a filling rate of the filler in the thermally conductive component is higher than a filling rate of the filler in the molding resin.

6. The semiconductor module according to claim 1 or 2, wherein: The thermally conductive member is disposed continuously from a region overlapping with the non-overlapping portion to a bump among the plurality of bumps that does not overlap with the transistor.

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