Chip flatness testing method based on optical microscope
The chip planarity is calculated through the inclination and z-axis data of the optical microscope stage, which solves the problem of dirt on the chip surface and achieves a more accurate chip planarity test.
Patent Information
- Application Number
- CN202310813880.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-04
- Publication Date
- 2025-01-07
AI Technical Summary
In the existing chip planarity testing methods, scanning tests based on 3D profilers are susceptible to chip surface dirt, resulting in errors in plane calculation.
Using an optical microscope-based test method, by obtaining the inclination of the optical microscope stage and the z-axis data of the chip, the planarity parameters of the chip are calculated using the target analytical formula to avoid the influence of foreign matter on the chip surface.
It effectively improves the accuracy of chip planarity testing, avoids the impact of foreign matter on the chip surface on the test results, and improves the accuracy of planarity calculation.
Smart Images
Figure CN119268608A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip flatness testing, and more specifically, to a chip flatness testing method based on an optical microscope. Background Art
[0002] Currently, most chip flatness testing methods use 3D profilometer-based scanning tests and visual point scanning tests. These devices are mainly based on industrial vision technology to perform panoramic scanning or point scanning on chips. Although the scanning speed is fast, if the corresponding chip is dirty and causes the chip to bulge or dent, the parameter readings of the high and low points of the chip flatness will deviate from the true value of the chip's own flatness, thereby causing errors in the chip's flatness calculation.
[0003] Therefore, how to effectively test the chip flatness is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0004] In view of this, in order to solve the above problems, the present invention provides a chip flatness testing method based on an optical microscope, and the technical solution is as follows:
[0005] A chip flatness testing method based on an optical microscope, the chip flatness testing method comprising:
[0006] Get the inclination of the optical microscope stage;
[0007] Placing the chip on the stage of the optical microscope and testing the z-axis data of the chip, wherein the z-axis is parallel to the optical axis of the optical microscope;
[0008] The flatness parameter of the chip is obtained according to the inclination of the optical microscope stage and the z-axis data.
[0009] Preferably, in the above chip flatness testing method, obtaining the inclination of the optical microscope stage comprises:
[0010] The z-axis numerical value test of the marked points on the test board is performed on multiple dimensional directions of the optical microscope stage using a calibrated test board to obtain the inclination of the optical microscope stage.
[0011] Preferably, in the above chip flatness testing method, the test plate is placed in the central area of the optical microscope stage.
[0012] Preferably, in the above chip flatness testing method, the multiple dimensional directions of the optical microscope stage include:
[0013] The optical microscope stage has a horizontal direction, a vertical direction, a left diagonal direction and a right diagonal direction.
[0014] Preferably, in the above chip flatness testing method, the testing board has a plurality of marking points arranged in sequence.
[0015] Preferably, in the above chip flatness test method, obtaining the flatness parameter of the chip according to the inclination of the optical microscope stage and the z-axis data includes:
[0016] The flatness parameter of the chip is obtained using a target analytical expression; the target analytical expression is:
[0017]
[0018] Among them, Z 芯片 represents a planarity parameter of the chip;
[0019] △z represents the change in axial focusing within the chip size range;
[0020] k represents the linear flatness slope of the optical microscope stage;
[0021] L is the size of the chip.
[0022] Preferably, in the above chip flatness testing method, placing the chip on the optical microscope stage and testing the z-axis data of the chip includes:
[0023] The chip is placed on a glass slide, and the glass slide with the chip is placed on the stage of the optical microscope.
[0024] Preferably, in the above chip flatness testing method, placing the chip on the optical microscope stage and testing the z-axis data of the chip further comprises:
[0025] Multiple areas of the chip are tested to obtain z-axis data of the chip.
[0026] Preferably, in the above chip flatness testing method, the step of testing multiple regions of the chip to obtain z-axis data of the chip includes:
[0027] Select a point from each of the multiple areas of the chip and test the z-axis data of the point;
[0028] The z-axis data of multiple points obtained from the test are processed to obtain the change in axial focus within the chip size range.
[0029] Preferably, in the above chip flatness testing method, the plurality of regions of the chip include:
[0030] The upper left corner area, the lower left corner area, the upper right corner area and the lower right corner area of the chip.
[0031] Compared with the prior art, the present invention has the following beneficial effects:
[0032] The present invention provides a chip flatness test method based on an optical microscope, which comprises: obtaining the inclination of the optical microscope stage; placing a chip on the optical microscope stage, testing the z-axis data of the chip, wherein the z-axis is parallel to the optical axis direction of the optical microscope; and obtaining the flatness parameters of the chip according to the inclination of the optical microscope stage and the z-axis data. The chip flatness test method can effectively test the chip flatness based on an optical microscope, and its greatest advantage is that it can avoid foreign matter on the chip surface, thereby reading the parameters of the chip plane itself, obtaining the chip flatness value, and improving the chip flatness test effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.
[0034] Figure 1 A schematic diagram of a process flow of a chip flatness testing method based on an optical microscope provided in an embodiment of the present invention;
[0035] Figure 2 A schematic diagram of the structure of a calibrated test board provided in an embodiment of the present invention;
[0036] Figure 3 A schematic diagram of a model of an optical microscope stage provided by an embodiment of the present invention;
[0037] Figure 4 A method provided in an embodiment of the present invention is to Figure 2 The test plate is placed in the horizontal direction of the optical microscope stage to test the horizontal inclination of the optical microscope stage;
[0038] Figure 5 A method provided in an embodiment of the present invention is to Figure 2 The middle test plate is placed in the vertical direction of the optical microscope stage to test the vertical inclination of the optical microscope stage;
[0039] Figure 6A method provided in an embodiment of the present invention is to Figure 2 The middle test plate is placed at the left diagonal direction of the optical microscope stage to test the inclination of the optical microscope stage at the left diagonal direction;
[0040] Figure 7 A method provided in an embodiment of the present invention is to Figure 2 The middle test plate is placed at the right diagonal direction of the optical microscope stage to test the inclination of the optical microscope stage at the right diagonal direction;
[0041] Figure 8 A schematic diagram of a fitting curve for testing the inclination of an optical microscope stage using a test plate provided in an embodiment of the present invention;
[0042] Fig. 9 A schematic diagram of placing a chip on a glass slide provided in an embodiment of the present invention;
[0043] Fig.10 A cross-sectional view of a test model for constructing an optical microscope stage and placing a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0045] Based on the content recorded in the background technology, the existing chip flatness testing method mainly adopts visual scanning technology. If the chip surface is dirty, this will cause the scanning result to deviate from the actual value of the chip flatness. For example, the convex point of the chip will be read by the device as the highest point of the chip, and the concave point will be read by the device as the lowest point of the chip. The above results will affect the actual flatness of the chip.
[0046] Based on this, the present invention proposes a chip flatness testing method based on an optical microscope. The chip flatness testing method can effectively test the chip flatness. Its biggest advantage is that it can avoid foreign matter on the chip surface, thereby reading the parameters of the chip's own plane, obtaining the chip's flatness value, and improving the chip flatness testing effect.
[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0048] refer to Figure 1 , Figure 1A schematic flow chart of a chip flatness testing method based on an optical microscope provided in an embodiment of the present invention, the chip flatness testing method based on an optical microscope comprises:
[0049] S101: Obtain the inclination of the optical microscope stage.
[0050] Specifically, in this step, before obtaining the inclination of the optical microscope stage, the chip flatness testing method also includes: cleaning the surface of the optical microscope stage to avoid the influence of dirt on the surface of the optical microscope stage on the test results, thereby improving the final chip flatness test accuracy.
[0051] refer to Figure 2 , Figure 2 A schematic diagram of a calibration test board provided in an embodiment of the present invention, wherein the test board has a plurality of marking points arranged in sequence. Figure 2 In the description, a test board 1 having 8 marking points is taken as an example, and the 8 marking points are marked as 11, 12, 13, 14, 15, 16, 17, and 18 respectively.
[0052] refer to Figure 3 , Figure 3 A schematic diagram of a model of an optical microscope stage provided in an embodiment of the present invention, including but not limited to using a calibrated test board 1 to perform z-axis numerical tests of the marked points on the test board in multiple dimensional directions of the optical microscope stage 2 to obtain the inclination of the optical microscope stage 2. Optionally, the multiple dimensional directions of the optical microscope stage 2 include: the horizontal direction, the vertical direction, the left diagonal direction, and the right diagonal direction of the optical microscope stage 2.
[0053] That is, by Figure 2 The test board 1 shown is placed on Figure 3 By testing different dimensional directions on the optical microscope stage 2 shown in the figure, the inclinations in different dimensional directions on the optical microscope stage 2 can be obtained, and then the data can be analyzed and processed to obtain the inclination of the optical microscope stage 2. Specifically, the corresponding z-axis parameters can be obtained by focusing on the 8 marking points on the test plate through an optical microscope.
[0054] For further reference, Figure 4 , Figure 4 A method provided in an embodiment of the present invention is to Figure 2 The test board is placed on the horizontal direction of the optical microscope stage to test the horizontal inclination of the optical microscope stage. Figure 5 , Figure 5 A method provided in an embodiment of the present invention is to Figure 2The test plate is placed in the vertical direction of the optical microscope stage to test the vertical inclination of the optical microscope stage. Figure 6 , Figure 6 A method provided in an embodiment of the present invention is to Figure 2 The test plate is placed at the left diagonal direction of the optical microscope stage. Schematic diagram of testing the inclination of the optical microscope stage at the left diagonal direction, reference Figure 7 , Figure 7 A method provided in an embodiment of the present invention is to Figure 2 Schematic diagram of placing the test plate in the right diagonal direction of the optical microscope stage to test the inclination of the optical microscope stage in the right diagonal direction.
[0055] At the same time, in order to ensure the effectiveness of using the test board 1 to test the inclination of the optical microscope stage 2 in different dimensional directions, the test board 1 is placed in the central area of the optical microscope stage 2 to perform the inclination test during the test.
[0056] Among them, the fitted linear expression of the inclination of the optical microscope stage is:
[0057] Z 载物台 =kx+b
[0058] Wherein, k represents the slope value that can be represented in the horizontal direction, vertical direction, left diagonal direction and right diagonal direction of the optical microscope stage.
[0059] b represents the intercept of the inclination of the optical microscope stage when the variable x=0 of the horizontal movement of the optical microscope stage.
[0060] Z 载物台 Indicates the inclination of the optical microscope stage.
[0061] The following is a specific example for explanation:
[0062] In the process of using the test plate 1 to test the inclination of the optical microscope stage 2 in different dimensional directions, the 40X objective lens of the optical microscope is selected for focusing, the image acquisition channel is selected as the incident bright field channel of the optical microscope, and the camera type is selected as a black and white camera. The specific process is as follows:
[0063] First, before testing, the cleanliness of the surface of the optical microscope stage 2 is ensured, and then the test plate 1 is placed in the central area of the optical microscope stage 2 .
[0064] Afterwards, the optical microscope image acquisition channel turntable is rotated to a specified position, that is, the rotated channel is the incident bright field channel of the optical microscope.
[0065] After that, open the optical microscope software and select the start button of the incident bright field channel. At this time, the optical microscope stage 2 will perform the initialization operation. After the initialization operation is completed, the multiple marking points on the test plate 1 are focused one by one along the horizontal direction, vertical direction, left diagonal direction and right diagonal direction of the optical microscope stage 2, and the focal plane z-axis data is recorded. The specific data is shown in Table 1 below (Table 1 shows the inclination parameters of the optical microscope stage 2 in four dimensions), and the fitting curve is shown in Figure 8 As shown, Figure 8 A schematic diagram of a fitting curve for testing the inclination of an optical microscope stage using a test plate provided in an embodiment of the present invention.
[0066] Table 1
[0067]
[0068] Combining the data shown in Table 1 above and Figure 8 The inclination of the optical microscope stage 2 can be calculated from the fitting curve shown.
[0069] S102: placing the chip on the stage of the optical microscope, and testing the z-axis data of the chip, where the z-axis is parallel to the optical axis of the optical microscope.
[0070] Specifically, in this step, refer to Fig. 9 , Fig. 9 A schematic diagram of placing a chip on a glass slide provided in an embodiment of the present invention is shown in FIG. 1 , wherein the chip is placed on a glass slide 3 , and the glass slide 3 on which the chip is placed is placed on the optical microscope stage 2 . Fig. 9 The middle figure shows that four chips, namely chip 4, chip 5, chip 6 and chip 7, are placed on a glass slide 3.
[0071] Multiple areas of the chip are tested to obtain z-axis data of the chip.
[0072] Optionally, a point is selected from each of the multiple areas of the chip, and the z-axis data of the point is tested.
[0073] The z-axis data of multiple points obtained from the test are processed to obtain the change in axial focus within the chip size range.
[0074] The multiple regions of the chip include: an upper left corner region, a lower left corner region, an upper right corner region and a lower right corner region of the chip.
[0075] S103: Obtaining the flatness parameter of the chip according to the inclination of the optical microscope stage and the z-axis data.
[0076] Specifically, in this step, the flatness parameter of the chip is obtained according to the inclination of the optical microscope stage and the z-axis data, including: obtaining the flatness parameter of the chip by using a target analytical expression, wherein by establishing a cross-sectional view of the test module, according to the geometric relationship between the chip and the optical microscope stage, a target analytical expression based on the optical microscope test chip flatness can be finally derived, and the target analytical expression is:
[0077]
[0078] Among them, Z 芯片 represents the flatness parameter of the chip.
[0079] Δz represents the change in axial focus within the chip size range.
[0080] k represents the linear flatness slope of the optical microscope stage.
[0081] L is the size of the chip.
[0082] That is to say, in the embodiment of the present invention, according to the geometric relationship between the chip and the optical microscope stage, the target analytical formula for testing the flatness of the chip based on the optical microscope can be finally derived. Based on the target analytical formula, during the test, only the four chips on the slide 3 need to be tested using an optical microscope, wherein the four points of chip 4 are 41, 42, 43, and 44, the four points of chip 5 are 51, 52, 53, and 54, the four points of chip 6 are 61, 62, 63, and 64, and the four points of chip 7 are 71, 72, 73, and 74.
[0083] The chip is placed in the central area of the optical microscope stage 2 before the test. During the test, the upper left corner, lower left corner, upper right corner, and lower right corner of the chip are moved to the bottom of the optical microscope objective for focusing (for example, the upper left corner is selected as the reference point before the test). The chip focus point selects a point on the chip plane that is not dirty, and then the z-axis data is read out, that is, the four points of the chip are the points in the upper left corner area, lower left corner area, upper right corner area, and lower right corner area of the chip that are not dirty.
[0084] By testing the z-axis data of the above points and combining the z-axis data of the four points on each chip for data analysis and processing, the change △z of the axial focus within this chip size range can be obtained. Then, the flatness parameters of the chip under test can be solved by combining the target analytical expression and parameters such as the inclination of the optical microscope stage 2. In addition, dirty chip focusing is avoided during the test process, and the flatness parameters of the chip can be effectively obtained.
[0085] The chip flatness parameters on the glass slide (in μm) are shown in Table 2 below:
[0086] Table 2
[0087] ID Chip 4 Chip 5 Chip 6 Chip 7 1# 6 4 4 2 2# 2 5 6 2 3# 14 11 13 7 4# 6 10 6 3 5# 7 6 7 7 6# 17 17 11 12 7# 9 11 6 7 8# 4 3 3 5 9# 10 6 8 9
[0088] Table 2 selects 9 glass slides corresponding to the chip test, and the IDs corresponding to the 9 glass slides are 1#, 2#, 3#, 4#, 5#, 6#, 7#, 8# and 9#.
[0089] For further reference, Fig.10 , Fig.10 A cross-sectional view of a test model for constructing an optical microscope stage and placing a chip provided in an embodiment of the present invention. In order to illustrate the model more vividly, the optical microscope stage 2 is placed at a certain tilt angle, and the chip 100 to be tested is placed on the optical microscope stage 2 at a certain tilt angle. Through geometric relationships, the flatness parameters of the chip can be solved. Since the model has a geometric mapping relationship, the final calculation formula only has a difference in signs. We can ensure the consistency of the table by finding the absolute value.
[0090] That is to say, an embodiment of the present invention provides a chip flatness testing method based on an optical microscope. By testing the inclination of the optical microscope stage from four dimensional directions through a test plate, the position of the optical microscope stage in space can be displayed. By constructing a model of the spatial position between the optical microscope stage and the chip being tested, a target analytical formula for solving the chip flatness is derived from the cross-sectional view of the model. Through the target analytical formula, the flatness parameters of the chip placed on the optical microscope stage with error can be solved.
[0091] In general, the chip flatness test method based on optical microscopy can avoid the experimental error caused by the inclination of the optical microscope stage, and can avoid the experimental influence caused by the dirt on the surface of the tested chip.
[0092] It should be noted that the flatness test method based on an optical microscope can also be used to test the flatness of other structural parts, and can effectively eliminate the influence of the error caused by the inclination of the optical microscope stage. Secondly, the phenomenon of dirt on the surface of the test object can be effectively avoided, thereby effectively testing the flatness value of the object.
[0093] The above is a detailed introduction to a chip flatness testing method based on an optical microscope provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technicians in this field, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.
[0094] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0095] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.
[0096] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A chip flatness testing method based on an optical microscope, characterized in that: The chip flatness testing method comprises: Get the inclination of the optical microscope stage; Placing the chip on the stage of the optical microscope and testing the z-axis data of the chip, wherein the z-axis is parallel to the optical axis of the optical microscope; The flatness parameter of the chip is obtained according to the inclination of the optical microscope stage and the z-axis data.
2. The chip flatness testing method according to claim 1, characterized in that: The step of obtaining the inclination of the optical microscope stage comprises: The z-axis numerical value test of the marked points on the test board is performed on multiple dimensional directions of the optical microscope stage using a calibrated test board to obtain the inclination of the optical microscope stage.
3. The chip flatness testing method according to claim 2, characterized in that: The test plate is placed in the central area of the optical microscope stage.
4. The chip flatness testing method according to claim 2, characterized in that: The multiple dimensional directions of the optical microscope stage include: The optical microscope stage has a horizontal direction, a vertical direction, a left diagonal direction and a right diagonal direction.
5. The chip flatness testing method according to claim 2, characterized in that: The test plate has a plurality of marking points arranged in sequence.
6. The chip flatness testing method according to claim 1, characterized in that: The step of obtaining the flatness parameter of the chip according to the inclination of the optical microscope stage and the z-axis data comprises: The flatness parameter of the chip is obtained using a target analytical expression; the target analytical expression is: Among them, Z 芯片 represents a planarity parameter of the chip; △z represents the change in axial focusing within the chip size range; k represents the linear flatness slope of the optical microscope stage; L is the size of the chip.
7. The chip flatness testing method according to claim 1, characterized in that: Placing the chip on the optical microscope stage and testing the z-axis data of the chip comprises: The chip is placed on a glass slide, and the glass slide with the chip is placed on the stage of the optical microscope.
8. The chip flatness testing method according to claim 7, characterized in that: Placing the chip on the optical microscope stage and testing the z-axis data of the chip further comprises: Multiple areas of the chip are tested to obtain z-axis data of the chip.
9. The chip flatness testing method according to claim 8, characterized in that: The testing of the plurality of regions of the chip to obtain z-axis data of the chip includes: Select a point from each of the multiple areas of the chip and test the z-axis data of the point; The z-axis data of multiple points obtained from the test are processed to obtain the change in axial focus within the chip size range.
10. The chip flatness testing method according to claim 9, characterized in that: The multiple areas of the chip include: The upper left corner area, the lower left corner area, the upper right corner area and the lower right corner area of the chip.