Curvature-compensated high-PSRR low-noise band-gap reference circuit and control method thereof

Abstract

The invention belongs to an integrated circuit chip technology. The invention discloses a high-PSRR low-noise band-gap reference circuit with a curvature compensation technology. The high-PSRR low-noise band-gap reference circuit comprises a band-gap core circuit, a compensation filter circuit and a starting circuit which are connected through fixed nodes. And the requirements of various high-precision, high-stability and low-power-consumption applications (such as precision measuring instruments or precision analog circuits) can be met. The circuit comprises a starting circuit, a core circuit and a compensation filter circuit. A nonlinear compensation circuit is adopted to reduce the temperature drift coefficient of the band-gap reference; and the PSRR of the band-gap reference is improved by adopting a self-adaptive dynamic loop structure. Compared with a traditional band gap structure, the band gap structure has higher power supply suppression capability and output precision and lower noise and temperature coefficients.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a curvature-compensated high PSRR (Power supply ripple rejection ratio) low-noise bandgap reference circuit and a control method thereof. Background Art

[0002] In modern analog and mixed-signal integrated circuit design, bandgap reference circuit is a crucial module, which is widely used in power management, analog-to-digital converter (ADC), digital-to-analog converter (DAC) and sensor interface systems. Its main function is to provide a stable reference voltage to ensure the performance stability and accuracy of the system under various working conditions.

[0003] Traditional bandgap reference circuits such as Figure 1 As shown in the figure, the basic principle is to use the op amp OPA to clamp the voltages at points A and B to be equal, and the difference between the base-emitter voltages of the PNP transistor Q1 and the PNP transistor Q2 generates a positive temperature coefficient voltage ΔV BE , a positive temperature coefficient current (I PTAT ), the current is mirrored to the branch where the resistor R2 is located to generate a voltage with a positive temperature coefficient, and the base-emitter (BE) junction voltage V BE3 It has a negative temperature characteristic. The two are superimposed to generate a reference voltage V after first-order temperature compensation. REF , Where V T is the thermal voltage, and N is the emitter area ratio of the PNP transistor Q1 and the PNP transistor Q2.

[0004] For the circuit structure of Figure 1, the introduction of the operational amplifier improves the accuracy to a certain extent, but the operational amplifier itself will also introduce power supply ripple. In addition, the operational amplifier has an offset voltage, resulting in the PSRR capability of the structure is still limited. In addition, the transistor base-emitter (BE) junction voltage V BE The presence of temperature-related high-order nonlinear components will still cause the reference voltage to have a large temperature drift coefficient, which cannot meet the requirements of modern high-precision circuits. Therefore, in response to the above problems, this paper designs a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation based on the above circuit. Summary of the invention

[0005] In order to solve the technical problems existing in the above circuit, a high-order curvature compensated high PSRR low noise bandgap reference circuit is proposed to further improve PSRR and reduce temperature coefficient and noise. The detailed technical solution of the present invention is as follows:

[0006] A curvature-compensated high-PSRR low-noise bandgap reference circuit, the circuit comprising: a bandgap core circuit, a compensation filter circuit, and a startup circuit connected via a fixed node;

[0007] The bandgap core circuit is used to generate a positive temperature coefficient current I PTAT and the first-order reference voltage V REF1 ;

[0008] The compensation filter circuit is used to generate a first-order reference voltage V REF1 and positive temperature coefficient current I PTAT Compensation is performed to generate a positive temperature coefficient compensation current and a negative temperature coefficient current of the compensation filter circuit. The positive temperature coefficient compensation current and the negative temperature coefficient current of the compensation filter circuit interact to generate a compensation current. The compensation current has an influence on the first-order reference voltage V REF1 The compensation current is mirrored to compensate the first-order reference voltage V REF1 The higher-order temperature term in the compensation first-order reference voltage V REF1 The voltage signal is low-pass filtered to obtain a low temperature coefficient reference voltage V REF2 ;

[0009] The startup circuit is used to provide a startup current for the bandgap core circuit, realize the soft start of the bandgap reference circuit, ensure that the circuit can start correctly from zero voltage and reach a stable state, and after the whole circuit is working normally, the low temperature coefficient reference voltage V REF2 The voltage signal controls the startup circuit to shut down, thereby shutting down part of the large current in the startup circuit and reducing the overall power consumption.

[0010] Preferably, the bandgap core circuit comprises: PMOS tube MP1, PMOS tube MP2, PMOS tube MP3; NMOS tube MN1, NMOS tube MN2; PNP triode Q1, PNP triode Q2, operational amplifier OPA; wherein the source of PMOS tube MP1, the source of PMOS tube MP2, and the source of PMOS tube MP3 are connected to the power supply VDD;

[0011] The compensation filter circuit includes: PMOS tube MP4, PMOS tube MP5, PMOS tube MP6; NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, NMOS tube MC2; PNP transistor Q3;

[0012] The startup circuit includes: PMOS tube MS1, PMOS tube MS2, PMOS tube MS3, PMOS tube MS4, PMOS tube MS6, PMOS tube MS7, PMOS tube MS8, PMOS tube MS9; NMOS tube MS5, NMOS tube MS10;

[0013] The gate and drain of the PMOS tube MP1 in the bandgap core circuit are connected, the gate of the PMOS tube MP1, the gate of the PMOS tube MP2, the gate of the PMOS tube MP3, and the gate of the PMOS tube MP4 in the compensation filter circuit are connected; the drain of the NMOS tube MN1 and the drain of the PMOS tube MP1 are connected, the gate of the NMOS tube MN1 and the gate of the NMOS tube MS10 in the startup circuit are connected, and the gate and drain of the NMOS tube MS10 are connected; the source of the NMOS tube MN1 and the drain of the NMOS tube MN2 are connected; the output of the operational amplifier OPA is connected to the NMOS tube MN1. The gate of the MOS tube MN2 is connected; the drain of the PMOS tube MP2 is connected to the internal bias current source of the operational amplifier OPA; the drain of the PMOS tube MP3 is connected to the reverse input terminal X of the operational amplifier OPA, and the non-inverting input terminal Y of the operational amplifier OPA is connected to the emitter of the PNP transistor Q2; the base and collector of the PNP transistor Q1 are connected, the base of the PNP transistor Q1, the base of the PNP transistor Q2, and the base of the PNP transistor Q3 are connected, and the collector of the PNP transistor Q1, the collector of the PNP transistor Q2, and the collector of the PNP transistor Q3 are grounded;

[0014] In the compensation filter circuit, the source of the PMOS tube MP4, the source of the PMOS tube MP5, and the source of the PMOS tube MP6 are connected to the positive electrode of the power supply; the gate and drain of the NMOS tube MN3 are connected, the drain of the PMOS tube MP4 is connected to the drain of the NMOS tube MN3, the gate of the NMOS tube MN3, the gate of the NMOS tube MN4, and the gate of the NMOS tube MN5 are connected; the source of the NMOS tube MN3 and the emitter of the PNP transistor Q3 are connected; the drain of the NMOS tube MN4, the drain of the NMOS tube MN5, and the drain of the PMOS tube MP5 are connected, the drain and the gate of the PMOS tube MP5 are connected, and the gate of the PMOS tube MP5 and the gate of the PMOS tube MP6 are connected; the collector of the PNP transistor Q3, the source of the NMOS tube MN5, and the drain and the source of the NMOS tube MC2 are connected to the ground;

[0015] In the startup circuit, the source of PMOS tube MS1, the source of PMOS tube MS2, the source of PMOS tube MS3, the source of PMOS tube MS4, the source of PMOS tube MS6, the source of PMOS tube MS7, the source of PMOS tube MS8, and the source of PMOS tube MS9 are connected to the positive electrode of the power supply; the gate and drain of PMOS tube MS1 are connected, the gate of PMOS tube MS1, the drain of PMOS tube MS6, and the gate of PMOS tube MS2 are connected, the drain of PMOS tube MS1, the gate of PMOS tube MS7, the gate of PMOS tube MS8, the gate of PMOS tube MS9, and the drain of PMOS tube MS4 are connected; the drain of PMOS tube MS2, the drain of PMOS tube MS3, and the drain of NMOS tube MS5 are connected; the gate and drain of NMOS tube MS10 are connected, and the gate of NMOS tube MS10 and the gate of NMOS tube MN1 are connected; the source of NMOS tube MS5 is grounded.

[0016] Preferably, the bandgap core circuit further includes: a resistor R1, a resistor R2, a resistor R3, and a resistor R11; two ends of the resistor R1 are respectively connected to the drain of the PMOS tube MP3 and the negative electrode of the operational amplifier OPA, two ends of the resistor R2 are respectively connected to the drain of the PMOS tube MP3 and the positive electrode of the operational amplifier OPA, two ends of the resistor R3 are respectively connected to the negative electrode of the operational amplifier OPA and the emitter of the PNP transistor Q1, and the resistor R11 is connected to the source of the NMOS tube MN2 and then grounded;

[0017] The compensation filter circuit also includes: a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a capacitor C1; the resistor R4 is connected to the source of the NMOS tube MN4 and then grounded; one end of the resistor R5 is connected to the drain of the PMOS tube MP6, and the other end of the resistor R5 is connected to one end of the resistor R6, and one end of the resistor R6 is connected to one end of the resistor R7 and one end of the resistor R8; the other end of the resistor R6 is connected to the output first-order reference voltage V of the core circuit REF1 The other end of the resistor R7 is grounded; the other end of the resistor R8 is connected to the gate of the NMOS tube capacitor MC2, and the capacitor C1 is connected in parallel to the NMOS tube capacitor MC2;

[0018] The startup circuit also includes: a resistor R9, a resistor R10, an inverter INV, and a Schmitt trigger SMT; the two ends of the resistor R9 are respectively connected to the drain of the PMOS tube MS4 and the drain of the NMOS tube MS10, one end of the resistor R10 is connected to the source of the NMOS tube MS10, and the other end of the resistor R10 is grounded; the inverter INV output is connected in series with the Schmitt trigger SMT input, the Schmitt trigger SMT output is connected to the gate of the PMOS tube MS6, and the inverter INV input is connected to the drain of the NMOS tube MS5.

[0019] Preferably, the PMOS tube MP1, PMOS tube MP2, and PMOS tube MP3 form a first current mirror; the first current mirror provides bias for the PMOS tube MP4 in the compensation filter circuit and the PMOS tube MS3 and PMOS tube MS4 in the startup circuit.

[0020] Preferably, the PNP transistor Q1, the PNP transistor Q2, and the PNP transistor Q3 form a second current mirror, and the second current mirror provides a bias for the PNP transistor Q3 in the compensation filter circuit.

[0021] Preferably, the PMOS tube MS1 and the PMOS tube MS2 form a fifth current mirror; the NMOS tube MN1 and the NMOS tube MS10 form a sixth current mirror; the sixth current mirror provides a bias for the NMOS tube MN1 in the core circuit.

[0022] The operational amplifier OPA in the bandgap core circuit has a high gain characteristic, so the in-phase and inverting input terminals have the same potential, that is, the voltage values ​​at point X and point Y are the same. The area ratio of the two branch PNP transistors Q1 and PNP transistor Q2 is N:1, and the current ratio flowing through the two branches is M:1. The voltage difference ΔV between the two PNP transistors is BE =V BE2 -V BE1 =V T lnMN,ΔV BE The positive temperature coefficient voltage formed by the PNP transistors Q1 and Q2 forms a positive temperature coefficient current I in the branch where the resistors R1 and R3 are located. PTAT , The PNP transistor Q1 itself forms a negative temperature coefficient voltage V BE1 They are superimposed in the branch to obtain a first-order reference voltage V that is insensitive to temperature. REF1 ,

[0023] Preferably, the core circuit controls and distributes the respective width-to-length ratios of the PMOS tubes MP3, PMOS tubes MP2, and PMOS tubes MP1 in the first current mirror, thereby adjusting the current of the loop formed by the first current mirror and the operational amplifier OPA, thereby achieving control of the operating current, and regulating and reducing the overall power consumption under the premise of meeting the performance requirements of the bandgap reference circuit.

[0024] Preferably, the resistor R8, the capacitor C1, and the NMOS transistor MC2 form a first-order RC low-pass filter, and the RC low-pass filter is used for the first-order reference voltage V REF1 The voltage signal is low-pass filtered to obtain a low temperature coefficient reference voltage VREF2 .

[0025] The first-order RC low-pass filter can reduce the output noise contribution and improve the PSRR in the high-frequency range. The reason why adding a low-pass filter can further improve the PSRR in the mid-high frequency range is that it introduces a pole at this frequency, which will additionally attenuate the noise in the high-frequency range, and the PSRR performance is improved in the mid-high frequency range, thereby ensuring a high PSRR in the entire operating frequency range.

[0026] The currents in several branches of the compensation filter circuit are from the mirror current provided by the first current mirror where the PMOS tube MP1 in the core circuit is located, and have a characteristic of being proportional to the absolute temperature of Kelvin (PTAT). Then the current in the branch where the NMOS tube MN3 is located is a PTAT current, and the base-emitter (BE) junction voltage of the PNP transistor Q3 has a negative temperature characteristic. After being mirrored by the third current mirror composed of the NMOS tubes MN3, MN4, and MN5, a current inversely proportional to the absolute temperature of Kelvin (CTAT) is generated under the action of the resistor R3. Similarly, after mirroring, a positive temperature coefficient compensation current is generated in the branch where the NMOS tube MN5 is located; that is, there is a CTAT current in the branch where the NMOS tube MN4 is located, and there is a PTAT compensation current in the branch where the NMOS tube MN5 is located; the temperature characteristics of the two currents interact to generate a compensation current, which is applied to the first-order reference voltage V REF1 Compensation is performed, and the compensation current is I COMP , Where x represents the ratio of the PTAT compensation current of the NMOS tube MN5 branch to the PTAT current of the PNP transistor Q1 branch, which is x:1. The compensated low temperature coefficient reference voltage V REF2 , Where y represents the ratio of the current proportional to absolute temperature (PTAT) flowing into the resistor R7 branch to the current of the PNP transistor Q1 branch, which is y:1. The compensated low temperature coefficient reference voltage V REF2 The high-order temperature terms can cancel each other out, and the temperature drift curve can be fitted with a high-order polynomial function to obtain more accurate temperature compensation.

[0027] The startup circuit injects quantized current into the low impedance node in the circuit or extracts quantized current from the low impedance node. The designed startup circuit can not only make the circuit enter the normal working state, but also charge the fixed node in advance to speed up the establishment of the normal state of the circuit. The startup circuit uses a large current transistor at startup, and switches to a small current transistor after the circuit works normally, further reducing power consumption while satisfying the normal working of the circuit.

[0028] The advantages and beneficial effects of the present invention are as follows:

[0029] The present invention provides a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation. Under the clamping action of the operational amplifier OPA, the base-emitter voltage difference ΔV between the PNP transistor Q1 and the PNP transistor Q2 is BE A positive temperature coefficient current I is generated in the branch where the resistor R1 is located. PTAT Provide bias for other circuits, and generate negative temperature coefficient voltage V with PNP transistor Q2 under the action of resistor R3. BE2 Forming the first-order reference voltage V REF1 The current of the compensation filter circuit comes from the mirror current of the core circuit, which has a PTAT characteristic. The branch where the NMOS tube MN3 is located is a PTAT current. The base-emitter (BE) junction voltage of the PNP transistor Q3 has a negative temperature characteristic. After being mirrored by the third current mirror composed of the NMOS tubes MN3, MN4, and MN5, a CTAT current inversely proportional to the Kelvin absolute temperature is generated under the action of the resistor R3. Similarly, after mirroring, a positive temperature coefficient compensation current is generated in the branch where the NMOS tube MN5 is located, that is, there is a CTAT current in the branch where the NMOS tube MN4 is located, and there is a PTAT compensation current in the branch where the NMOS tube MN5 is located; the temperature characteristics of the two currents interact to generate a compensation current, which is compensated for the first-order reference voltage after mirror adjustment, and has higher power supply suppression capability and output accuracy, and has lower noise and temperature coefficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a bandgap reference voltage source of background technology;

[0031] Figure 2 A schematic diagram of a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation according to the present invention;

[0032] Figure 3 It is a schematic diagram of the operational amplifier OPA of the present invention.

[0033] Figure 4 This is a simulation diagram of the output reference temperature characteristics of a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation according to the present invention.

[0034] Figure 5 A PSRR simulation diagram of a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation according to the present invention;

[0035] Figure 6 The transient startup simulation curve of a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation according to the present invention. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are part of the embodiments of the present invention.

[0037] In the description of the present invention, the directions or positional relationships indicated by the terms "up", "down", "left", "right", etc. are based on the directions or positional relationships shown in the drawings and are only for the convenience of describing the present invention and simplifying the description.

[0038] like Figure 2-5 As shown, the present invention proposes a control method for a curvature-compensated high-PSRR low-noise bandgap reference circuit. When the startup circuit 3 is started, the PMOS (Positive Channel Metal Oxide Semiconductor) tube MS1 is first turned on, and then the PMOS tubes MS7, MS8 and MS9 begin to inject charges into the nodes of the bandgap core circuit 1, so that the bandgap core circuit 1 escapes from the zero-output steady state;

[0039] The low temperature coefficient reference voltage V REF2 During the establishment process, PMOS tubes MS1 and MS2 replace PMOS tubes MS3 and MS4 to provide current for the startup circuit 3; the fifth current mirror provides bias current for the operational amplifier OPA until the low temperature coefficient reference voltage V REF2 After the establishment is completed, the NMOS (Negative Channel Metal Oxide Semiconductor) tube MS5 is controlled to be turned on, and a low level is input to the inverter INV. After passing through the Schmitt trigger SMT, the PMOS tube MS6 is slowly turned on, and the gate voltages of the PMOS tubes MS1 and MS2 are gradually increased. The PMOS tubes MS1, MS2, MS7, MS8 and MS9 are controlled to be turned off, and the PMOS tubes MS3, MS4 and MP2 continue to supply power to the startup circuit 3, and the startup circuit 3 is started; the bandgap core circuit 1 and the compensation filter circuit 2 enter the working state, and the entire bandgap circuit works to provide the required bias current and output the low temperature coefficient reference voltage V REF2 .

[0040] like Figure 2 The operational amplifier OPA designed in the present invention has a high gain characteristic, so the in-phase and inverting input terminals have the same potential, that is, the voltage values ​​of point X and point Y are the same. The emitter area ratio of the PNP transistor Q1 and the emitter area ratio of the PNP transistor Q2 is N:1, and the current ratio of the two branches where the PNP transistor Q1 and the PNP transistor Q2 are located is M:1. The positive temperature coefficient current I PTAT It can be expressed as:

[0041]

[0042] In the formula, I PTAT is the positive temperature coefficient current, V BE2 is the base-emitter voltage of the corresponding PNP transistor Q2; V BE1 is the base-emitter voltage of the corresponding PNP transistor Q1; R1 is the resistance value of the resistor R1; R3 is the resistance value of the resistor R3; V T is the thermal voltage; PNP transistor Q1, PNP transistor Q2 and resistor R3 form a positive temperature coefficient voltage, and PNP transistor Q1 itself forms a negative temperature coefficient voltage V BE1 The positive temperature coefficient voltage and the negative temperature coefficient voltage are superimposed in the branch to obtain a first-order reference voltage V that is insensitive to temperature. REF1 .

[0043]

[0044] Where V REF1 is the first-order reference voltage; the current in the compensation filter circuit 2 comes from the mirror current in the bandgap core circuit 1, and has a PTAT characteristic. Then the branch where the NMOS tube MN3 is located is a PTAT current, and the base-emitter (BE) junction voltage of the PNP transistor Q3 has a negative temperature characteristic, and its negative temperature coefficient voltage V BE3 After being mirrored by the third current mirror formed by NMOS tubes MN3, MN4 and MN5, a CTAT current inversely proportional to the Kelvin absolute temperature is generated under the action of resistor R3, and a positive temperature coefficient compensation current is generated in NMOS tube MN5, that is, a CTAT current exists in the branch where NMOS tube MN4 is located; a PTAT compensation current exists in the branch where NMOS tube MN5 is located, and the temperature characteristics of the two currents interact to generate a compensation current, which is applied to the first-order reference voltage V REF1 The PTAT compensation current of the branch where the NMOS tube MN5 is located and the CTAT current temperature characteristics of the branch where the NMOS tube MN4 is located interact to generate a compensation current. The compensation current is mirrored to the first-order reference voltage V by the fourth current mirror composed of the PMOS tube MP5 and the PMOS tube MP6. REF1Compensation is performed, and the compensation current I COMP for:

[0045]

[0046] In the formula, I COMP is the compensation current; x indicates that the ratio of the PTAT compensation current of the NMOS tube MN5 branch to the PTAT current of the PNP transistor Q1 branch is x:1; V BE3 is the base-emitter voltage of the PNP transistor Q3. The compensation current is adjusted by the mirror image to the first-order reference voltage V REF1 The high-order temperature term in is compensated, and the compensated low temperature coefficient reference voltage V REF2 for:

[0047]

[0048] Where V REF2 is a low temperature coefficient reference voltage; y represents the ratio of the PTAT current portion flowing into the resistor R7 branch to the PNP transistor Q1 branch current, which is y:1; R4 is the resistance value of the resistor R4; R7 is the resistance value of the resistor R7.

[0049] It is worth pointing out that the structure of the present invention can adjust the output low temperature coefficient reference voltage V through the resistor. REF2 The output voltage value can meet more usage scenarios. It is only necessary to adjust the parameters of the two branches related to the compensation current to make the low temperature coefficient reference voltage V REF2 It is sufficient to satisfy the low temperature characteristics. Low temperature coefficient reference voltage V REF2 The temperature characteristics can be expressed as follows:

[0050]

[0051] Where V REF2 (T) is the low temperature coefficient reference voltage V REF2 Temperature characteristics; y represents the ratio of the PTAT current flowing into the resistor R7 branch to the PNP transistor Q1 branch current, which is y:1; V T is the thermal voltage; V G is the bandgap voltage at a fixed temperature; T represents the absolute temperature; T0 represents the constant temperature; η represents the constant related to the temperature characteristic of silicon mobility; a is the constant related to the temperature characteristic of collector current; the low temperature coefficient reference voltage V can be calculated by equation (5): REF2 The temperature characteristics are described as follows:

[0052] V REF2 (T)=AV BE +BT+Cf(T) (6)

[0053] In the formula, T and f(T) represent the zero-order, first-order and higher-order temperature terms respectively; A, B and C represent the temperature term coefficients after compensation respectively. It can be seen from formula (6) that B and C control the first-order and higher-order nonlinear terms. This high-order polynomial function can fit the temperature drift curve to obtain more accurate temperature compensation. Therefore, the polynomial coefficients are appropriately adjusted so that the relevant temperature terms are almost zero, thereby obtaining a low temperature drift coefficient voltage, which is then output after low-pass filtering.

[0054] Figure 3 The operational amplifier structure diagram of a high-order curvature compensated high PSRR low-noise bandgap reference circuit of the present invention is provided. Its basic structure is a folded common source and common gate amplifier, which has the following advantages: it can provide a higher gain, which is very important for the accuracy of the bandgap reference circuit. The high gain helps to reduce the error of the amplifier, thereby improving the accuracy of the bandgap voltage; a wider output swing. Compared with the traditional common source amplifier, the folded common source and common gate amplifier can achieve a wider output swing, which is particularly important under low power supply voltage. It can work in a larger voltage range, thereby improving the adaptability and performance of the circuit; low output impedance, which helps the bandgap circuit to maintain a stable output voltage under different load conditions, and can improve the driving ability and load regulation ability of the circuit; good PSRR, the folded common source and common gate structure has a good power supply rejection ratio, which means that it has a good suppression ability for power supply noise and power supply voltage changes, which is an important prerequisite for the bandgap reference circuit to achieve high PSRR, and is very critical for the stability and reliability of the bandgap reference circuit. On this basis, a source negative feedback structure is added to further reduce the noise contribution of the bandgap reference circuit, and the source negative feedback resistor can also improve the linearity of the amplifier. By introducing negative feedback, the gain variation of the amplifier becomes smoother, thereby reducing nonlinear distortion, which has a positive impact on the accuracy and stability of the bandgap reference circuit.

[0055] Figure 4 This is a temperature characteristic simulation curve of a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation according to the present invention, wherein the abscissa is the temperature TEMP and the ordinate is the low temperature coefficient reference voltage V of the bandgap reference. REF2 The simulation results show that within the temperature range of -40℃~125℃, its low temperature coefficient reference voltage V REF2 The temperature coefficient is 3.053ppm / ℃, and the temperature characteristics of the band gap meet the low temperature coefficient requirements.

[0056] Figure 5The PSRR simulation curve of a high-order curvature compensated high-PSRR low-noise bandgap reference circuit of the present invention shows the influence of the power supply voltage change frequency on the output reference voltage. The horizontal axis is the frequency Freq, and the vertical axis is the PSRR of the bandgap reference. The simulation results show that the circuit PSRR is -123.5dB in the low frequency range and -45.5dB in the high frequency range, achieving a high PSRR in a wide bandwidth range.

[0057] Figure 6 The transient startup simulation curve of a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation of the present invention is shown in the figure, wherein the horizontal axis is the time TIME and the vertical axis is the voltage value of the bandgap reference. The simulation results show that the startup time of the bandgap reference circuit 1 from power-on to normal operation is 14us. During the establishment process, as the input voltage increases, the slope of the output voltage also increases. It can be seen from the figure that the startup circuit 3 works normally, the bandgap output reference voltage is stable at the design value, and the soft start of the bandgap is achieved.

[0058] In the above embodiment of the present invention, a high-order curvature compensation high PSRR low noise bandgap reference circuit includes a core circuit: generating a positive temperature coefficient current I PTAT and the first-order reference voltage V REF1 ; Compensation filter circuit: The first-order reference voltage V generated by the core circuit REF1 and I PTAT To compensate, the PNP transistor Q3 has a negative temperature characteristic, and its negative temperature coefficient voltage V BE3 After being mirrored by the third current mirror formed by the NMOS tubes MN3 and MN4, a CTAT current is generated under the action of the resistor R4, that is, there is a CTAT current in the branch where the NMOS tube MN4 is located, and the PTAT current of the branch where the NMOS tube MN3 is located and the CTAT current temperature characteristics of the branch where the NMOS tube MN4 is located interact to generate a compensation current, which is used to adjust the first-order reference voltage V REF1 To compensate, the PNP transistor Q3 is used to CTAT It has a high-order temperature term, which can compensate the first-order reference voltage V after mirroring REF1 The high-order temperature term in the compensation is used to achieve the compensation effect. After compensation, the low temperature coefficient reference voltage V is obtained through low-pass filtering. REF2 ; Startup circuit: used to provide startup current for the bandgap core circuit 1, realize soft start of the bandgap reference circuit 1, and ensure that the circuit can start correctly from zero voltage and reach a stable state.

[0059] Those skilled in the art should know that:

[0060] The traditional bandgap reference circuit introduces an operational amplifier to improve the accuracy to a certain extent, but the operational amplifier itself will also introduce power supply ripple. In addition, the operational amplifier has an offset voltage, which leads to the limited PSRR capability of the structure. It also does not take into account the influence of noise factors and cannot be used in systems that are more sensitive to noise. In addition, the transistor base-emitter (BE) junction voltage V BE The presence of temperature-related high-order nonlinear components will still cause the reference voltage to have a large temperature drift coefficient, which cannot meet the needs of modern high-stability and high-precision circuits. Therefore, in response to the above problems, this paper designs a high-PSRR low-noise bandgap reference circuit with high-order curvature compensation based on the above circuit.

[0061] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0062] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0063] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A curvature compensated high PSRR low noise bandgap reference circuit, characterized in that: The circuit comprises: a bandgap core circuit (1), a compensation filter circuit (2), and a start-up circuit (3) connected via a fixed node; The bandgap core circuit (1) is used to generate a positive temperature coefficient current I PTAT and the first-order reference voltage V REF1 ; The compensation filter circuit (2) is used to generate a first-order reference voltage V generated by the bandgap core circuit (1). REF1 and positive temperature coefficient current I PTAT Compensation is performed to generate a positive temperature coefficient compensation current and a negative temperature coefficient current of the compensation filter circuit (2), wherein the positive temperature coefficient compensation current and the negative temperature coefficient current of the compensation filter circuit (2) interact to generate a compensation current, and the compensation current has an influence on the first-order reference voltage V REF1 The compensation current is mirrored to compensate the first-order reference voltage V REF1 The higher-order temperature term in the compensation first-order reference voltage V REF1 The voltage signal is low-pass filtered to obtain a low temperature coefficient reference voltage V REF2 ; The startup circuit (3) is used to provide a startup current for the bandgap core circuit (1), and the low temperature coefficient reference voltage V REF The voltage signal controls the start-up circuit (3) to close.

2. The circuit according to claim 1, characterized in that The bandgap core circuit (1) comprises: a PMOS tube MP1, a PMOS tube MP2, and a PMOS tube MP3; an NMOS tube MN1, and an NMOS tube MN2; a PNP transistor Q1, a PNP transistor Q2, and an operational amplifier OPA; wherein the source of the PMOS tube MP1, the source of the PMOS tube MP2, and the source of the PMOS tube MP3 are connected to a power supply VDD; The compensation filter circuit (2) comprises: PMOS tube MP4, PMOS tube MP5, PMOS tube MP6; NMOS tube MN3, NMOS tube MN4, NMOS tube MN5, NMOS tube MC2; PNP transistor Q3; The startup circuit (3) comprises: a PMOS tube MS1, a PMOS tube MS2, a PMOS tube MS3, a PMOS tube MS4, a PMOS tube MS6, a PMOS tube MS7, a PMOS tube MS8, a PMOS tube MS9; an NMOS tube MS5, an NMOS tube MS10; The gate and drain of the PMOS tube MP1 in the bandgap core circuit (1) are connected; the gate of the PMOS tube MP1, the gate of the PMOS tube MP2, the gate of the PMOS tube MP3, and the gate of the PMOS tube MP4 in the compensation filter circuit (2) are connected; the drain of the NMOS tube MN1 and the drain of the PMOS tube MP1 are connected; the gate of the NMOS tube MN1 and the gate of the NMOS tube MS10 in the start-up circuit (3) are connected; the gate and drain of the NMOS tube MS10 are connected; the source of the NMOS tube MN1 and the drain of the NMOS tube MN2 are connected; the operational amplifier OPA The output is connected to the gate of the NMOS tube MN2; the drain of the PMOS tube MP2 is connected to the internal bias current source of the operational amplifier OPA; the drain of the PMOS tube MP3 is connected to the reverse input terminal X of the operational amplifier OPA, and the non-inverting input terminal Y of the operational amplifier OPA is connected to the emitter of the PNP transistor Q2; the base and collector of the PNP transistor Q1 are connected, the base of the PNP transistor Q1, the base of the PNP transistor Q2, and the base of the PNP transistor Q3 are connected, and the collector of the PNP transistor Q1, the collector of the PNP transistor Q2, and the collector of the PNP transistor Q3 are grounded; In the compensation filter circuit (2), the source of the PMOS tube MP4, the source of the PMOS tube MP5, and the source of the PMOS tube MP6 are connected to the positive electrode of the power supply; the gate and drain of the NMOS tube MN3 are connected, the drain of the PMOS tube MP4 is connected to the drain of the NMOS tube MN3, the gate of the NMOS tube MN3, the gate of the NMOS tube MN4, and the gate of the NMOS tube MN5 are connected; the source of the NMOS tube MN3 and the emitter of the PNP transistor Q3 are connected; the drain of the NMOS tube MN4, the drain of the NMOS tube MN5, and the drain of the PMOS tube MP5 are connected, the drain and gate of the PMOS tube MP5 are connected, and the gate of the PMOS tube MP5 and the gate of the PMOS tube MP6 are connected; the collector of the PNP transistor Q3, the source of the NMOS tube MN5, and the drain and source of the NMOS tube MC2 are connected to ground; In the startup circuit (3), the source of the PMOS tube MS1, the source of the PMOS tube MS2, the source of the PMOS tube MS3, the source of the PMOS tube MS4, the source of the PMOS tube MS6, the source of the PMOS tube MS7, the source of the PMOS tube MS8, and the source of the PMOS tube MS9 are connected to the positive electrode of the power supply; the gate and drain of the PMOS tube MS1 are connected, the gate of the PMOS tube MS1, the drain of the PMOS tube MS6, the gate of the PMOS tube MS2 are connected, the drain of the PMOS tube MS1, the gate of the PMOS tube MS7, the gate of the PMOS tube MS8, the gate of the PMOS tube MS9, and the drain of the PMOS tube MS4 are connected; the drain of the PMOS tube MS2, the drain of the PMOS tube MS3, and the drain of the NMOS tube MS5 are connected; the gate and drain of the NMOS tube MS10 are connected, the gate of the NMOS tube MS10 and the gate of the NMOS tube MN1 are connected; and the source of the NMOS tube MS5 is grounded.

3. The circuit according to claim 2, characterized in that The bandgap core circuit (1) further comprises: a resistor R1, a resistor R2, a resistor R3, and a resistor R11; two ends of the resistor R1 are respectively connected to the drain of the PMOS tube MP3 and the negative electrode of the operational amplifier OPA, two ends of the resistor R2 are respectively connected to the drain of the PMOS tube MP3 and the positive electrode of the operational amplifier OPA, two ends of the resistor R3 are respectively connected to the negative electrode of the operational amplifier OPA and the emitter of the PNP transistor Q1, and the resistor R11 is connected to the source of the NMOS tube MN2 and then grounded; The compensation filter circuit (2) further comprises: a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a capacitor C1; the resistor R4 is connected to the source of the NMOS tube MN4 and then to ground; one end of the resistor R5 is connected to the drain of the PMOS tube MP6, the other end of the resistor R5 is connected to one end of the resistor R6, and one end of the resistor R6 is connected to one end of the resistor R7 and one end of the resistor R8; the other end of the resistor R6 is connected to the output first-order reference voltage V of the core circuit (1). REF1 The other end of the resistor R7 is grounded; the other end of the resistor R8 is connected to the gate of the NMOS tube capacitor MC2, and the capacitor C1 is connected in parallel to the NMOS tube capacitor MC2; The startup circuit (3) further comprises: a resistor R9, a resistor R10, an inverter INV, and a Schmitt trigger SMT; the two ends of the resistor R9 are respectively connected to the drain of the PMOS tube MS4 and the drain of the NMOS tube MS10, one end of the resistor R10 is connected to the source of the NMOS tube MS10, and the other end of the resistor R10 is grounded; the inverter INV output is connected in series with the Schmitt trigger SMT input, the Schmitt trigger SMT output is connected to the gate of the PMOS tube MS6, and the inverter INV input is connected to the drain of the NMOS tube MS5.

4. The circuit according to claim 2, characterized in that The PMOS tube MP1, the PMOS tube MP2 and the PMOS tube MP3 form a first current mirror; the first current mirror provides bias for the PMOS tube MP4 in the compensation filter circuit (2) and the PMOS tube MS3 and the PMOS tube MS4 in the start-up circuit (3).

5. The circuit according to claim 2, characterized in that The PNP transistor Q1, the PNP transistor Q2 and the PNP transistor Q3 form a second current mirror, and the second current mirror provides a bias for the PNP transistor Q3 in the compensation filter circuit (2).

6. The circuit according to claim 2, characterized in that: The PMOS tube MS1 and the PMOS tube MS2 form a fifth current mirror; the NMOS tube MN1 and the NMOS tube MS10 form a sixth current mirror; the sixth current mirror provides a bias for the NMOS tube MN1 in the core circuit (1).

7. The circuit according to claim 4, characterized in that The core circuit (1) controls and distributes the respective width-to-length ratios of the PMOS tube MP3, the PMOS tube MP2, and the PMOS tube MP1 in the first current mirror, thereby adjusting the current of the loop formed by the first current mirror and the operational amplifier OPA, thereby achieving control of the operating current.

8. The circuit according to claim 3, characterized in that The resistor R8, the capacitor C1, and the NMOS transistor MC2 form a first-order RC low-pass filter, and the RC low-pass filter is used for the first-order reference voltage V REF1 The voltage signal is low-pass filtered to obtain a low temperature coefficient reference voltage V REF2 .

9. A control method for a high PSRR low noise bandgap reference circuit with curvature compensation according to any one of claims 1 to 8, characterized in that: When the start-up circuit (3) is started, the PMOS transistor MS1 is turned on first, and then the PMOS transistors MS7, MS8 and MS9 start to inject charges into the nodes of the bandgap core circuit (1), so that the bandgap core circuit (1) escapes from the zero output steady state; The low temperature coefficient reference voltage V REF2 During the establishment process, PMOS tubes MS1 and MS2 replace PMOS tubes MS3 and MS4 to provide current for the startup circuit (3); the fifth current mirror provides bias current for the operational amplifier OPA until the low temperature coefficient reference voltage V REF2 After the establishment is completed, the NMOS tube MS5 is controlled to be turned on and a low level is input to the inverter INV. After passing through the Schmitt trigger SMT, the PMOS tube MS6 is slowly turned on, and the gate voltages of the PMOS tubes MS1 and MS2 are gradually increased. The PMOS tubes MS1, MS2, MS7, MS8 and MS9 are controlled to be turned off. The PMOS tubes MS3, MS4 and MP2 continuously supply power to the startup circuit (3), and the startup circuit (3) is started. The bandgap core circuit (1) and the compensation filter circuit (2) enter the working state, and the entire bandgap circuit works to provide the required bias current and output the low temperature coefficient reference voltage V REF2 .

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