Method for adjusting working state of memory device and related memory device, electronic device and memory controller

Abstract

The invention relates to a method for adjusting the working state of a memory device, a related memory device, an electronic device and a memory controller. The method includes configuring the memory controller to perform the following steps: setting a waiting time before the memory device enters a power-saving state as a first time value, wherein the memory device enters the power-saving state after being driven by a power-saving instruction and passing through the waiting time; judging whether the host device is performing read-write operation or not; and setting the waiting time as a second time value in response to the fact that the host device is performing the read-write operation, the first time value being smaller than the second time value.

Description

Technical Field

[0001] The present invention relates to the field of memory control, and in particular to a method for adjusting the working state of a memory device and a related memory device, an electronic device and a memory controller. Background Art

[0002] The memory device may include a flash memory for storing data, and the management of access to the flash memory is quite complex. For example, the memory device may be a memory card, a solid state drive (SSD), or an embedded memory device (e.g., an embedded memory device that complies with the universal flash storage (UFS) specification).

[0003] In order to save power, the host side (e.g., the bottom layer of a host device) will automatically send a packet to enter the power saving mode to inform the memory device to enter the power saving mode. When the memory device receives this packet, it will enter the power saving mode. After the memory device enters the power saving mode, it takes a relatively long time to process the instructions sent by the host side, resulting in a decrease in performance. In order to maintain performance, the prior art practice is that after the memory device receives the power saving instruction (i.e., the above-mentioned packet) from the host side, it waits for a predetermined time instead of immediately entering the power saving mode, so as to avoid experiencing the wake-up time too frequently due to improper entry into the power saving mode. On the other hand, in the above method, the memory device waits for an additional predetermined time before entering the power saving mode, which is equivalent to the memory device having to bear the additional power consumption caused by the delay in entering the power saving mode.

[0004] Therefore, there is a real need for an innovative method and related architecture to solve the above problems. Summary of the invention

[0005] As mentioned above, one embodiment of the present invention is to provide a method for adjusting the working state of a memory device and related memory devices, electronic devices and memory controllers, so that when the bottom layer of the host side automatically sends a power saving instruction, a judgment condition is added to the original firmware through software to confirm whether the host side is currently in an idle state or a non-idle state, thereby dynamically adjusting the waiting time before the memory device enters the power saving mode, so as to reduce power consumption while maintaining the reading and writing speed of the memory device.

[0006] Another embodiment of the present invention further provides a method for adjusting the working state of a memory device, wherein the memory device is used to couple to a host device and includes a memory controller and a non-volatile memory, wherein the memory controller is coupled to the non-volatile memory and used to control the operation of the memory device; the method includes configuring the memory controller to perform the following steps: setting a waiting time before the memory device enters a power saving state to a first time value, wherein the memory device enters the power saving state only after being driven by a power saving instruction and after the waiting time has passed; determining whether the host device is performing a read or write operation; and in response to the host device performing a read or write operation, setting the waiting time to a second time value, wherein the first time value is less than the second time value.

[0007] Another embodiment of the present invention provides a memory device, comprising a non-volatile memory and a memory controller. The non-volatile memory is used to store information, and the memory controller is coupled to the non-volatile memory and used to control the operation of the memory device, wherein the memory controller comprises a processing circuit and a transmission interface circuit. The processing circuit is used to control the memory controller according to a plurality of host instructions from a host device, so as to allow the host device to access the non-volatile memory through the memory controller. The transmission interface circuit is used to communicate with the host device and perform transmission and reception operations. The memory controller is configured to perform the following steps: setting a waiting time before the memory device enters a power saving state to a first time value, wherein the memory device enters the power saving state after being driven by a power saving instruction and after the waiting time has passed; determining whether the host device is performing a read / write operation; and in response to the host device performing a read / write operation, setting the waiting time to a second time value, wherein the first time value is less than the second time value.

[0008] Another embodiment of the present invention provides an electronic device, which includes the above-mentioned memory device and the above-mentioned host device, wherein the host device is coupled to the memory device and includes: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and used to provide power to the at least one processor and the memory device; wherein the memory device provides storage space for the host device.

[0009] Another embodiment of the present invention provides a memory controller for a memory device, wherein the memory device includes the memory controller and a non-volatile memory, wherein the memory controller includes: a processing circuit for controlling the memory controller according to a plurality of host instructions from a host device to allow the host device to access the non-volatile memory through the memory controller; and a transmission interface circuit for communicating with the host device, wherein the memory controller is configured to perform the following steps: setting a waiting time before the memory device enters a power saving state to a first time value, wherein the memory device enters the power saving state after being driven by a power saving instruction and after the waiting time has passed, wherein the waiting time starts when the host device is in an idle state, and the first time value is less than the waiting time; determining whether the host device is performing a read or write operation; and in response to the host device performing a read or write operation, setting the waiting time to a second time value, wherein the first time value is less than the second time value.

[0010] Optionally, in an embodiment of the present invention, the first time value is greater than or equal to 0 ms.

[0011] Optionally, in an embodiment of the present invention, the second time value is greater than or equal to 20 ms.

[0012] Optionally, in one embodiment of the present invention, the step of determining whether the host device is performing a read / write operation includes: detecting whether a read instruction or a write instruction is received from the host device, wherein when the read instruction or the write instruction is detected and at least one of the following conditions is met, it is determined that the host device is performing a read / write operation: if the amount of data read or written after executing the read instruction or the write instruction is greater than a first threshold; and if the number of consecutive read instructions or write instructions executed after executing the read instruction or the write instruction is greater than a second threshold. Optionally, in one embodiment of the present invention, when the amount of data in three consecutive read instructions or the write instructions is greater than the first threshold, it is determined that the host device is performing a read / write operation.

[0013] Optionally, in an embodiment of the present invention, the second threshold is at least 2.

[0014] Optionally, in an embodiment of the present invention, the first threshold is greater than or equal to 512Kb.

[0015] In summary, the present invention can accelerate the memory device to enter power saving mode to reduce power consumption by changing the conditions for the memory device to enter power saving mode. At the same time, through the judgment mechanism, when the electronic device has read and write requirements, the memory device is restored to enter power saving mode after a waiting period, thereby not reducing the overall performance.

[0016] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0018] Figure 2 FIG. 4 is a flow chart of a method for adjusting the working state of a memory device according to an embodiment of the present invention.

[0019] Figure 3 The present invention is a block diagram of a memory controller adjusting the working state of a memory device. DETAILED DESCRIPTION

[0020] The present invention is particularly described with the following examples, which are only used for illustration, because for those skilled in the art, various changes and modifications can be made without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be determined by the scope of the attached patent application. Throughout the specification and the patent application, unless the content clearly specifies, the meaning of "one" and "the" includes this type of description including "one or at least one" element or component. In addition, as used in the present invention, unless it is obvious from the specific context that the plural number is excluded, the singular article also includes the description of multiple elements or components. Moreover, when applied in this description and the following all patent applications, unless the content clearly specifies, the meaning of "in which" may include "in which" and "on it". The terms used in the specification and the patent application, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed herein and in the special content. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide practitioners with additional guidance in describing the present invention. The use of examples anywhere throughout the specification, including examples of any term discussed herein, is intended to be illustrative only and certainly does not limit the scope and meaning of the present invention or any exemplified term. Likewise, the present invention is not limited to the various embodiments set forth in this specification.

[0021] As used herein, the terms "substantially", "around", "about" or "approximately" shall generally mean within 20%, preferably within 10%, of a given value or range. In addition, the quantities provided herein may be approximate, thus meaning that the terms "approximately", "about" or "approximately" may be used unless otherwise stated. When a quantity, concentration or other numerical value or parameter has a specified range, a preferred range or lists upper and lower ideal values, it shall be deemed to specifically disclose all ranges consisting of any upper and lower limit pairs or ideal values, regardless of whether the same ranges are disclosed separately. For example, if a range is disclosed as a length of X cm to Y cm, it shall be deemed to disclose a length of H cm and H may be any real number between X and Y.

[0022] In addition, if the term "electrically coupled" or "electrically connected" is used, it includes any direct and indirect electrical connection means. For example, if the text describes that a first device is electrically coupled to a second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means. In addition, if the transmission or provision of an electrical signal is described, a person skilled in the art should understand that the transmission process of the electrical signal may be accompanied by attenuation or other non-ideal changes, but the source and receiving end of the transmission or provision of the electrical signal should be regarded as the same signal if there is no special description. For example, if an electrical signal S is transmitted (or provided) from terminal A of an electronic circuit to terminal B of the electronic circuit, a voltage drop may be generated through the source and drain of a transistor switch and / or possible stray capacitance. However, if the purpose of this design is not to deliberately use the attenuation or other non-ideal changes generated during the transmission (or provision) to achieve certain specific technical effects, the electrical signal S at terminal A and terminal B of the electronic circuit should be regarded as substantially the same signal.

[0023] It is understood that the terms "comprising", "including", "having", "containing", "involving", etc. used herein are open-ended, that is, they mean including but not limited to. In addition, any embodiment or patent application of the present invention does not necessarily achieve all the objects, advantages or features disclosed in the present invention. In addition, the abstract part and the title are only used to assist in searching patent documents and are not used to limit the patent application scope of the present invention.

[0024] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The memory device 100 may include at least one processor (e.g., one or more processors), which may be collectively referred to as a processor 52, a power supply circuit 54, and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the power supply circuit 54, and the memory device 100, and output one or more driving voltages to the memory device 100, wherein the memory device 100 may provide storage space to the host device 50, and may obtain one or more driving voltages from the host device 50 as the power supply of the memory device 100. Examples of the host device 50 may include, but are not limited to, multi-function mobile phones, tablet computers, wearable devices, and personal computers, such as desktop calculators and notebook calculators. Examples of the memory device 100 may include, but are not limited to, portable memory devices (such as memory cards that comply with SD / MMC, CF, MS, or XD specifications, solid state drives (SSDs), and different types of embedded memory devices (such as embedded memory devices that comply with universal flash storage (UFS) specifications or embedded multimedia card (eMMC) specifications). According to this embodiment, the memory device 100 may include a memory controller, such as a memory controller 110, and may further include a non-volatile (NV) memory 120 (in Figure 1 The nonvolatile memory 120 may include at least one nonvolatile memory element (e.g., one or more nonvolatile memory elements), such as a plurality of nonvolatile memory elements 122-1, 122-2, ..., and 122-N (in the example of FIG. 1 ). Figure 1 , respectively marked as “NV memory elements”), where “N” can represent a positive integer greater than 1. For example, the non-volatile memory 120 can be a flash memory, and the multiple non-volatile memory elements 122-1, 122-2, ..., and 122-N can be multiple flash memory chips or multiple flash memory dies, respectively, but the present invention is not limited to this.

[0025] like Figure 1As shown, the memory controller 110 may include a processing circuit (e.g., a microprocessor 112), a storage unit (e.g., a read-only memory (ROM) 112M; labeled as "ROM"), a control logic circuit 114, a random access memory 116 (e.g., it can be implemented by a static random access memory; labeled as "RAM"), and a transmission interface circuit 118, wherein at least a portion (e.g., a portion or all) of the above components may be coupled to each other via a bus. The random access memory 116 may be used to provide an internal storage space (e.g., temporarily storing information) to the memory controller 110, but the present invention is not limited thereto. In addition, the read-only memory 112M of this embodiment is used to store a computer code 112C, and the microprocessor 112 is used to execute the computer code 112C to control access to the non-volatile memory 120. It should be noted that the computer code 112C may also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 may be used to control the non-volatile memory 120. The control logic circuit 114 may include an error correction code (ECC) circuit (not shown). Figure 1 ), which can perform error correction code encoding and error correction code decoding to protect data, and / or perform error correction. The transmission interface circuit 118 can comply with one or more communication specifications among various communication specifications (such as the Serial Advanced Technology Attachment (SATA) specification, the Universal Serial Bus (USB) specification, the Peripheral Component Interconnect Express (PCIE) specification, the Embedded Multimedia Card specification, and the Universal Flash Memory specification), and can communicate with the memory device 100 and the host device 50 (such as the transmission interface circuit 58) according to the one or more communication specifications. Similarly, the transmission interface circuit 58 can comply with one or more communication specifications, and can communicate with the host device 50 and the memory device 100 (such as the transmission interface circuit 118) according to the one or more communication specifications. The transmission interface circuit 58 can be implemented with a circuit architecture (such as a plurality of corresponding sub-circuits) having a circuit architecture similar to or identical to the circuit architecture of the transmission interface circuit 118.

[0026] In this embodiment, the host device 50 may transmit a plurality of host commands corresponding to the logical address to the memory controller 110 to indirectly access the non-volatile memory 120 in the memory device 100. The memory controller 110 receives the plurality of host commands and the logical address, converts the plurality of host commands into memory operation commands (which may be operation commands), and further controls the non-volatile memory 120 with the operation commands to read or write / program memory cells or data pages at specific physical addresses in the non-volatile memory 120, wherein the physical address may be associated with the logical address. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical address and the logical address.

[0027] In addition, the at least one non-volatile memory element (e.g., one or more non-volatile memory elements, such as {122-1, 122-2, ..., 122-N}) may include a plurality of blocks, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the non-volatile memory 120 may be a block, and the minimum unit for the memory controller 110 to perform a data write operation on the non-volatile memory 120 may be a page, but the present invention is not limited thereto. For example, any non-volatile memory element 122-N (where "N" may represent any integer in the interval [1, N]) among the non-volatile memory elements 122-1, 122-2, ..., and 122-N may include a plurality of blocks, and one of the plurality of blocks may include and record a specific number of pages, wherein the memory controller 110 may access a certain page in a certain block among the plurality of blocks according to the block address and the page address.

[0028] After the host device 50 sends a power saving instruction to the control logic circuit 114, the control logic circuit 114 can add a judgment condition to the original firmware through software to confirm whether the host device 50 is currently in an idle state or a non-idle state, and then dynamically adjust the waiting time before the memory device 100 enters the power saving mode, so as to maintain the read and write speed of the memory device 100 while also reducing power consumption. The above power saving state can be a dormant state of the device, such as a low power mode or a shutdown mode.

[0029] Please refer to Figure 2 , Figure 2 1 is a flow chart of a method for adjusting the working state of a memory device according to an embodiment of the present invention. Please note that these steps do not necessarily have to be followed if substantially the same results can be obtained. Figure 2 Execute in the order shown. Figure 2 The method shown can be adopted by the electronic device 10, the host device 50 and / or the memory device 100, and performs the following steps by configuring the memory controller in the memory device:

[0030] Step S202: start;

[0031] Step S204: setting the waiting time before the memory device enters the power saving state to a first time value, wherein the memory device enters the power saving state only after being driven by the power saving instruction and the waiting time has elapsed;

[0032] Step S206: Determine whether the host device is performing a read / write operation; and

[0033] Step S208: In response to the host device performing a read or write operation, setting the waiting time to a second time value, wherein the first time value is smaller than the second time value.

[0034] Since those who are familiar with the technology should be able to easily understand after reading the above paragraphs Figure 2 The details of each step in the above process will be omitted for brevity.

[0035] For details, please refer to Figure 3 , Figure 3 It is a block diagram of the memory controller 110 of the present invention adjusting the working state of the memory device 100. Figure 3 The block diagram can be seen as Figure 2 An implementation detail of the method. First, in steps S302 and S304, the memory controller 110 sets the waiting time for the memory device 100 to enter the power saving state to a first time value (e.g., 0 ms, but the present invention is not limited thereto), wherein the waiting time starts when, for example, the memory controller 110 receives a power saving instruction from the host device 50. The above-mentioned waiting time is set to prevent the memory device 100 from entering the power saving mode and being awakened too frequently, so a buffer time is required to confirm that the host device 50 has no need to access the memory device 100 before the memory device 100 enters the power saving mode. In this embodiment, it is assumed at the beginning of the process that the host device 50 has no need to access the memory device 100, so the waiting time is first set to the first time value (e.g., 0 ms).

[0036] Next, the memory controller 110 detects in step S306 whether there are any commands from the host device 50. If any commands from the host device 50 are detected, the memory controller 110 further determines in step S308 whether the commands include read commands or write commands. If so, the process proceeds to step S312; if not, the process proceeds to step S310 to process other types of commands.

[0037] Next, in step S312, in response to a read instruction or a write instruction from the host device 5, the memory controller 110 detects whether the amount of data to be read or written by the instruction is greater than a first threshold value (e.g., 512Kb, but the present invention is not limited thereto). If the detection result is yes, the process enters step S314, for example, by using a counter to add a count value by 1 (indicated as "Counter+1" in the figure), and this count value represents the number of consecutive processing of read instructions or write instructions whose data amount is greater than the first threshold value; if the detection result is no, the process enters step S320, processing the read instruction or write instruction, but not modifying the above-mentioned waiting time. After step S314, the process enters step S316 to determine whether the number of consecutive processing of read instructions or write instructions with a data volume greater than the first threshold is greater than a second threshold (indicated as "Counter>2" in the figure) after executing the read instruction or write instruction. In this example, if there are at least three consecutive instructions greater than the first threshold, it is determined that the host device 50 still has a need for read and write operations, and the process enters step S318; if not, the process enters step S320 to process the read and write instructions, but does not modify the above-mentioned first time value. Please note that although in this embodiment, the host device 50 is judged whether it still has a need for read and write operations based on the continuous processing of two read instructions or write instructions with a data volume greater than 512KB, other judgment conditions can also be used to replace it according to actual design requirements. For example, 512KB in step S312 can be set to other data volumes, and / or the value 2 used to determine the number of data for continuous reading and writing in step S316 can be changed to other values. Even step S314 and step S316 may be omitted, and when the execution result of step S312 is "yes", step S318 is directly executed); or even step S314 may be omitted, and step S314 and step S316 are executed after step S308, or step S318 is directly executed after step S308.

[0038] In step S318, the memory controller 110 sets the waiting time to a second time value. The second time value may be, for example, 20 ms or a time of other length (but should be greater than the first time value). This is because it is determined that the host device 50 may still have a need for read and write operations. Therefore, after receiving the power saving instruction, a waiting time (for example, 20 ms) is required before the memory device 100 enters the power saving mode.

[0039] In summary, the present invention can accelerate the memory device to enter power saving mode to reduce power consumption by changing the conditions for the memory device to enter power saving mode. At the same time, through the judgment mechanism, when the electronic device has read and write requirements, the memory device is restored to enter power saving mode after a waiting period, thereby not reducing the overall performance.

[0040] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes by using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for adjusting the working state of a memory device, characterized in that: The memory device is used to couple to a host device and includes a memory controller and a non-volatile memory. The memory controller is coupled to the non-volatile memory and used to control the operation of the memory device. The method includes configuring the memory controller to perform the following steps: Setting a waiting time before the memory device enters a power saving state to a first time value, wherein the memory device enters the power saving state after being driven by a power saving instruction and the waiting time has elapsed; Determining whether the host device is performing a read or write operation; and In response to the host device performing a read / write operation, the waiting time is set to a second time value, wherein the first time value is smaller than the second time value.

2. The method according to claim 1, characterized in that The first time value is greater than or equal to 0 ms.

3. The method according to claim 1, characterized in that The second time value is greater than or equal to 20 ms.

4. The method according to claim 1, characterized in that The step of determining whether the host device is performing a read / write operation comprises: Detecting whether a read instruction or a write instruction is received from the host device, wherein when the read instruction or the write instruction is detected and meets at least one of the following conditions, it is determined that the host device is performing a read or write operation: If after executing the read instruction or the write instruction, the amount of data read or written is greater than a first threshold; as well as If after executing the read instruction or the write instruction, the number of the read instructions or the write instructions that have been executed continuously is greater than a second threshold.

5. The method according to claim 4, characterized in that The second threshold is at least 2.

6. The method according to claim 4, characterized in that The first threshold is greater than or equal to 512Kb.

7. A memory device, characterized in that: Contains: a non-volatile memory for storing information; as well as a memory controller coupled to the non-volatile memory and configured to control the operation of the memory device, wherein the memory controller comprises: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller; as well as a transmission interface circuit for communicating with the host device to perform transmission and reception operations; The memory controller is configured to perform the following steps: Setting a waiting time before the memory device enters a power saving state to a first time value, wherein the memory device enters the power saving state after being driven by a power saving instruction and the waiting time has elapsed; Determining whether the host device is performing a read or write operation; and In response to the host device performing a read / write operation, the waiting time is set to a second time value, wherein the first time value is smaller than the second time value.

8. The memory device according to claim 7, wherein: The first time value is greater than or equal to 0 ms.

9. The memory device according to claim 7, wherein: The second waiting time is greater than or equal to 20 ms.

10. The memory device according to claim 9, wherein: The memory controller detects whether a read instruction or a write instruction is received from the host device. When the read instruction or the write instruction is detected and at least one of the following conditions is met, the memory controller determines that the host device is performing a read or write operation: If after executing the read instruction or the write instruction, the amount of data read or written is greater than a first threshold; as well as If after executing the read instruction or the write instruction, the number of the read instructions or the write instructions that have been executed continuously is greater than a second threshold.

11. The memory device according to claim 10, wherein: The second threshold is at least 2.

12. The memory device according to claim 10, wherein: The first threshold is greater than or equal to 512Kb.

13. An electronic device, characterized in that: The electronic device comprises the memory device of claim 8, and further comprises: the host device coupled to the memory device, wherein the host device comprises: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor and used to provide power to the at least one processor and the memory device; wherein the memory device provides storage space to the host device.

14. The electronic device according to claim 13, wherein: The first time value is greater than or equal to 0 ms, and the second time value is greater than or equal to 20 ms.

15. The electronic device as claimed in claim 13, wherein: The memory controller detects whether a read instruction or a write instruction is received from the host device. When the read instruction or the write instruction is detected, the memory controller determines that the host device is performing a read or write operation when the read instruction or the write instruction is detected and at least one of the following conditions is met: If after executing the read instruction or the write instruction, the amount of data read or written is greater than a first threshold; as well as If after executing the read instruction or the write instruction, the number of the read instructions or the write instructions that have been executed continuously is greater than a second threshold.

16. The electronic device as claimed in claim 15, characterized in that: The second threshold is at least 2, and the first threshold is greater than or equal to 512Kb.

17. A memory controller for a memory device, characterized in that: The memory device includes the memory controller and a non-volatile memory, wherein the memory controller includes: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller; and a transmission interface circuit for communicating with the host device, wherein the memory controller is configured to perform the following steps: Setting a waiting time before the memory device enters a power saving state to a first time value, wherein the memory device enters the power saving state after being driven by a power saving instruction and after the waiting time has elapsed, the waiting time starting when the host device is in an idle state, and the first time value is less than the waiting time; Determining whether the host device is performing a read or write operation; and In response to the host device performing a read / write operation, the waiting time is set to a second time value, wherein the first time value is smaller than the second time value.

18. The memory controller according to claim 17, wherein: The first time value is greater than or equal to 0 ms, and the second time value is greater than or equal to 20 ms.

19. The memory controller according to claim 17, wherein: The memory controller detects whether a read instruction or a write instruction is received from the host device. When the read instruction or the write instruction is detected and at least one of the following conditions is met, the memory controller determines that the host device is performing a read or write operation: If after executing the read instruction or the write instruction, the amount of data read or written is greater than a first threshold; as well as If after executing the read instruction or the write instruction, the number of the read instructions or the write instructions that have been executed continuously is greater than a second threshold.

20. The memory controller of claim 19, wherein: The second threshold is at least 2, and the first threshold is greater than or equal to 512Kb.

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