Space array type processor core
By using a spatial array processor core in the processor core, using the MO broadcast bus, MC broadcast bus and ACC standard bus for data communication, the problems of limited computing unit scale and poor data communication flexibility in the prior art are solved, and the problem of implementation is realized. Efficient computing power expansion and memory access optimization have been improved, and the overall performance of the processor has been improved.
Patent Information
- Application Number
- CN202411411259.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-01-07
AI Technical Summary
The existing processor core computing units have shortcomings in computing power expansion and memory access efficiency, especially the problems of limited computing unit size and poor data communication flexibility.
Using a spatial array processor core, by arranging the computing units into an array according to spatial dimensions, using the MO broadcast bus, MC broadcast bus and ACC standard bus for data communication, forming a ring interconnect structure to realize data sharing and Cache of operation results, reducing dependence on centralized registers and control logic.
It effectively saves the memory access bandwidth of the computing unit, expands the computing power of the processor, can run at higher efficiency and lower power consumption, and supports flexible data communication mode, improving algorithm execution efficiency.
Smart Images
Figure CN119271173A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a processor core architecture, and in particular to a spatial array processor core. Background Art
[0002] The arithmetic unit is the carrier for the processor core to perform operations. The reasonable organization of the arithmetic unit is the key to the performance of the processor. A large number of arithmetic units are integrated inside the high-computing power processor. How to make these arithmetic units run efficiently at a higher frequency and lower power consumption is an issue that needs to be paid attention to in the design of the processor core. At present, the organization forms of the arithmetic units of the mainstream processor core include two categories: vector processors and data stream processors. The following analyzes the advantages and disadvantages of these two processors respectively.
[0003] Figure 6 This is a schematic diagram of the organization of the core arithmetic unit of the vector processor. In the figure, ALU (Algorithm Logical Unit) represents the arithmetic logic unit. Each ALU is an independent arithmetic unit. The source operand and the destination operand are all from the centralized register file and are controlled by a unified control logic. There is no data exchange between ALUs. This organizational form is simple in design and can run at a higher frequency when the number of arithmetic units is small. The disadvantage of this organizational form is that the scale of the arithmetic unit is limited. As the number of arithmetic units increases, the scale of the register file and the control logic increases linearly. The register file is a storage unit that takes up a lot of physical space and cannot be increased linearly. On the other hand, the number of arithmetic units that can be controlled by the centralized control logic is also limited. As the number of arithmetic units increases, the fan-out number of the control logic also increases, which will reduce the operating frequency of the processor.
[0004] Figure 7 This is a diagram of the organization of the core computing unit of the data stream processor. The centralized register file and control logic are broken up and distributed inside each ALU, which solves the problem of limited physical scale of the register file and control logic. Adjacent ALUs complete data interaction by hand-in-hand. A group of ALUs close to the memory access the memory hierarchy and transmit the accessed data or processed data to the adjacent ALU to achieve data stream communication. This organizational form solves the problem of centralized storage and control of vector processors. Distributed registers and control logic have the advantage of scalable computing unit scale, but the ALU interconnection structure is single and cannot meet the flexible data communication requirements, especially communication modes such as data broadcasting and aggregation, thereby reducing the actual execution efficiency of the algorithm. Summary of the invention
[0005] 1. Technical issues to be solved
[0006] In view of the above-mentioned shortcomings of the prior art, the present invention provides a spatial array processor core, which can effectively overcome the defects of the prior art such as poor computing power scalability and low memory access efficiency.
[0007] (II) Technical solution
[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:
[0009] A spatial array processor core comprises a processing array PE_Array, an arithmetic logic array ALU_Array, a register file REG, a processing macro Macro, a data memory DM and an instruction memory IMEM;
[0010] Operation array PE_Array, an array composed of operation units PE arranged according to the spatial dimension;
[0011] Arithmetic logic array ALU_Array, an array composed of arithmetic logic units ALU;
[0012] Register file REG, used for communication between operation array PE_Array and data memory DM, and between arithmetic logic array ALU_Array and data memory DM;
[0013] The operation macro Macro is composed of the operation array PE_Array, the arithmetic logic array ALU_Array and the register file REG. The operation macros Macro form a ring interconnection structure through the inter-macro data transmission channel;
[0014] Data memory DM is a private data storage space for each operation macro Macro;
[0015] The instruction memory IMEM is used to store the execution instructions of the processor core. The program counter drives the core instruction fetch module to access the instruction memory IMEM. The decoding module completes the instruction decoding. The execution module completes the instruction execution task according to the instruction decoding result.
[0016] The computing units PE in the computing array PE_Array communicate with each other via the MO broadcast bus, the MC broadcast bus and the ACC protocol bus.
[0017] Preferably, the operation unit PE includes a multiplier MUL, an adder ADD, a truncation unit CUT, an accumulator register ACC and a local cache MO. The operation unit PE can perform operations using the local cache MO to store data or the MO data transmitted by the MO broadcast bus. The intermediate results of the operations are cached in the accumulator register ACC, or written to the local cache MO after being truncated by the truncation unit CUT.
[0018] Preferably, the MO broadcast bus includes a MO row broadcast bus and a MO column broadcast bus, and the operation units PE located in the same row realize MO data sharing through the MO row broadcast bus, and the operation units PE located in the same column realize MO data sharing through the MO column broadcast bus;
[0019] The MC broadcast bus is used for the computing units PE in the same row to share a coefficient memory MC, and the coefficient memory MC broadcasts MC data to the computing units PE in the same row;
[0020] The ACC protocol bus is a protocol tree formed by interconnecting the accumulator registers ACC in the operation units PE in the same column to complete the addition or subtraction operations of the accumulator registers ACC in the operation units PE in the same column.
[0021] Preferably, each of the operation arrays PE_Array is composed of 16*16, a total of 256 operation units PE arranged according to the spatial dimension;
[0022] The operation macro Macro includes a first operation macro X, a second operation macro Y, a third operation macro Z, and a fourth operation macro T. The processor core includes 4*16*16, a total of 1024 operation units PE;
[0023] The data memory DM includes a first data memory DM1, a second data memory DM2, a third data memory DM3, and a fourth data memory DM4, which are private data storage spaces of the first operation macro X, the second operation macro Y, the third operation macro Z, and the fourth operation macro T respectively.
[0024] Preferably, the bit width of the MO row broadcast bus depends on the number of operation units PE participating in the row broadcast at the same time. Each operation array PE_Array contains 16 operation units PE in one row, and the number of operation units PE participating in the row broadcast at the same time is 4. Each operation unit PE sends local MO data to 4 broadcast buses and selects 1 broadcast data from the 4 broadcast buses as an operand. Therefore, each operation unit PE is a 4-transmit 1-receive structure on the MO row broadcast bus.
[0025] The bit width of the MO column broadcast bus depends on the number of operation units PE participating in the column broadcast at the same time. Each column in the operation array PE_Array contains 16 operation units PE, and the number of operation units PE participating in the column broadcast at the same time is 4. Each of the operation units PE sends local MO data to 4 broadcast buses and selects 1 broadcast data from these 4 broadcast buses as an operand. Therefore, each of the operation units PE on the MO column broadcast bus is also a 4-transmit 1-receive structure.
[0026] Preferably, the coefficient memory MC is composed of 4 static random access memory cells SRAM, which are interleavedly addressed;
[0027] Among them, the four static random access memory cells SRAM are MC_0, MC_1, MC_2, and MC_3. All storage addresses inside MC_0 are addresses modulo 4 = 0, all storage addresses inside MC_1 are addresses modulo 4 = 1, all storage addresses inside MC_2 are addresses modulo 4 = 2, and all storage addresses inside MC_3 are addresses modulo 4 = 3.
[0028] Preferably, the coefficient memory MC includes a base address register MB, and the coefficient memory MC is addressed by using the base address register MB+immediate number. When accessing the coefficient memory MC, only the immediate number needs to be specified, and the base address register MB+immediate number will be used as the initial access address, and the subsequent three addresses will be accessed continuously.
[0029] The bit width of the base address register MB is log2 (the depth of the coefficient memory MC).
[0030] Preferably, the MC data output by the coefficient memory MC is transmitted to one MC broadcast bus through the first selector MUX1, and is simultaneously transmitted to another MC broadcast bus through the second selector MUX2, and the operation units PE in the same row all obtain the broadcast data from the two broadcast buses;
[0031] The first selector MUX1 and the second selector MUX2 are both 4-to-1 data selectors.
[0032] Preferably, the reduction tree composed of 16 accumulator registers ACC corresponding to the operation unit PE in the same column is symmetrical in the upper and lower parts, the upper 8 accumulator registers ACC are mirror-symmetrical with the lower 8 accumulator registers ACC, the sequence number of the target accumulator register ACC reduced by the upper 8 accumulator registers ACC is an even number, and the sequence number of the target accumulator register ACC reduced by the lower 8 accumulator registers ACC is an odd number, and the operation results of the upper 8 accumulator registers ACC and the lower 8 accumulator registers ACC are respectively aggregated to the accumulator register ACC with the smallest sequence number and the largest sequence number, which is conducive to realizing data reduction;
[0033] The height of the reduction tree is log2 (the number of accumulator registers ACC).
[0034] (III) Beneficial effects
[0035] Compared with the prior art, the spatial array processor core provided by the present invention has the following beneficial effects:
[0036] 1) It can effectively save the memory access bandwidth of the computing unit PE. The data required by each computing unit PE to perform operations no longer needs to pass through the centralized register file. The operation can be performed using the local cache MO storage data or the MO data transmitted by the MO broadcast bus. The intermediate results of the operation do not need to be written back to the centralized register file, but can be cached in the accumulator register ACC, or written to the local cache MO after truncation. In a well-designed algorithm, each computing unit PE does not need to repeatedly read and write external data memory, and all operations can be completed based on the on-chip local cache MO;
[0037] 2) It can effectively expand the computing power of the processor. The computing unit PE is not only an independent computing unit, but also can be interconnected through a bus to form an array structure. The array structure can be expanded according to the computing power requirements, and multiple computing arrays PE_Array can also be expanded through the spatial dimension to form a processor computing core with higher computing power;
[0038] 3) It is conducive to design and implementation. In the specific implementation process, the design scale of each operation macro is limited according to the physical implementation constraints, and then all operation macros are implemented according to one hard core. Since the internal structure of each operation macro is consistent, multiple copies can be directly copied during hardware design and physical implementation to form a multi-macro structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0040] Figure 1 It is a schematic diagram of the architecture of the spatial array processor core in the present invention;
[0041] Figure 2 It is a schematic diagram of the structure of the MO broadcast bus and the MC broadcast bus in the present invention;
[0042] Figure 3 Schematic diagram of the address of the coefficient memory MC in the present invention;
[0043] Figure 4 It is a schematic diagram of the coefficient memory MC in the present invention using the base address register MB + immediate number for addressing;
[0044] Figure 5 It is a structural diagram of the ACC protocol bus in the present invention;
[0045] Figure 6A schematic diagram of the organization of a vector processor core computing unit;
[0046] Figure 7 Schematic diagram of the organization of the core computing unit of the data stream processor. DETAILED DESCRIPTION
[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0048] A spatial array processor core, such as Figure 1 As shown, it includes an operation array PE_Array, an arithmetic logic array ALU_Array, a register file REG, an operation macro Macro, a data memory DM and an instruction memory IMEM;
[0049] Operation array PE_Array, an array composed of operation units PE arranged according to the spatial dimension;
[0050] Arithmetic logic array ALU_Array, an array composed of arithmetic logic units ALU;
[0051] Register file REG, used for communication between operation array PE_Array and data memory DM, and between arithmetic logic array ALU_Array and data memory DM;
[0052] The operation macro Macro is composed of the operation array PE_Array, the arithmetic logic array ALU_Array and the register file REG. The operation macros Macro form a ring interconnection structure through the inter-macro data transmission channel;
[0053] Data memory DM is a private data storage space for each operation macro Macro;
[0054] The instruction memory IMEM is used to store the execution instructions of the processor core. The program counter drives the core instruction fetch module to access the instruction memory IMEM. The decoding module completes the instruction decoding. The execution module completes the instruction execution task according to the instruction decoding result.
[0055] The operation units PE in the operation array PE_Array communicate with each other through the MO broadcast bus, the MC broadcast bus and the ACC protocol bus.
[0056] In the technical solution of the present application, the organization form of the spatial array processor core computing unit is to arrange all the computing units PE according to three spatial dimensions, namely "macro-row-column" from top to bottom.
[0057] like Figure 1 As shown in the upper right corner (in the figure, "×" represents the multiplier MUL, and "+" represents the adder ADD), the operation unit PE includes the multiplier MUL, the adder ADD, the truncation unit CUT, the accumulator register ACC and the local cache MO. The operation unit PE can perform operations by using the local cache MO to store data or the MO data transmitted by the MO broadcast bus. The intermediate results of the operation are cached in the accumulator register ACC, or written to the local cache MO after being truncated by the truncation unit CUT.
[0058] In the technical solution of the present application, the operation unit PE is a storage-computation fusion operation unit, which, in addition to the multiplier MUL and the adder ADD for operation, also includes a bit truncation CUT, an accumulator register ACC and a local cache MO. The source operands and destination operands of the traditional arithmetic logic unit ALU can only come from the centralized register file, while the operation unit PE can perform operations based on the local cache MO.
[0059] In the technical solution of the present application, each operation array PE_Array is composed of 16*16, a total of 256 operation units PE arranged according to the spatial dimension;
[0060] The operation macro Macro includes a first operation macro X, a second operation macro Y, a third operation macro Z, and a fourth operation macro T. The processor core includes 4*16*16 operation units PE, a total of 1024;
[0061] The data memory DM includes a first data memory DM1, a second data memory DM2, a third data memory DM3, and a fourth data memory DM4, which are private data storage spaces of the first operation macro X, the second operation macro Y, the third operation macro Z, and the fourth operation macro T respectively.
[0062] like Figure 2 As shown, the MO broadcast bus includes a MO row broadcast bus and a MO column broadcast bus. The operation units PE located in the same row share MO data through the MO row broadcast bus, and the operation units PE located in the same column share MO data through the MO column broadcast bus.
[0063] The bit width of the MO row broadcast bus depends on the number of PEs participating in the row broadcast at the same time. Each row in the PE_Array contains 16 PEs. The number of PEs participating in the row broadcast is 4. Each PE sends local MO data to 4 broadcast buses and selects 1 broadcast data from the 4 broadcast buses. Figure 2 In the example, the 4-to-1 data selector is used as the operand, so each operation unit PE is a 4-transmit 1-receive structure on the MO broadcast bus;
[0064] The bit width of the MO column broadcast bus depends on the number of PEs participating in the column broadcast at the same time. Each column in each operation array PE_Array contains 16 PEs, and the number of PEs participating in the column broadcast is 4. Each PE sends local MO data to 4 broadcast buses and selects 1 broadcast data from these 4 broadcast buses ( Figure 2 In the example, it is implemented through a 4-to-1 data selector) as an operand, so each operation unit PE is also a 4-transmit 1-receive structure on the MO column broadcast bus.
[0065] like Figure 2 As shown, the MC broadcast bus allows the operation units PE in the same row to share a coefficient memory MC, and the coefficient memory MC broadcasts MC data to the operation units PE in the same row.
[0066] like Figure 3 As shown, the coefficient memory MC is composed of 4 static random access memory cells SRAM, which are interleavedly addressed;
[0067] Among them, the four static random access memory cells SRAM are MC_0, MC_1, MC_2, and MC_3. All storage addresses inside MC_0 are addresses modulo 4 = 0, all storage addresses inside MC_1 are addresses modulo 4 = 1, all storage addresses inside MC_2 are addresses modulo 4 = 2, and all storage addresses inside MC_3 are addresses modulo 4 = 3.
[0068] like Figure 4 As shown, the coefficient memory MC includes a base address register MB. The addressing of the coefficient memory MC adopts the base address register MB+immediate number mode. For accessing the coefficient memory MC, only the immediate number needs to be specified, and the base address register MB+immediate number will be used as the initial access address, and the subsequent three addresses will be accessed continuously.
[0069] The bit width of the base address register MB is log2 (the depth of the coefficient memory MC). If the depth of the coefficient memory MC is 256, the bit width of the base address register MB is 8 bits.
[0070] like Figure 4 As shown, the immediate value IMM encoded by the software instruction is 4, and the base address register MB is A, then the hardware directly accesses the corresponding MC[A+4], MC[A+5], MC[A+6], MC[A+7] in MC_0, MC_1, MC_2, and MC_3.
[0071] like Figure 4 As shown, the MC data output by the coefficient memory MC is transmitted to one MC broadcast bus through the first selector MUX1, and is transmitted to another MC broadcast bus through the second selector MUX2. The operation units PE in the same row all obtain the broadcast data from the two broadcast buses.
[0072] The first selector MUX1 and the second selector MUX2 are both 4-to-1 data selectors.
[0073] like Figure 5 As shown, the ACC protocol bus is a protocol tree formed by interconnecting the accumulator registers ACC in the operation units PE in the same column to complete the addition or subtraction operations of the accumulator registers ACC in the operation units PE in the same column.
[0074] like Figure 5 As shown, the reduction tree composed of 16 accumulator registers ACC corresponding to the operation unit PE in the same column is symmetrical from top to bottom, the upper 8 accumulator registers ACC are mirror-symmetrical with the lower 8 accumulator registers ACC, the sequence number of the target accumulator register ACC reduced by the upper 8 accumulator registers ACC is an even number, and the sequence number of the target accumulator register ACC reduced by the lower 8 accumulator registers ACC is an odd number, and the operation results of the upper 8 accumulator registers ACC and the lower 8 accumulator registers ACC are respectively gathered to the accumulator register ACC with the smallest sequence number and the largest sequence number, which is conducive to realizing data reduction;
[0075] The height of the reduction tree is log2 (the number of accumulator registers ACC). If the number of accumulator registers ACC is 2, one accumulation can be completed. Figure 5 To accumulate the 16 accumulation registers ACC, four accumulations are required (represented by ①, ②, ③, and ④ in the figure).
[0076] In the above technical solution, the ACC protocol bus is implemented based on the accumulator register ACC. The accumulator register ACC has a higher data bit width. The ACC protocol bus based on the accumulator register ACC can ensure the calculation accuracy of the intermediate results. In addition, the ACC protocol bus structure has the characteristics of high concurrency, and all accumulator registers ACC can start protocol at the same time.
[0077] In order to better illustrate the technical solution of the present application, the following takes matrix multiplication (expressed as C=A*B, where A and B are input matrices and C is the result matrix) as an example to illustrate the actual implementation process of the technical solution of the present application:
[0078] 1) Data loading: First, load the first column of vector data of matrix A into the local cache MO of a row of operation units PE, and load the first row of vector data of matrix B into the local cache MO of a column of operation units PE;
[0079] 2) Performing vector outer product operation: In the technical solution of the present application, it is equivalent to broadcasting the MO data of a row of operation units PE vertically and broadcasting the MO data of a column of operation units PE horizontally. Each operation unit PE will receive the MO data transmitted by the above row broadcast and column broadcast. The operation unit PE performs multiplication and accumulation operations based on the MO data, and the intermediate results of the operations are stored in the accumulation register ACC;
[0080] 3) Loop execution: Continue to load the second column vector data of matrix A and the second row vector data of matrix B, and perform vector outer product operation as in step 2) above until all vector data in matrix A and matrix B are loaded and executed;
[0081] 4) Data reduction: After completing the above steps, the data stored in the accumulator register ACC in the operation unit PE participating in the operation is each element in the matrix C. If it is necessary to accumulate a column of elements in the matrix C to finally form a row vector, the ACC reduction bus can be used to reduce the data stored in each column of the accumulator register ACC into a result.
[0082] Based on the spatial array processor core computing unit organization form proposed in the technical solution of the present application, matrix multiplication can mobilize all computing units PE to execute during each clock cycle, with the highest execution efficiency. At the same time, all intermediate results are stored in the accumulator register ACC, which can meet the accuracy requirements.
[0083] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A spatial array processor core, characterized in that: It includes operation array PE_Array, arithmetic logic array ALU_Array, register file REG, operation macro Macro, data memory DM and instruction memory IMEM; Operation array PE_Array, an array composed of operation units PE arranged according to the spatial dimension; Arithmetic logic array ALU_Array, an array composed of arithmetic logic units ALU; Register file REG, used for communication between operation array PE_Array and data memory DM, and between arithmetic logic array ALU_Array and data memory DM; The operation macro Macro is composed of the operation array PE_Array, the arithmetic logic array ALU_Array and the register file REG. The operation macros Macro form a ring interconnection structure through the inter-macro data transmission channel; Data memory DM is a private data storage space for each operation macro Macro; The instruction memory IMEM is used to store the execution instructions of the processor core. The program counter drives the core instruction fetch module to access the instruction memory IMEM. The decoding module completes the instruction decoding. The execution module completes the instruction execution task according to the instruction decoding result. The computing units PE in the computing array PE_Array communicate with each other via the MO broadcast bus, the MC broadcast bus and the ACC protocol bus.
2. The spatial array processor core according to claim 1, characterized in that: The operation unit PE includes a multiplier MUL, an adder ADD, a truncation unit CUT, an accumulator register ACC and a local cache MO. The operation unit PE can perform operations using the local cache MO to store data or the MO data transmitted by the MO broadcast bus. The intermediate results of the operations are cached in the accumulator register ACC, or written into the local cache MO after being truncated by the truncation unit CUT.
3. The spatial array processor core according to claim 2, characterized in that: The MO broadcast bus includes a MO row broadcast bus and a MO column broadcast bus. The operation units PE located in the same row share MO data through the MO row broadcast bus, and the operation units PE located in the same column share MO data through the MO column broadcast bus. The MC broadcast bus is used for the computing units PE in the same row to share a coefficient memory MC, and the coefficient memory MC broadcasts MC data to the computing units PE in the same row; The ACC protocol bus is a protocol tree formed by interconnecting the accumulator registers ACC in the operation units PE in the same column to complete the addition or subtraction operations of the accumulator registers ACC in the operation units PE in the same column.
4. The spatial array processor core according to claim 3, characterized in that: Each of the operation arrays PE_Array is composed of 16*16, a total of 256 operation units PE arranged according to the spatial dimension; The operation macro Macro includes a first operation macro X, a second operation macro Y, a third operation macro Z, and a fourth operation macro T. The processor core includes 4*16*16, a total of 1024 operation units PE; The data memory DM includes a first data memory DM1, a second data memory DM2, a third data memory DM3, and a fourth data memory DM4, which are private data storage spaces of the first operation macro X, the second operation macro Y, the third operation macro Z, and the fourth operation macro T respectively.
5. The spatial array processor core according to claim 4, characterized in that: The bit width of the MO row broadcast bus depends on the number of operation units PE participating in the row broadcast at the same time. Each operation array PE_Array contains 16 operation units PE in one row, and the number of operation units PE participating in the row broadcast at the same time is 4. Each operation unit PE sends local MO data to 4 broadcast buses and selects 1 broadcast data from the 4 broadcast buses as an operand. Therefore, each operation unit PE is a 4-transmit 1-receive structure on the MO row broadcast bus. The bit width of the MO column broadcast bus depends on the number of operation units PE participating in the column broadcast at the same time. Each column in the operation array PE_Array contains 16 operation units PE, and the number of operation units PE participating in the column broadcast at the same time is 4. Each of the operation units PE sends local MO data to 4 broadcast buses and selects 1 broadcast data from these 4 broadcast buses as an operand. Therefore, each of the operation units PE on the MO column broadcast bus is also a 4-transmit 1-receive structure.
6. The spatial array processor core according to claim 4, characterized in that: The coefficient memory MC is composed of 4 static random access memory cells SRAM, which are interleavedly addressed; Among them, the four static random access memory cells SRAM are MC_0, MC_1, MC_2, and MC_3. All storage addresses inside MC_0 are addresses modulo 4 = 0, all storage addresses inside MC_1 are addresses modulo 4 = 1, all storage addresses inside MC_2 are addresses modulo 4 = 2, and all storage addresses inside MC_3 are addresses modulo 4 = 3.
7. The spatial array processor core according to claim 6, characterized in that: The coefficient memory MC includes a base address register MB. The coefficient memory MC is addressed by the base address register MB+immediate number. To access the coefficient memory MC, only the immediate number needs to be specified. The base address register MB+immediate number will be used as the initial access address, and the subsequent three addresses will be accessed continuously. The bit width of the base address register MB is log2 (the depth of the coefficient memory MC).
8. The spatial array processor core according to claim 7, characterized in that: The MC data output by the coefficient memory MC is transmitted to one MC broadcast bus through the first selector MUX1, and is transmitted to another MC broadcast bus through the second selector MUX2. The operation units PE in the same row all obtain the broadcast data from the two broadcast buses. The first selector MUX1 and the second selector MUX2 are both 4-to-1 data selectors.
9. The spatial array processor core according to claim 4, characterized in that: The reduction tree composed of 16 accumulator registers ACC corresponding to the operation unit PE in the same column is symmetrical in the upper and lower parts, the upper 8 accumulator registers ACC are mirror-symmetrical with the lower 8 accumulator registers ACC, the sequence number of the target accumulator register ACC reduced by the upper 8 accumulator registers ACC is an even number, and the sequence number of the target accumulator register ACC reduced by the lower 8 accumulator registers ACC is an odd number, and the operation results of the upper 8 accumulator registers ACC and the lower 8 accumulator registers ACC are respectively gathered to the accumulator register ACC with the smallest sequence number and the largest sequence number, which is conducive to realizing data reduction; The height of the reduction tree is log2 (the number of accumulator registers ACC).