Test method for realizing automatic chip configuration of FPGA (Field Programmable Gate Array) by sending instruction through serial port

Abstract

The invention relates to a test method for realizing automatic chip configuration of an FPGA (Field Programmable Gate Array) by sending an instruction through a serial port, which comprises the following steps of: mutually connecting an FPGA development board and a certain type of clock generator test circuit board, building a hardware platform, sending an instruction through a serial port debugging assistant, controlling the FPGA to work to read and write a chip, and realizing one-key configuration of the certain type of clock generator chip. The computer is connected with the FPGA development board and the chip test circuit board according to the schematic of the hardware connection diagram, and a hardware platform is built; wherein the FPGA judges a frame header. According to the test method for the FPGA automatic configuration chip, a selected hardware platform is an FPGA development board, control ports of various types of chip test circuit boards can be interconnected with IO ports of the FPGA in a jumper mode, the platform building operation is simple, and a large amount of hardware cost is saved; the control instruction is sent through one key, so that the FPGA immediately completes chip function configuration, the debugging time is saved, and the debugging efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing and development, in particular to a testing method for implementing FPGA automatic chip configuration by sending instructions through a serial port. Background Art

[0002] In modern chip testing, the quickest and most effective way to configure a chip is to use a set of software and hardware configuration platforms provided by the official software and generate the parameters to be configured in the computer. With one-click control, the hardware connected to the computer configures the chip, writes the parameters of each register of the chip, and the chip starts working according to the parameters. For example, if you want a clock chip to output a certain frequency, output format, input clock, etc., enter these parameters into the official software, which can automatically generate a configuration table, and then click Write All Registers to start controlling the supporting hardware, and write the parameters in the configuration table into the clock chip in turn. The chip immediately implements the configuration of the specified parameters and starts working at the specified frequency, format, and other requirements. Sometimes during online debugging, if a parameter is changed, the software automatically rewrites the register parameters of the segment to achieve fast configuration. This configuration method is commonly used by chip design and manufacturing units.

[0003] However, in actual applications, the supporting hardware provided by various chip design and manufacturing units varies greatly and is expensive. The method of using chip application customers is to use controllers such as FPGA or single-chip microcomputers to interconnect with the control port of the chip, develop programs, and automatically generate the register parameters of the configuration table by the official configuration software, and write them into the chip in sequence to realize the configuration. When encountering uncertain parameters, repeated debugging and compilation are required, which greatly affects the debugging efficiency. For application customers, how to unify the hardware platform, integrate existing resources, and realize rapid debugging of chip performance has become a problem that needs to be solved urgently. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a test method for sending instructions through a serial port to realize automatic configuration of an FPGA chip. The test method uses an FPGA development board and a certain type of clock generator test circuit board to interconnect, builds a hardware platform, sends instructions through a serial port debugging assistant, controls the FPGA to read and write the chip, and realizes one-key configuration of a certain type of clock generator chip, including the following steps:

[0005] Step S1: After the hardware environment is built, download the FPGA test control program, reset the software, and start configuring the chip so that the chip works in the initial default state. After the configuration is completed, the FPGA automatically sends a register read instruction and sends data to the serial port. The serial port debugging assistant will display the data written to each register of the chip;

[0006] Step S2: In the official chip configuration software, change a parameter, the software automatically calculates, and prompts that relevant parameter data has been written to one or more registers;

[0007] Step S3: Enter "WRITE XXXXXXXX" in the sending interface of the serial port debugging assistant, and click the "Send" button to send the command to the FPGA through the serial port. The FPGA writes the command to the chip according to the communication protocol to implement configuration writing;

[0008] Step S4: Enter "READ XXXXXXXX" in the sending interface of the serial port debugging assistant and click the "Send" button to send the command to the FPGA through the serial port. The FPGA writes the command to the chip according to the communication protocol to realize configuration readback.

[0009] Step S5: After a single parameter is changed, after writing the data of this part of the register, it does not reach the expected state, and all registers need to be rewritten; enter "WRITEALL" in the sending interface of the serial port debugging assistant, click the "Send" button, and then send the instruction to the FPGA through the serial port. The FPGA writes the refreshed data of each address register into each address of the chip in turn to achieve rewriting; after the writing is completed, the FPGA sends a group of data to the serial port, such as "D0AE D0AE", indicating that the operation is completed;

[0010] Step S6: Enter "READALL" in the sending interface of the serial port debugging assistant and click the "Send" button to send the command to the FPGA through the serial port. The FPGA automatically sends a register read command to read the data of each address in turn and send the data to the serial port. The serial port debugging assistant will display the data written to each register of the chip.

[0011] In one embodiment of the present invention, the order of steps S3 to S6 is arbitrarily combined, and the design is to write first or read first. The FPGA only responds to instructions. If no write operation is performed on certain registers and "WRITE ALL" is sent directly, the default state is rewritten.

[0012] In one embodiment of the present invention, after the instructions are sent in steps S3 to S6, the FPGA can respond quickly because the FPGA can effectively identify the frame header. The specific steps of the identification algorithm are:

[0013] Step I: After clicking the "Send" button, the frame data is sent to the FPGA in bytes through the serial port. The baud rate is 115200, the data transmission time per bit is 8.68us, and the data transmission time per byte is about 100us;

[0014] Step II, when there is data received, FPGA triggers the receive valid bit, and then counts during this period. If there is new byte data received, the timing is reset, otherwise it is automatically incremented. If the timing is greater than 20ms, it indicates that there is no new data received, the frame data reception is completed, and the frame data is cached;

[0015] Step III, FPGA judges the frame header. If the frame header is "WRITE", the subsequent data is written to the byte. If the frame header is "READ", the subsequent data is read from the byte. If a frame of data is "WRITEALL", all registers are rewritten. If a frame of data is "READALL", the values ​​of all registers are read in sequence. If these frame headers are not met, it is considered invalid data and returns to wait for new data to be received.

[0016] The above technical solution of the present invention has the following advantages compared with the prior art:

[0017] (1) The FPGA automatic configuration chip testing method described in the present invention uses an FPGA development board as the hardware platform. Through jumpers, the control ports of various chip test circuit boards can be interconnected with the IO ports of the FPGA. The platform construction operation is simple, saving a lot of hardware costs.

[0018] (2) The present invention sends instructions through a serial port debugging assistant, which is simple to operate, highly adaptable, and suitable for use by engineering personnel.

[0019] (3) The present invention sends control instructions with one click, allowing FPGA to immediately complete chip function configuration, which greatly saves debugging time and greatly improves debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0021] Figure 1 This is a schematic diagram of the present invention of sending instructions through a serial port to implement automatic configuration of an FPGA chip.

[0022] Figure 2 The present invention is a flow chart of the FPGA receiving serial port data and making judgments.

[0023] Figure 3 It is the serial port data sending and receiving display interface of the present invention. DETAILED DESCRIPTION

[0024] like Figure 1As shown, this embodiment provides a test method for sending serial port instructions to realize automatic configuration of FPGA chip. The test method uses the interconnection of FPGA development board and a certain type of clock generator test circuit board to build a hardware platform, sends instructions with a serial port debugging assistant, controls the FPGA work to read and write the chip, realizes one-key configuration of a certain type of clock generator chip, and interconnects the computer with the FPGA development board and the chip test circuit board according to the hardware connection diagram to build a hardware platform. After downloading the program, it starts to run automatically, including the following steps:

[0025] ① Set parameters to enable the chip configuration software to generate configuration data.

[0026] ② Enter the command in the serial debugging assistant sending interface and send it to the FPGA development board through the serial port. The FPGA control chip works and writes the configuration data.

[0027] ③After configuration is completed, FPGA reads the data written into each register of the chip.

[0028] ④FPGA transmits the read chip register value to the computer through the 232 serial port and displays and prints it.

[0029] See Figure 2 , the algorithm for FPGA to receive serial port data and make judgment in step ② is as follows:

[0030] I. After receiving the serial port data, FPGA starts timing. If the timing is greater than 20ms, the frame data is received and cached.

[0031] II. FPGA judges the frame header. If the frame header is "WRITE", the subsequent data is written to the byte. If the frame header is "READ", the subsequent data is read from the byte. If a frame of data is "WRITEALL", all registers are rewritten. If a frame of data is "READALL", the values ​​of all registers are read in sequence. If these frame headers are not met, it is considered invalid data and returns to wait for new data to be received.

[0032] III. After completing each write or read operation, the current operation ends and waits for the next instruction to be received.

[0033] See Figure 3 , which is the display of sending and receiving data on the serial port debugging assistant interface. Enter "WRITE00020017" in the sending interface and click the "Send" button. FPGA starts to automatically configure the chip. After the configuration is completed, the display interface shows the data read after configuration, "00020017".

[0034] The test method for the FPGA automatic configuration chip described in this embodiment is to control the FPGA to read and write the chip by sending instructions using a serial port debugging assistant, specifically focusing on judging the frame header.

[0035] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A test method for sending instructions through a serial port to realize automatic configuration of an FPGA chip. The test method uses an FPGA development board and a certain type of clock generator test circuit board to interconnect, builds a hardware platform, uses a serial port debugging assistant to send instructions, controls the FPGA to read and write the chip, and realizes one-key configuration of a certain type of clock generator chip, characterized in that: The steps include: Step S1: After the hardware environment is built, download the FPGA test control program, reset the software, and start configuring the chip so that the chip works in the initial default state. After the configuration is completed, the FPGA automatically sends a register read instruction and sends data to the serial port. The serial port debugging assistant will display the data written to each register of the chip; Step S2: In the official chip configuration software, change a certain parameter, the software automatically calculates, and prompts that relevant parameter data has been written to one or more registers; Step S3: Enter "WRITE XXXXXXXX" in the sending interface of the serial port debugging assistant, and click the "Send" button to send the command to the FPGA through the serial port. The FPGA writes the command to the chip according to the communication protocol to implement configuration writing; Step S4: Enter "READ XXXXXXXX" in the serial port debugging assistant sending interface, and click the "Send" button to send the command to the FPGA through the serial port. The FPGA writes the command to the chip according to the communication protocol to realize configuration readback; Step S5: After a single parameter is changed, after writing the data of this part of the register, it does not reach the expected state, and all registers need to be rewritten; enter "WRITEALL" in the sending interface of the serial port debugging assistant, click the "Send" button, and the command will be sent to the FPGA through the serial port. The FPGA will write the refreshed data of each address register into each address of the chip in turn to achieve rewriting; after the writing is completed, the FPGA sends a group of data to the serial port, such as "D0AE D0AE", indicating that the operation is completed; Step S6: Enter "READALL" in the serial port debugging assistant sending interface and click the "Send" button to send the command to the FPGA through the serial port. The FPGA automatically sends a register read command to read the data of each address in turn and send the data to the serial port. The serial port debugging assistant will display the data written to each register of the chip.

2. The method for testing an FPGA automatic configuration chip according to claim 1, wherein: The order of steps S3 to S6 can be combined arbitrarily, and the design is to write first or read first. The FPGA only responds to instructions. If no write operation is performed on certain registers and "WRITE ALL" is sent directly, the default state is rewritten.

3. The method for testing an FPGA automatic configuration chip according to claim 2, wherein: After the instructions are sent in steps S3 to S6, the FPGA can respond quickly because the FPGA can effectively identify the frame header. The specific steps of the identification algorithm are: Step I: After clicking the "Send" button, the frame data is sent to the FPGA in bytes through the serial port. The baud rate is 115200, the data transmission time per bit is 8.68us, and the data transmission time per byte is about 100us; Step II, when there is data received, FPGA triggers the receive valid bit, and then counts during this period. If there is new byte data received, the timing is reset, otherwise it is automatically incremented. If the timing is greater than 20ms, it indicates that there is no new data received, the frame data reception is completed, and the frame data is cached; Step III, FPGA judges the frame header. If the frame header is "WRITE", the subsequent data is written to the byte. If the frame header is "READ", the subsequent data is read from the byte. If a frame of data is "WRITEALL", all The register is rewritten. If a frame of data is "READALL", the values ​​of all registers are read in sequence. If these frame headers are not met, If it is invalid data, it returns and waits for new data to be received.

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