Distributed acquisition system based on network-on-chip

Abstract

The invention discloses a distributed acquisition system based on a network-on-chip, each master node is connected with four slave nodes, each slave node is responsible for acquiring one path of waveform data after clock synchronization of each node, and then multiple paths of sampling data are sent to the master node through an optical fiber link; and each main node carries out data processing and synthesis on the received four paths of sampling data, and finally uploads the spliced waveform data to a display for waveform display.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-speed data acquisition, and more specifically, relates to a distributed acquisition system based on a network on a chip. Background Art

[0002] Data acquisition is a comprehensive application technology with signal measurement, sensors and computers as the core, and is an important branch of modern information science. For early data acquisition, due to the immaturity of sensor technology and analog-to-digital conversion technology, it can only perform simple acquisition and processing on analog signals. However, with the gradual maturity of sensor technology and analog-to-digital conversion technology, multi-channel data acquisition has begun to appear, with more and more acquisition channels, larger signal volume, and higher accuracy requirements.

[0003] For large-scale and long-distance data transmission, if the traditional centralized data acquisition system is used, the multiple groups of long transmission distance signal lines used will not only interfere with the analog signal, but also fail to ensure the real-time transmission of the data. The distributed data acquisition system can avoid these problems.

[0004] The distributed data acquisition system distributes multiple acquisition modules near each test point. Each acquisition module collects data from the corresponding test point and finally transmits the data back to the host through the transmission line. In order to realize the real-time acquisition, testing and control of the entire distributed data acquisition system, each acquisition module needs to maintain high-precision clock synchronization, and the requirements for synchronization accuracy are constantly increasing with the development of science and technology. Therefore, the core technology of the distributed data acquisition system is the clock synchronization and real-time transmission of data.

[0005] With the development of A / D converters and sensor technology, multi-channel data acquisition systems began to appear, and the scale of data acquisition gradually increased. Large-scale data acquisition systems have the characteristics of multiple acquisition channels, large signal volume, and high precision requirements. They are generally divided into three types: centralized, distributed, and distributed. Compared with traditional centralized data acquisition systems and distributed data acquisition systems, distributed data acquisition systems have the advantages of high efficiency and good scalability. Distributed data acquisition systems began to appear in the 1980s. It is a system in which multiple independent devices collect sensor signals on site, and then transmit the collected data to the back-end host computer through a communication network for analysis and processing. Distributed data acquisition systems integrate hardware technology, computer software technology, communication technology, redundancy technology and other technologies. They are often used in scenarios with a large number of sensors, a wide spatial distribution range, and high data bandwidth, such as marine scientific research, ocean exploration, earthquake monitoring, industrial control and other fields.

[0006] The network-on-chip (NoC) technology has greatly improved the versatility of the entire system design and facilitated the flexible expansion of the overall system. Compared with the system-on-chip (SoC) technology, its main advantages are as follows: NoC technology is a structural form based on network topology, so each network node can work independently and can achieve multi-task parallel processing capabilities to a greater extent; NoC separates the two functions of computing and communication, which solves the problem that the original system can only be reused as computing units, so that computing and communication units can be reused at the same time, greatly enhancing the reusability of the system; the network-on-chip is easy to expand. In theory, there is no upper limit to the expandable data acquisition channels, so the maximum number of terminals that can support access to the network can be determined by the number of data acquisition channel interfaces. Therefore, it is an excellent choice to apply the network-on-chip to the distributed data acquisition system. Summary of the invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a distributed acquisition system based on an on-chip network, which collects data in parallel under the clock synchronization of the distributed acquisition system and has the advantages of high acquisition efficiency and good scalability.

[0008] To achieve the above-mentioned object of the invention, the present invention provides a distributed acquisition system based on a network on a chip, characterized by comprising: n master nodes and 4n slave nodes;

[0009] Each master node is connected to four slave nodes. After the clocks of each node are synchronized, each slave node is responsible for collecting one channel of waveform data, and then sending multiple channels of sampled data to the master node through the optical fiber link. Each master node processes and synthesizes the received four channels of sampled data, and finally uploads the spliced ​​waveform data to the display for waveform display.

[0010] At the same time, the distributed acquisition system based on the on-chip network of the present invention also has the following beneficial effects:

[0011] (1) The high-speed data acquisition technology based on the on-chip network of the present invention breaks through the key technologies such as the on-chip network architecture based on high-performance FPGA, off-chip A / D acquisition, gain error, offset error and phase error processing algorithm, high-throughput non-congestion data transmission routing, high-speed transmission interface, multi-channel sampling data time mismatch and correction;

[0012] (2) The present invention takes advantage of the on-chip network to build a distributed data acquisition system, which is mainly to reduce the delay in data transmission between networks and reduce the power consumption of the entire distributed system;

[0013] (3) The clock synchronization of the distributed acquisition system based on the on-chip network is the key to the synchronous acquisition of each slave node. The present invention mainly completes the clock synchronization relationship between the master node and the slave node by means of radio frequency optical fiber transmission. The clock signal is converted into an optical signal by means of electro-optical conversion. The master node and the slave node are connected by optical fiber to transmit the reference clock signal to the acquisition system of the slave node. The acquisition system of the slave node builds a local sampling clock system based on the reference clock signal to complete the remote synchronization relationship between the local sampling clock of the slave node and the working clock system of the master node.

[0014] (4) The master node control system of the present invention integrates an ARM chip, and multiple user communication interfaces, such as network ports, optical fibers, etc., can be expanded on the board-level system. The server side can complete the issuance of control instructions or the upload of data of interest through the communication interface. The remote server side can control each slave node via ARM, and the collected data from the slave node can be transmitted to the server via Ethernet on the ARM side; at the same time, more remote collection nodes can be expanded to complete a richer distributed collection system network. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a diagram of the architecture of a distributed acquisition system based on an on-chip network of the present invention;

[0016] Figure 2 It is a diamond topology diagram of master and slave nodes;

[0017] Figure 3 This is the internal structure diagram of the master node router;

[0018] Figure 4 This is the internal structure diagram of the child node router. DETAILED DESCRIPTION

[0019] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0020] Example

[0021] Figure 1 This is an architecture diagram of the distributed acquisition system based on on-chip network of the present invention.

[0022] In this embodiment, if Figure 1As shown, the present invention is a distributed acquisition system based on an on-chip network, including: 16 slave nodes and 4 master nodes; in this embodiment, the data acquisition master node has a storage depth of 4Gpts, and the sampling rate gradually decreases when multiple slave nodes work simultaneously. When 16 slave nodes work simultaneously, the slave node sampling rate is 250MSPS, the storage depth is 250Mpts, the vertical resolution is 12bit and other indicators of the distributed acquisition system.

[0023] In the design of network nodes, common topological structures include 2D-Mesh, 3D-Mesh, 2D-Torus and other forms. This invention mainly studies the design of 20 network nodes based on the 2D topological structure and designs the master-slave node diamond topological structure, such as Figure 2 As shown in the figure, under this topology, the number of on-chip network nodes is 20, of which the main control board has 4 nodes, which are master nodes and are mainly responsible for sending synchronization information and control information to each slave node, and receiving data sent by each sub-node; each of the 4 data acquisition sub-cards has 4 nodes, which are slave nodes and are mainly responsible for ADC acquisition control; each master node is connected to four slave nodes, and after the clocks of each node are synchronized, each slave node is responsible for collecting one channel of waveform data, and then sending multiple channels of sampling data to the master node through the optical fiber link, and each master node processes and synthesizes the received four channels of sampling data, and finally uploads the spliced ​​waveform data to the display for waveform display.

[0024] In this embodiment, the data acquisition principle is the same as that of an ordinary digital oscilloscope, and the signal conditioning channel, ADC, trigger control module and memory are used to complete the acquisition and storage of analog waveform signals; therefore, the master node will continuously receive the sampled data stream transmitted by the slave node, and perform data analysis in the slave node. The master node mainly completes the extraction of characteristic information of different slave node data, various parameter measurements and calculations, and can complete mathematical operations between different node signals, including addition, subtraction, multiplication, division and FFT functions. At the same time, the calculated data and the original collected data can be sent to the display for display.

[0025] The input signal conditioned by the signal conditioning channel output is sent to the ADC for analog-to-digital conversion. The obtained sampled data stream is stored in the memory controlled by the trigger control module in the FPGA, and then the stored data is sent to the 10 Gigabit Ethernet interface module; the master node transmits the sampled data stream sent by the slave node via 10 Gigabit Ethernet to the ARM end to analyze and process the data and realize waveform display.

[0026] In this embodiment, if Figure 1 As shown, the master node includes: 10G optical fiber, SoC chip integrating FPGA and ARM, clock source, electro-optical conversion module, optical splitter, display and peripheral interface;

[0027] In this embodiment, the internal structure of the master node router is as follows: Figure 3 As shown in the figure, there are five channels in the master node router, including east, west, south, north and local channels. The east, west, south and north data channels are used to receive data transmitted from the sub-node routers during operation, while the local channel of the master node is used for data transmission, and the data is sent to the back stage for processing through the channel. At the same time, the master node data can be transmitted to the remote server through the 10G network. The remote server can build a program control software to control each sub-node and receive the collected data from each sub-node.

[0028] The 10 Gigabit optical fiber is interconnected with the slave nodes and is mainly responsible for receiving the collected data from the slave nodes and issuing control commands from the master node. The 10 Gigabit optical fiber logically implements the physical layer and protocol layer of the 10 Gigabit Ethernet protocol, demodulates the optical signal into an electrical signal through the 10 Gigabit optical fiber, and inputs the electrical signal into the SoC chip to complete the interactive channel function of data and commands.

[0029] The SoC chip serves as the controller of the entire distributed acquisition system, which integrates two parts: FPGA and ARM. FPGA is mainly used for the logical implementation of the physical layer and MAC layer of the 10G interface, completes the data decoding and mapping process, and transmits the acquired data from the slave node to the cache FIFO of the master node for the next data processing process. In the logical implementation of FPGA, it has the function of data recognition and mapping, and stores the data in different cache FIFOs according to the data of different slave nodes. ARM is mainly used for the display and processing of acquired data, including parameter operations of time measurement parameters, voltage measurement parameters and other data, as well as waveform operation functions, such as addition, subtraction, multiplication, division and FFT functions; the acquisition control process is implemented on the ARM side, including controlling the acquisition status of each node and the acquisition data acquisition process of each node.

[0030] The ARM side runs the Linux system, and builds the human-computer interaction interface of the distributed acquisition system in the Linux system, which displays the data acquisition waveform of each node, the working status of each node, and the results of data processing and analysis. The interactive function of the display screen and the mouse and keyboard is completed by driving the USB interface and HDMI interface through ARM.

[0031] There are two types of data communication between FPGA and ARM: AXI-Stream interface for large-capacity data transmission and AXI-Bram-Lite interface for control command interaction, which respectively complete the fast upload of slave node data and the issuance of acquisition process commands and status reading back.

[0032] The clock source, electro-optical conversion module, and optical splitter constitute the clock system of the master node. The clock source provides a high-precision, low-temperature drift reference clock signal for the entire test system, and provides the working clock of the master node and the reference clock of the slave node. The electro-optical conversion module mainly completes the modulation function of the electrical signal and the optical signal. It receives the clock signal provided by the clock source, and converts it into the output of the modulated optical signal using the radio frequency fiber conversion technology. The optical splitter mainly divides a single-channel optical modulated signal into multiple channels according to the number of test nodes. In order to ensure the power and phase relationship of the input and output matching, the power adjustment and phase shifting functions of the optical splitter can be used to complete the stable output of the modulated optical signal. Finally, the modulated optical signal is transmitted to the slave node using the optical signal output terminal to complete the outward transmission process of the reference clock signal, that is, the clock synchronization process.

[0033] The display and peripherals mainly include a display with HDMI and a mouse and keyboard with USB interface.

[0034] In this embodiment, if Figure 1 As shown, the slave node includes: an analog channel, an analog-to-digital converter ADC, a field programmable logic device FPGA, a memory, a 10G optical fiber, an optoelectronic conversion module and a clock module;

[0035] In this embodiment, the internal structure of the subnode router is as follows: Figure 4 As shown, the sub-node is generally used as a data acquisition node to mount an external ADC, to control the ADC and receive data sent by the ADC. The sub-node, as a routing node for mounting the ADC, only receives data information from the main node, so this route can be designed to have an information channel with only one direction.

[0036] The input signal is first conditioned by the signal conditioning channel, and then converted by the ADC to obtain a digital signal. In FPGFA, the ADC's collected data is first demapped, and the high-speed serial signal is transformed into low-speed parallel data. Then, the parallel data is sampled according to the sampling requirements sent by the master node. At the same time, the trigger signal extraction process of the digital trigger model is completed in the trigger logic module for the parallel data. After a valid trigger signal is identified, the storage operation of the memory is completed, that is, the waveform capture after a trigger is completed, and then the SoC chip of the master node is notified to extract the collected trigger data. Then, the stored waveform data is mapped and input into the 10 Gigabit optical fiber.

[0037] The main function of 10 Gigabit optical fiber is to upload the collected data of the slave node to the master node, receive the collection control commands from the master node and feedback the collection status information of the slave node to the master node; the slave node 10 Gigabit optical fiber module is also divided into two parts. The hardware is a 10 Gigabit optical module, which completes the modulation process of electrical and optical signals. Logically, it is the processing process of the 10 Gigabit Ethernet protocol, which is divided into physical layer and protocol layer.

[0038] The photoelectric conversion module and the clock module (phase-locked loop) constitute the clock system of the slave node, providing a clock source for the sampling system and control logic. The photoelectric conversion module receives the modulated optical signal transmitted by the clock system of the master node through the optical fiber, converts it into an electrical signal using the photoelectric demodulation technology, and completes the RF optical fiber transmission process of the reference clock signal. The clock module mainly involves a multi-stage phase-locked loop circuit. The clock reference of the phase-locked loop circuit comes from the clock signal demodulated by the optical / electrical conversion module. According to the basic principle of the phase-locked loop circuit, the necessary clock signal can be generated according to user needs and output to the logic working module of the test node. In addition, the phase-locked loop circuit can adjust the phase of each output clock to compensate for the phase offset during the RF optical fiber transmission process. Finally, the clock signal is output to each ADC and FPGA. Under clock synchronization, the FPGA simultaneously controls each ADC to collect data.

[0039] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A distributed acquisition system based on a network on chip, characterized in that: include: n master nodes and 4n slave nodes; Each master node is connected to four slave nodes. After the clocks of each node are synchronized, each slave node is responsible for collecting one channel of waveform data, and then sending multiple channels of sampled data to the master node through the optical fiber link. Each master node processes and synthesizes the received four channels of sampled data, and finally uploads the spliced ​​waveform data to the display for waveform display.

2. The distributed acquisition system based on network on chip according to claim 1, characterized in that: The master node includes: 10G optical fiber, SoC chip integrating FPGA and ARM, clock source, electro-optical conversion module, optical splitter, display and peripheral interface; The 10 Gigabit optical fiber is interconnected with the slave node, and is mainly responsible for receiving the collected data from the slave node and issuing the control command of the master node; the 10 Gigabit optical fiber logically implements the physical layer and protocol layer of the 10 Gigabit Ethernet protocol, demodulates the optical signal into an electrical signal through the 10 Gigabit optical fiber, and inputs the electrical signal into the SoC chip to complete the interactive channel function of data and commands; The SoC chip serves as the controller of the entire distributed acquisition system, integrating FPGA and ARM. Among them, FPGA is mainly used for the logical implementation of the physical layer and MAC layer of the 10G interface, completing the data decoding and mapping process, transmitting the collected data from the slave node to the cache FIFO of the master node, and the data of different slave nodes are stored in different cache FIFOs for the next data processing process. ARM runs the Linux system, and builds the human-computer interaction interface of the distributed acquisition system in the Linux system. The interactive functions of the display screen and the mouse and keyboard are completed through ARM-driven USB and HDMI interfaces. ARM is mainly used for displaying and processing the acquired data. There are two types of data communication between FPGA and ARM: AXI-Stream interface for large-capacity data transmission and AXI-Bram-Lite interface for control command interaction, which respectively complete the fast upload of slave node data and the issuance of acquisition process commands and status reading back process; The clock source, the electro-optical conversion module, and the optical splitter constitute the clock system of the master node. The clock source provides a high-precision, low-temperature drift reference clock signal for the entire test system, and provides the working clock of the master node and the reference clock of the slave node; the electro-optical conversion module mainly completes the modulation function of the electrical signal and the optical signal, and receives the clock signal provided by the clock source, and then converts it into a modulated optical signal; the optical splitter divides a single-channel modulated optical signal into multiple channels according to the number of test nodes, and completes the power and phase shift adjustment after the splitting, so that the modulated optical signal can be output stably; finally, the modulated optical signal is transmitted to the slave node using the optical signal output terminal to complete the reference clock synchronization; The display and peripherals mainly include a display screen with HDMI and a mouse and keyboard with USB interfaces.

3. The distributed acquisition system based on network on chip according to claim 1, characterized in that: The slave node includes: an analog channel, an analog-to-digital converter ADC, a field programmable logic device FPGA, a memory, a 10G optical fiber, a photoelectric conversion module and a clock module; The input signal is first conditioned by the signal conditioning channel, and then converted by the ADC to obtain a digital signal. In FPGFA, the ADC's collected data is first demapped, and the high-speed serial signal is transformed into low-speed parallel data. Then, the parallel data is sampled according to the sampling requirements sent by the master node. At the same time, the trigger signal extraction process of the digital trigger model is completed in the trigger logic module for the parallel data. After a valid trigger signal is identified, the storage operation of the memory is completed, that is, the waveform capture after a trigger is completed, and then the SoC chip of the master node is notified to extract the collected trigger data. Then, the stored waveform data is mapped and input into the 10 Gigabit optical fiber. The main function of the 10 Gigabit optical fiber is to upload the collected data of the slave node to the master node, receive the collection control commands from the master node and feedback the collection status information of the slave node to the master node; the slave node 10 Gigabit optical fiber module is also divided into two parts. The hardware is a 10 Gigabit optical module, which completes the modulation process of electrical signals and optical signals. Logically, it is the processing process of the 10 Gigabit Ethernet protocol, which is divided into physical layer and protocol layer. The photoelectric conversion module and the clock module constitute the clock system of the slave node. The photoelectric conversion module receives the modulated optical signal transmitted by the clock system of the master node via the optical fiber, and then converts it into an electrical signal to complete the radio frequency optical fiber transmission process of the reference clock signal. The clock module mainly involves a multi-stage phase-locked loop circuit. The reference clock of the phase-locked loop circuit is derived from the clock signal demodulated by the photoelectric conversion module. The clock signal required by the user is generated according to the basic principle of the phase-locked loop circuit, and then the clock signal is output to each ADC and FPGA. Under clock synchronization, the FPGA simultaneously controls each ADC to collect data.

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